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44 #ifndef __CPU_O3_COMMIT_IMPL_HH__
45 #define __CPU_O3_COMMIT_IMPL_HH__
51 #include "arch/utility.hh"
52 #include "base/loader/symtab.hh"
53 #include "base/cp_annotate.hh"
54 #include "config/the_isa.hh"
55 #include "cpu/checker/cpu.hh"
56 #include "cpu/o3/commit.hh"
57 #include "cpu/o3/thread_state.hh"
58 #include "cpu/base.hh"
59 #include "cpu/exetrace.hh"
60 #include "cpu/timebuf.hh"
61 #include "debug/Activity.hh"
62 #include "debug/Commit.hh"
63 #include "debug/CommitRate.hh"
64 #include "debug/Drain.hh"
65 #include "debug/ExecFaulting.hh"
66 #include "debug/O3PipeView.hh"
67 #include "params/DerivO3CPU.hh"
68 #include "sim/faults.hh"
69 #include "sim/full_system.hh"
74 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
76 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
82 DefaultCommit<Impl>::TrapEvent::process()
84 // This will get reset by commit if it was switched out at the
85 // time of this event processing.
86 commit->trapSquash[tid] = true;
91 DefaultCommit<Impl>::TrapEvent::description() const
97 DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
99 iewToCommitDelay(params->iewToCommitDelay),
100 commitToIEWDelay(params->commitToIEWDelay),
101 renameToROBDelay(params->renameToROBDelay),
102 fetchToCommitDelay(params->commitToFetchDelay),
103 renameWidth(params->renameWidth),
104 commitWidth(params->commitWidth),
105 numThreads(params->numThreads),
107 drainImminent(false),
108 trapLatency(params->trapLatency),
109 canHandleInterrupts(true),
110 avoidQuiesceLiveLock(false)
112 if (commitWidth > Impl::MaxWidth)
113 fatal("commitWidth (%d) is larger than compiled limit (%d),\n"
114 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
115 commitWidth, static_cast<int>(Impl::MaxWidth));
118 _nextStatus = Inactive;
119 std::string policy = params->smtCommitPolicy;
121 //Convert string to lowercase
122 std::transform(policy.begin(), policy.end(), policy.begin(),
123 (int(*)(int)) tolower);
125 //Assign commit policy
126 if (policy == "aggressive"){
127 commitPolicy = Aggressive;
129 DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
130 } else if (policy == "roundrobin"){
131 commitPolicy = RoundRobin;
133 //Set-Up Priority List
134 for (ThreadID tid = 0; tid < numThreads; tid++) {
135 priority_list.push_back(tid);
138 DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
139 } else if (policy == "oldestready"){
140 commitPolicy = OldestReady;
142 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
144 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
145 "RoundRobin,OldestReady}");
148 for (ThreadID tid = 0; tid < numThreads; tid++) {
149 commitStatus[tid] = Idle;
150 changedROBNumEntries[tid] = false;
151 checkEmptyROB[tid] = false;
152 trapInFlight[tid] = false;
153 committedStores[tid] = false;
154 trapSquash[tid] = false;
155 tcSquash[tid] = false;
157 lastCommitedSeqNum[tid] = 0;
158 squashAfterInst[tid] = NULL;
163 template <class Impl>
165 DefaultCommit<Impl>::name() const
167 return cpu->name() + ".commit";
170 template <class Impl>
172 DefaultCommit<Impl>::regProbePoints()
174 ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit");
175 ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall");
176 ppSquash = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Squash");
179 template <class Impl>
181 DefaultCommit<Impl>::regStats()
183 using namespace Stats;
185 .name(name() + ".commitSquashedInsts")
186 .desc("The number of squashed insts skipped by commit")
187 .prereq(commitSquashedInsts);
190 .name(name() + ".commitNonSpecStalls")
191 .desc("The number of times commit has been forced to stall to "
192 "communicate backwards")
193 .prereq(commitNonSpecStalls);
196 .name(name() + ".branchMispredicts")
197 .desc("The number of times a branch was mispredicted")
198 .prereq(branchMispredicts);
201 .init(0,commitWidth,1)
202 .name(name() + ".committed_per_cycle")
203 .desc("Number of insts commited each cycle")
208 .init(cpu->numThreads)
209 .name(name() + ".committedInsts")
210 .desc("Number of instructions committed")
215 .init(cpu->numThreads)
216 .name(name() + ".committedOps")
217 .desc("Number of ops (including micro ops) committed")
222 .init(cpu->numThreads)
223 .name(name() + ".swp_count")
224 .desc("Number of s/w prefetches committed")
229 .init(cpu->numThreads)
230 .name(name() + ".refs")
231 .desc("Number of memory references committed")
236 .init(cpu->numThreads)
237 .name(name() + ".loads")
238 .desc("Number of loads committed")
243 .init(cpu->numThreads)
244 .name(name() + ".membars")
245 .desc("Number of memory barriers committed")
250 .init(cpu->numThreads)
251 .name(name() + ".branches")
252 .desc("Number of branches committed")
257 .init(cpu->numThreads)
258 .name(name() + ".fp_insts")
259 .desc("Number of committed floating point instructions.")
264 .init(cpu->numThreads)
265 .name(name()+".int_insts")
266 .desc("Number of committed integer instructions.")
271 .init(cpu->numThreads)
272 .name(name()+".function_calls")
273 .desc("Number of function calls committed.")
277 statCommittedInstType
278 .init(numThreads,Enums::Num_OpClass)
279 .name(name() + ".op_class")
280 .desc("Class of committed instruction")
281 .flags(total | pdf | dist)
283 statCommittedInstType.ysubnames(Enums::OpClassStrings);
285 commitEligibleSamples
286 .name(name() + ".bw_lim_events")
287 .desc("number cycles where commit BW limit reached")
291 template <class Impl>
293 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
298 template <class Impl>
300 DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
304 // Setup wire to send information back to IEW.
305 toIEW = timeBuffer->getWire(0);
307 // Setup wire to read data from IEW (for the ROB).
308 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
311 template <class Impl>
313 DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
317 // Setup wire to get instructions from rename (for the ROB).
318 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
321 template <class Impl>
323 DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
325 renameQueue = rq_ptr;
327 // Setup wire to get instructions from rename (for the ROB).
328 fromRename = renameQueue->getWire(-renameToROBDelay);
331 template <class Impl>
333 DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
337 // Setup wire to get instructions from IEW.
338 fromIEW = iewQueue->getWire(-iewToCommitDelay);
341 template <class Impl>
343 DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
345 iewStage = iew_stage;
350 DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
352 activeThreads = at_ptr;
355 template <class Impl>
357 DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
359 for (ThreadID tid = 0; tid < numThreads; tid++)
360 renameMap[tid] = &rm_ptr[tid];
363 template <class Impl>
365 DefaultCommit<Impl>::setROB(ROB *rob_ptr)
370 template <class Impl>
372 DefaultCommit<Impl>::startupStage()
374 rob->setActiveThreads(activeThreads);
377 // Broadcast the number of free entries.
378 for (ThreadID tid = 0; tid < numThreads; tid++) {
379 toIEW->commitInfo[tid].usedROB = true;
380 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
381 toIEW->commitInfo[tid].emptyROB = true;
384 // Commit must broadcast the number of free entries it has at the
385 // start of the simulation, so it starts as active.
386 cpu->activateStage(O3CPU::CommitIdx);
388 cpu->activityThisCycle();
391 template <class Impl>
393 DefaultCommit<Impl>::drain()
398 template <class Impl>
400 DefaultCommit<Impl>::drainResume()
402 drainPending = false;
403 drainImminent = false;
406 template <class Impl>
408 DefaultCommit<Impl>::drainSanityCheck() const
411 rob->drainSanityCheck();
414 template <class Impl>
416 DefaultCommit<Impl>::isDrained() const
418 /* Make sure no one is executing microcode. There are two reasons
420 * - Hardware virtualized CPUs can't switch into the middle of a
421 * microcode sequence.
422 * - The current fetch implementation will most likely get very
423 * confused if it tries to start fetching an instruction that
424 * is executing in the middle of a ucode sequence that changes
425 * address mappings. This can happen on for example x86.
427 for (ThreadID tid = 0; tid < numThreads; tid++) {
428 if (pc[tid].microPC() != 0)
432 /* Make sure that all instructions have finished committing before
433 * declaring the system as drained. We want the pipeline to be
434 * completely empty when we declare the CPU to be drained. This
435 * makes debugging easier since CPU handover and restoring from a
436 * checkpoint with a different CPU should have the same timing.
438 return rob->isEmpty() &&
439 interrupt == NoFault;
442 template <class Impl>
444 DefaultCommit<Impl>::takeOverFrom()
447 _nextStatus = Inactive;
448 for (ThreadID tid = 0; tid < numThreads; tid++) {
449 commitStatus[tid] = Idle;
450 changedROBNumEntries[tid] = false;
451 trapSquash[tid] = false;
452 tcSquash[tid] = false;
453 squashAfterInst[tid] = NULL;
458 template <class Impl>
460 DefaultCommit<Impl>::deactivateThread(ThreadID tid)
462 list<ThreadID>::iterator thread_it = std::find(priority_list.begin(),
463 priority_list.end(), tid);
465 if (thread_it != priority_list.end()) {
466 priority_list.erase(thread_it);
471 template <class Impl>
473 DefaultCommit<Impl>::updateStatus()
475 // reset ROB changed variable
476 list<ThreadID>::iterator threads = activeThreads->begin();
477 list<ThreadID>::iterator end = activeThreads->end();
479 while (threads != end) {
480 ThreadID tid = *threads++;
482 changedROBNumEntries[tid] = false;
484 // Also check if any of the threads has a trap pending
485 if (commitStatus[tid] == TrapPending ||
486 commitStatus[tid] == FetchTrapPending) {
487 _nextStatus = Active;
491 if (_nextStatus == Inactive && _status == Active) {
492 DPRINTF(Activity, "Deactivating stage.\n");
493 cpu->deactivateStage(O3CPU::CommitIdx);
494 } else if (_nextStatus == Active && _status == Inactive) {
495 DPRINTF(Activity, "Activating stage.\n");
496 cpu->activateStage(O3CPU::CommitIdx);
499 _status = _nextStatus;
502 template <class Impl>
504 DefaultCommit<Impl>::changedROBEntries()
506 list<ThreadID>::iterator threads = activeThreads->begin();
507 list<ThreadID>::iterator end = activeThreads->end();
509 while (threads != end) {
510 ThreadID tid = *threads++;
512 if (changedROBNumEntries[tid]) {
520 template <class Impl>
522 DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
524 return rob->numFreeEntries(tid);
527 template <class Impl>
529 DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
531 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
533 TrapEvent *trap = new TrapEvent(this, tid);
535 cpu->schedule(trap, cpu->clockEdge(trapLatency));
536 trapInFlight[tid] = true;
537 thread[tid]->trapPending = true;
540 template <class Impl>
542 DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
544 assert(!trapInFlight[tid]);
545 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
547 tcSquash[tid] = true;
550 template <class Impl>
552 DefaultCommit<Impl>::squashAll(ThreadID tid)
554 // If we want to include the squashing instruction in the squash,
555 // then use one older sequence number.
556 // Hopefully this doesn't mess things up. Basically I want to squash
557 // all instructions of this thread.
558 InstSeqNum squashed_inst = rob->isEmpty(tid) ?
559 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
561 // All younger instructions will be squashed. Set the sequence
562 // number as the youngest instruction in the ROB (0 in this case.
563 // Hopefully nothing breaks.)
564 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
566 rob->squash(squashed_inst, tid);
567 changedROBNumEntries[tid] = true;
569 // Send back the sequence number of the squashed instruction.
570 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
572 // Send back the squash signal to tell stages that they should
574 toIEW->commitInfo[tid].squash = true;
576 // Send back the rob squashing signal so other stages know that
577 // the ROB is in the process of squashing.
578 toIEW->commitInfo[tid].robSquashing = true;
580 toIEW->commitInfo[tid].mispredictInst = NULL;
581 toIEW->commitInfo[tid].squashInst = NULL;
583 toIEW->commitInfo[tid].pc = pc[tid];
586 template <class Impl>
588 DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
592 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
594 thread[tid]->trapPending = false;
595 thread[tid]->noSquashFromTC = false;
596 trapInFlight[tid] = false;
598 trapSquash[tid] = false;
600 commitStatus[tid] = ROBSquashing;
601 cpu->activityThisCycle();
604 template <class Impl>
606 DefaultCommit<Impl>::squashFromTC(ThreadID tid)
610 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
612 thread[tid]->noSquashFromTC = false;
613 assert(!thread[tid]->trapPending);
615 commitStatus[tid] = ROBSquashing;
616 cpu->activityThisCycle();
618 tcSquash[tid] = false;
621 template <class Impl>
623 DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
625 DPRINTF(Commit, "Squashing after squash after request, "
626 "restarting at PC %s\n", pc[tid]);
629 // Make sure to inform the fetch stage of which instruction caused
630 // the squash. It'll try to re-fetch an instruction executing in
631 // microcode unless this is set.
632 toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
633 squashAfterInst[tid] = NULL;
635 commitStatus[tid] = ROBSquashing;
636 cpu->activityThisCycle();
639 template <class Impl>
641 DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst)
643 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
644 tid, head_inst->seqNum);
646 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
647 commitStatus[tid] = SquashAfterPending;
648 squashAfterInst[tid] = head_inst;
651 template <class Impl>
653 DefaultCommit<Impl>::tick()
655 wroteToTimeBuffer = false;
656 _nextStatus = Inactive;
658 if (activeThreads->empty())
661 list<ThreadID>::iterator threads = activeThreads->begin();
662 list<ThreadID>::iterator end = activeThreads->end();
664 // Check if any of the threads are done squashing. Change the
665 // status if they are done.
666 while (threads != end) {
667 ThreadID tid = *threads++;
669 // Clear the bit saying if the thread has committed stores
671 committedStores[tid] = false;
673 if (commitStatus[tid] == ROBSquashing) {
675 if (rob->isDoneSquashing(tid)) {
676 commitStatus[tid] = Running;
678 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
679 " insts this cycle.\n", tid);
681 toIEW->commitInfo[tid].robSquashing = true;
682 wroteToTimeBuffer = true;
689 markCompletedInsts();
691 threads = activeThreads->begin();
693 while (threads != end) {
694 ThreadID tid = *threads++;
696 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
697 // The ROB has more instructions it can commit. Its next status
699 _nextStatus = Active;
701 DynInstPtr inst = rob->readHeadInst(tid);
703 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
704 " ROB and ready to commit\n",
705 tid, inst->seqNum, inst->pcState());
707 } else if (!rob->isEmpty(tid)) {
708 DynInstPtr inst = rob->readHeadInst(tid);
710 ppCommitStall->notify(inst);
712 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
713 "%s is head of ROB and not ready\n",
714 tid, inst->seqNum, inst->pcState());
717 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
718 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
722 if (wroteToTimeBuffer) {
723 DPRINTF(Activity, "Activity This Cycle.\n");
724 cpu->activityThisCycle();
730 template <class Impl>
732 DefaultCommit<Impl>::handleInterrupt()
734 // Verify that we still have an interrupt to handle
735 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
736 DPRINTF(Commit, "Pending interrupt is cleared by master before "
737 "it got handled. Restart fetching from the orig path.\n");
738 toIEW->commitInfo[0].clearInterrupt = true;
740 avoidQuiesceLiveLock = true;
744 // Wait until all in flight instructions are finished before enterring
746 if (canHandleInterrupts && cpu->instList.empty()) {
747 // Squash or record that I need to squash this cycle if
748 // an interrupt needed to be handled.
749 DPRINTF(Commit, "Interrupt detected.\n");
751 // Clear the interrupt now that it's going to be handled
752 toIEW->commitInfo[0].clearInterrupt = true;
754 assert(!thread[0]->noSquashFromTC);
755 thread[0]->noSquashFromTC = true;
758 cpu->checker->handlePendingInt();
761 // CPU will handle interrupt. Note that we ignore the local copy of
762 // interrupt. This is because the local copy may no longer be the
763 // interrupt that the interrupt controller thinks is being handled.
764 cpu->processInterrupts(cpu->getInterrupts());
766 thread[0]->noSquashFromTC = false;
768 commitStatus[0] = TrapPending;
770 // Generate trap squash event.
771 generateTrapEvent(0);
774 avoidQuiesceLiveLock = false;
776 DPRINTF(Commit, "Interrupt pending: instruction is %sin "
777 "flight, ROB is %sempty\n",
778 canHandleInterrupts ? "not " : "",
779 cpu->instList.empty() ? "" : "not " );
783 template <class Impl>
785 DefaultCommit<Impl>::propagateInterrupt()
787 // Don't propagate intterupts if we are currently handling a trap or
788 // in draining and the last observable instruction has been committed.
789 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
790 tcSquash[0] || drainImminent)
793 // Process interrupts if interrupts are enabled, not in PAL
794 // mode, and no other traps or external squashes are currently
796 // @todo: Allow other threads to handle interrupts.
798 // Get any interrupt that happened
799 interrupt = cpu->getInterrupts();
801 // Tell fetch that there is an interrupt pending. This
802 // will make fetch wait until it sees a non PAL-mode PC,
803 // at which point it stops fetching instructions.
804 if (interrupt != NoFault)
805 toIEW->commitInfo[0].interruptPending = true;
808 template <class Impl>
810 DefaultCommit<Impl>::commit()
813 // Check if we have a interrupt and get read to handle it
814 if (cpu->checkInterrupts(cpu->tcBase(0)))
815 propagateInterrupt();
818 ////////////////////////////////////
819 // Check for any possible squashes, handle them first
820 ////////////////////////////////////
821 list<ThreadID>::iterator threads = activeThreads->begin();
822 list<ThreadID>::iterator end = activeThreads->end();
824 int num_squashing_threads = 0;
826 while (threads != end) {
827 ThreadID tid = *threads++;
829 // Not sure which one takes priority. I think if we have
830 // both, that's a bad sign.
831 if (trapSquash[tid]) {
832 assert(!tcSquash[tid]);
834 } else if (tcSquash[tid]) {
835 assert(commitStatus[tid] != TrapPending);
837 } else if (commitStatus[tid] == SquashAfterPending) {
838 // A squash from the previous cycle of the commit stage (i.e.,
839 // commitInsts() called squashAfter) is pending. Squash the
841 squashFromSquashAfter(tid);
844 // Squashed sequence number must be older than youngest valid
845 // instruction in the ROB. This prevents squashes from younger
846 // instructions overriding squashes from older instructions.
847 if (fromIEW->squash[tid] &&
848 commitStatus[tid] != TrapPending &&
849 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
851 if (fromIEW->mispredictInst[tid]) {
853 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
855 fromIEW->mispredictInst[tid]->instAddr(),
856 fromIEW->squashedSeqNum[tid]);
859 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
860 tid, fromIEW->squashedSeqNum[tid]);
863 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
865 fromIEW->pc[tid].nextInstAddr());
867 commitStatus[tid] = ROBSquashing;
869 // If we want to include the squashing instruction in the squash,
870 // then use one older sequence number.
871 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
873 if (fromIEW->includeSquashInst[tid]) {
877 // All younger instructions will be squashed. Set the sequence
878 // number as the youngest instruction in the ROB.
879 youngestSeqNum[tid] = squashed_inst;
881 rob->squash(squashed_inst, tid);
882 changedROBNumEntries[tid] = true;
884 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
886 toIEW->commitInfo[tid].squash = true;
888 // Send back the rob squashing signal so other stages know that
889 // the ROB is in the process of squashing.
890 toIEW->commitInfo[tid].robSquashing = true;
892 toIEW->commitInfo[tid].mispredictInst =
893 fromIEW->mispredictInst[tid];
894 toIEW->commitInfo[tid].branchTaken =
895 fromIEW->branchTaken[tid];
896 toIEW->commitInfo[tid].squashInst =
897 rob->findInst(tid, squashed_inst);
898 if (toIEW->commitInfo[tid].mispredictInst) {
899 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
900 toIEW->commitInfo[tid].branchTaken = true;
905 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
908 if (commitStatus[tid] == ROBSquashing) {
909 num_squashing_threads++;
913 // If commit is currently squashing, then it will have activity for the
914 // next cycle. Set its next status as active.
915 if (num_squashing_threads) {
916 _nextStatus = Active;
919 if (num_squashing_threads != numThreads) {
920 // If we're not currently squashing, then get instructions.
923 // Try to commit any instructions.
927 //Check for any activity
928 threads = activeThreads->begin();
930 while (threads != end) {
931 ThreadID tid = *threads++;
933 if (changedROBNumEntries[tid]) {
934 toIEW->commitInfo[tid].usedROB = true;
935 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
937 wroteToTimeBuffer = true;
938 changedROBNumEntries[tid] = false;
939 if (rob->isEmpty(tid))
940 checkEmptyROB[tid] = true;
943 // ROB is only considered "empty" for previous stages if: a)
944 // ROB is empty, b) there are no outstanding stores, c) IEW
945 // stage has received any information regarding stores that
947 // c) is checked by making sure to not consider the ROB empty
948 // on the same cycle as when stores have been committed.
949 // @todo: Make this handle multi-cycle communication between
951 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
952 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
953 checkEmptyROB[tid] = false;
954 toIEW->commitInfo[tid].usedROB = true;
955 toIEW->commitInfo[tid].emptyROB = true;
956 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
957 wroteToTimeBuffer = true;
963 template <class Impl>
965 DefaultCommit<Impl>::commitInsts()
967 ////////////////////////////////////
969 // Note that commit will be handled prior to putting new
970 // instructions in the ROB so that the ROB only tries to commit
971 // instructions it has in this current cycle, and not instructions
972 // it is writing in during this cycle. Can't commit and squash
973 // things at the same time...
974 ////////////////////////////////////
976 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
978 unsigned num_committed = 0;
980 DynInstPtr head_inst;
982 // Commit as many instructions as possible until the commit bandwidth
983 // limit is reached, or it becomes impossible to commit any more.
984 while (num_committed < commitWidth) {
985 // Check for any interrupt that we've already squashed for
986 // and start processing it.
987 if (interrupt != NoFault)
990 ThreadID commit_thread = getCommittingThread();
992 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
995 head_inst = rob->readHeadInst(commit_thread);
997 ThreadID tid = head_inst->threadNumber;
999 assert(tid == commit_thread);
1001 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
1002 head_inst->seqNum, tid);
1004 // If the head instruction is squashed, it is ready to retire
1005 // (be removed from the ROB) at any time.
1006 if (head_inst->isSquashed()) {
1008 DPRINTF(Commit, "Retiring squashed instruction from "
1011 rob->retireHead(commit_thread);
1013 ++commitSquashedInsts;
1014 // Notify potential listeners that this instruction is squashed
1015 ppSquash->notify(head_inst);
1017 // Record that the number of ROB entries has changed.
1018 changedROBNumEntries[tid] = true;
1020 pc[tid] = head_inst->pcState();
1022 // Increment the total number of non-speculative instructions
1024 // Hack for now: it really shouldn't happen until after the
1025 // commit is deemed to be successful, but this count is needed
1027 thread[tid]->funcExeInst++;
1029 // Try to commit the head instruction.
1030 bool commit_success = commitHead(head_inst, num_committed);
1032 if (commit_success) {
1034 statCommittedInstType[tid][head_inst->opClass()]++;
1035 ppCommit->notify(head_inst);
1037 changedROBNumEntries[tid] = true;
1039 // Set the doneSeqNum to the youngest committed instruction.
1040 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1043 canHandleInterrupts = (!head_inst->isDelayedCommit()) &&
1044 ((THE_ISA != ALPHA_ISA) ||
1045 (!(pc[0].instAddr() & 0x3)));
1048 // Updates misc. registers.
1049 head_inst->updateMiscRegs();
1051 // Check instruction execution if it successfully commits and
1052 // is not carrying a fault.
1054 cpu->checker->verify(head_inst);
1057 cpu->traceFunctions(pc[tid].instAddr());
1059 TheISA::advancePC(pc[tid], head_inst->staticInst);
1061 // Keep track of the last sequence number commited
1062 lastCommitedSeqNum[tid] = head_inst->seqNum;
1064 // If this is an instruction that doesn't play nicely with
1065 // others squash everything and restart fetch
1066 if (head_inst->isSquashAfter())
1067 squashAfter(tid, head_inst);
1070 if (pc[tid].microPC() == 0 && interrupt == NoFault &&
1071 !thread[tid]->trapPending) {
1072 // Last architectually committed instruction.
1073 // Squash the pipeline, stall fetch, and use
1074 // drainImminent to disable interrupts
1075 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1076 squashAfter(tid, head_inst);
1077 cpu->commitDrained(tid);
1078 drainImminent = true;
1082 bool onInstBoundary = !head_inst->isMicroop() ||
1083 head_inst->isLastMicroop() ||
1084 !head_inst->isDelayedCommit();
1086 if (onInstBoundary) {
1089 // Make sure we're not currently updating state while
1090 // handling PC events.
1091 assert(!thread[tid]->noSquashFromTC &&
1092 !thread[tid]->trapPending);
1094 oldpc = pc[tid].instAddr();
1095 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1097 } while (oldpc != pc[tid].instAddr());
1100 "PC skip function event, stopping commit\n");
1105 // Check if an instruction just enabled interrupts and we've
1106 // previously had an interrupt pending that was not handled
1107 // because interrupts were subsequently disabled before the
1108 // pipeline reached a place to handle the interrupt. In that
1109 // case squash now to make sure the interrupt is handled.
1111 // If we don't do this, we might end up in a live lock situation
1112 if (!interrupt && avoidQuiesceLiveLock &&
1113 onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0)))
1114 squashAfter(tid, head_inst);
1116 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1117 "[tid:%i] [sn:%i].\n",
1118 head_inst->pcState(), tid ,head_inst->seqNum);
1124 DPRINTF(CommitRate, "%i\n", num_committed);
1125 numCommittedDist.sample(num_committed);
1127 if (num_committed == commitWidth) {
1128 commitEligibleSamples++;
1132 template <class Impl>
1134 DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1138 ThreadID tid = head_inst->threadNumber;
1140 // If the instruction is not executed yet, then it will need extra
1141 // handling. Signal backwards that it should be executed.
1142 if (!head_inst->isExecuted()) {
1143 // Keep this number correct. We have not yet actually executed
1144 // and committed this instruction.
1145 thread[tid]->funcExeInst--;
1147 // Make sure we are only trying to commit un-executed instructions we
1148 // think are possible.
1149 assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional()
1150 || head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
1151 (head_inst->isLoad() && head_inst->strictlyOrdered()));
1153 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1154 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1155 head_inst->seqNum, head_inst->pcState());
1157 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1158 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1162 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1164 // Change the instruction so it won't try to commit again until
1166 head_inst->clearCanCommit();
1168 if (head_inst->isLoad() && head_inst->strictlyOrdered()) {
1169 DPRINTF(Commit, "[sn:%lli]: Strictly ordered load, PC %s.\n",
1170 head_inst->seqNum, head_inst->pcState());
1171 toIEW->commitInfo[tid].strictlyOrdered = true;
1172 toIEW->commitInfo[tid].strictlyOrderedLoad = head_inst;
1174 ++commitNonSpecStalls;
1180 if (head_inst->isThreadSync()) {
1181 // Not handled for now.
1182 panic("Thread sync instructions are not handled yet.\n");
1185 // Check if the instruction caused a fault. If so, trap.
1186 Fault inst_fault = head_inst->getFault();
1188 // Stores mark themselves as completed.
1189 if (!head_inst->isStore() && inst_fault == NoFault) {
1190 head_inst->setCompleted();
1193 if (inst_fault != NoFault) {
1194 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1195 head_inst->seqNum, head_inst->pcState());
1197 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1198 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1202 head_inst->setCompleted();
1204 // If instruction has faulted, let the checker execute it and
1205 // check if it sees the same fault and control flow.
1207 // Need to check the instruction before its fault is processed
1208 cpu->checker->verify(head_inst);
1211 assert(!thread[tid]->noSquashFromTC);
1213 // Mark that we're in state update mode so that the trap's
1214 // execution doesn't generate extra squashes.
1215 thread[tid]->noSquashFromTC = true;
1217 // Execute the trap. Although it's slightly unrealistic in
1218 // terms of timing (as it doesn't wait for the full timing of
1219 // the trap event to complete before updating state), it's
1220 // needed to update the state as soon as possible. This
1221 // prevents external agents from changing any specific state
1222 // that the trap need.
1223 cpu->trap(inst_fault, tid, head_inst->staticInst);
1225 // Exit state update mode to avoid accidental updating.
1226 thread[tid]->noSquashFromTC = false;
1228 commitStatus[tid] = TrapPending;
1230 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1232 if (head_inst->traceData) {
1233 if (DTRACE(ExecFaulting)) {
1234 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1235 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1236 head_inst->traceData->dump();
1238 delete head_inst->traceData;
1239 head_inst->traceData = NULL;
1242 // Generate trap squash event.
1243 generateTrapEvent(tid);
1247 updateComInstStats(head_inst);
1250 if (thread[tid]->profile) {
1251 thread[tid]->profilePC = head_inst->instAddr();
1252 ProfileNode *node = thread[tid]->profile->consume(
1253 thread[tid]->getTC(), head_inst->staticInst);
1256 thread[tid]->profileNode = node;
1258 if (CPA::available()) {
1259 if (head_inst->isControl()) {
1260 ThreadContext *tc = thread[tid]->getTC();
1261 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1265 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1266 head_inst->seqNum, head_inst->pcState());
1267 if (head_inst->traceData) {
1268 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1269 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1270 head_inst->traceData->dump();
1271 delete head_inst->traceData;
1272 head_inst->traceData = NULL;
1274 if (head_inst->isReturn()) {
1275 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1276 head_inst->seqNum, head_inst->pcState());
1279 // Update the commit rename map
1280 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1281 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1282 head_inst->renamedDestRegIdx(i));
1285 // Finally clear the head ROB entry.
1286 rob->retireHead(tid);
1289 if (DTRACE(O3PipeView)) {
1290 head_inst->commitTick = curTick() - head_inst->fetchTick;
1294 // If this was a store, record it for this cycle.
1295 if (head_inst->isStore())
1296 committedStores[tid] = true;
1298 // Return true to indicate that we have committed an instruction.
1302 template <class Impl>
1304 DefaultCommit<Impl>::getInsts()
1306 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1308 // Read any renamed instructions and place them into the ROB.
1309 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1311 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1314 inst = fromRename->insts[inst_num];
1315 ThreadID tid = inst->threadNumber;
1317 if (!inst->isSquashed() &&
1318 commitStatus[tid] != ROBSquashing &&
1319 commitStatus[tid] != TrapPending) {
1320 changedROBNumEntries[tid] = true;
1322 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1323 inst->pcState(), inst->seqNum, tid);
1325 rob->insertInst(inst);
1327 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1329 youngestSeqNum[tid] = inst->seqNum;
1331 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1332 "squashed, skipping.\n",
1333 inst->pcState(), inst->seqNum, tid);
1338 template <class Impl>
1340 DefaultCommit<Impl>::markCompletedInsts()
1342 // Grab completed insts out of the IEW instruction queue, and mark
1343 // instructions completed within the ROB.
1344 for (int inst_num = 0; inst_num < fromIEW->size; ++inst_num) {
1345 assert(fromIEW->insts[inst_num]);
1346 if (!fromIEW->insts[inst_num]->isSquashed()) {
1347 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1349 fromIEW->insts[inst_num]->threadNumber,
1350 fromIEW->insts[inst_num]->pcState(),
1351 fromIEW->insts[inst_num]->seqNum);
1353 // Mark the instruction as ready to commit.
1354 fromIEW->insts[inst_num]->setCanCommit();
1359 template <class Impl>
1361 DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1363 ThreadID tid = inst->threadNumber;
1365 if (!inst->isMicroop() || inst->isLastMicroop())
1366 instsCommitted[tid]++;
1367 opsCommitted[tid]++;
1369 // To match the old model, don't count nops and instruction
1370 // prefetches towards the total commit count.
1371 if (!inst->isNop() && !inst->isInstPrefetch()) {
1372 cpu->instDone(tid, inst);
1376 // Control Instructions
1378 if (inst->isControl())
1379 statComBranches[tid]++;
1382 // Memory references
1384 if (inst->isMemRef()) {
1387 if (inst->isLoad()) {
1388 statComLoads[tid]++;
1392 if (inst->isMemBarrier()) {
1393 statComMembars[tid]++;
1396 // Integer Instruction
1397 if (inst->isInteger())
1398 statComInteger[tid]++;
1400 // Floating Point Instruction
1401 if (inst->isFloating())
1402 statComFloating[tid]++;
1406 statComFunctionCalls[tid]++;
1410 ////////////////////////////////////////
1412 // SMT COMMIT POLICY MAINTAINED HERE //
1414 ////////////////////////////////////////
1415 template <class Impl>
1417 DefaultCommit<Impl>::getCommittingThread()
1419 if (numThreads > 1) {
1420 switch (commitPolicy) {
1423 //If Policy is Aggressive, commit will call
1424 //this function multiple times per
1426 return oldestReady();
1429 return roundRobin();
1432 return oldestReady();
1435 return InvalidThreadID;
1438 assert(!activeThreads->empty());
1439 ThreadID tid = activeThreads->front();
1441 if (commitStatus[tid] == Running ||
1442 commitStatus[tid] == Idle ||
1443 commitStatus[tid] == FetchTrapPending) {
1446 return InvalidThreadID;
1451 template<class Impl>
1453 DefaultCommit<Impl>::roundRobin()
1455 list<ThreadID>::iterator pri_iter = priority_list.begin();
1456 list<ThreadID>::iterator end = priority_list.end();
1458 while (pri_iter != end) {
1459 ThreadID tid = *pri_iter;
1461 if (commitStatus[tid] == Running ||
1462 commitStatus[tid] == Idle ||
1463 commitStatus[tid] == FetchTrapPending) {
1465 if (rob->isHeadReady(tid)) {
1466 priority_list.erase(pri_iter);
1467 priority_list.push_back(tid);
1476 return InvalidThreadID;
1479 template<class Impl>
1481 DefaultCommit<Impl>::oldestReady()
1483 unsigned oldest = 0;
1486 list<ThreadID>::iterator threads = activeThreads->begin();
1487 list<ThreadID>::iterator end = activeThreads->end();
1489 while (threads != end) {
1490 ThreadID tid = *threads++;
1492 if (!rob->isEmpty(tid) &&
1493 (commitStatus[tid] == Running ||
1494 commitStatus[tid] == Idle ||
1495 commitStatus[tid] == FetchTrapPending)) {
1497 if (rob->isHeadReady(tid)) {
1499 DynInstPtr head_inst = rob->readHeadInst(tid);
1504 } else if (head_inst->seqNum < oldest) {
1514 return InvalidThreadID;
1518 #endif//__CPU_O3_COMMIT_IMPL_HH__