src/cpu/o3/cpu.cc

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Korey Sewell
  30  */
  31
  32 #include "config/full_system.hh"
  33 #include "config/use_checker.hh"
  34
  35 #if FULL_SYSTEM
  36 #include "sim/system.hh"
  37 #else
  38 #include "sim/process.hh"
  39 #endif
  40
  41 #include "cpu/activity.hh"
  42 #include "cpu/simple_thread.hh"
  43 #include "cpu/thread_context.hh"
  44 #include "cpu/o3/isa_specific.hh"
  45 #include "cpu/o3/cpu.hh"
  46
  47 #include "sim/root.hh"
  48 #include "sim/stat_control.hh"
  49
  50 #if USE_CHECKER
  51 #include "cpu/checker/cpu.hh"
  52 #endif
  53
  54 using namespace std;
  55 using namespace TheISA;
  56
  57 BaseO3CPU::BaseO3CPU(Params *params)
  58     : BaseCPU(params), cpu_id(0)
  59 {
  60 }
  61
  62 void
  63 BaseO3CPU::regStats()
  64 {
  65     BaseCPU::regStats();
  66 }
  67
  68 template <class Impl>
  69 FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
  70     : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
  71 {
  72 }
  73
  74 template <class Impl>
  75 void
  76 FullO3CPU<Impl>::TickEvent::process()
  77 {
  78     cpu->tick();
  79 }
  80
  81 template <class Impl>
  82 const char *
  83 FullO3CPU<Impl>::TickEvent::description()
  84 {
  85     return "FullO3CPU tick event";
  86 }
  87
  88 template <class Impl>
  89 FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
  90     : Event(&mainEventQueue, CPU_Tick_Pri)
  91 {
  92 }
  93
  94 template <class Impl>
  95 void
  96 FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
  97                                            FullO3CPU<Impl> *thread_cpu)
  98 {
  99     tid = thread_num;
 100     cpu = thread_cpu;
 101 }
 102
 103 template <class Impl>
 104 void
 105 FullO3CPU<Impl>::ActivateThreadEvent::process()
 106 {
 107     cpu->activateThread(tid);
 108 }
 109
 110 template <class Impl>
 111 const char *
 112 FullO3CPU<Impl>::ActivateThreadEvent::description()
 113 {
 114     return "FullO3CPU \"Activate Thread\" event";
 115 }
 116
 117 template <class Impl>
 118 FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
 119     : Event(&mainEventQueue, CPU_Tick_Pri)
 120 {
 121 }
 122
 123 template <class Impl>
 124 void
 125 FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
 126                                            FullO3CPU<Impl> *thread_cpu)
 127 {
 128     tid = thread_num;
 129     cpu = thread_cpu;
 130 }
 131
 132 template <class Impl>
 133 void
 134 FullO3CPU<Impl>::DeallocateContextEvent::process()
 135 {
 136     cpu->deactivateThread(tid);
 137     cpu->removeThread(tid);
 138 }
 139
 140 template <class Impl>
 141 const char *
 142 FullO3CPU<Impl>::DeallocateContextEvent::description()
 143 {
 144     return "FullO3CPU \"Deallocate Context\" event";
 145 }
 146
 147 template <class Impl>
 148 FullO3CPU<Impl>::FullO3CPU(Params *params)
 149     : BaseO3CPU(params),
 150       tickEvent(this),
 151       removeInstsThisCycle(false),
 152       fetch(params),
 153       decode(params),
 154       rename(params),
 155       iew(params),
 156       commit(params),
 157
 158       regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
 159
 160       freeList(params->numberOfThreads,
 161                TheISA::NumIntRegs, params->numPhysIntRegs,
 162                TheISA::NumFloatRegs, params->numPhysFloatRegs),
 163
 164       rob(params->numROBEntries, params->squashWidth,
 165           params->smtROBPolicy, params->smtROBThreshold,
 166           params->numberOfThreads),
 167
 168       scoreboard(params->numberOfThreads,
 169                  TheISA::NumIntRegs, params->numPhysIntRegs,
 170                  TheISA::NumFloatRegs, params->numPhysFloatRegs,
 171                  TheISA::NumMiscRegs * number_of_threads,
 172                  TheISA::ZeroReg),
 173
 174       timeBuffer(params->backComSize, params->forwardComSize),
 175       fetchQueue(params->backComSize, params->forwardComSize),
 176       decodeQueue(params->backComSize, params->forwardComSize),
 177       renameQueue(params->backComSize, params->forwardComSize),
 178       iewQueue(params->backComSize, params->forwardComSize),
 179       activityRec(NumStages,
 180                   params->backComSize + params->forwardComSize,
 181                   params->activity),
 182
 183       globalSeqNum(1),
 184
 185 #if FULL_SYSTEM
 186       system(params->system),
 187       physmem(system->physmem),
 188 #endif // FULL_SYSTEM
 189       mem(params->mem),
 190       drainCount(0),
 191       deferRegistration(params->deferRegistration),
 192       numThreads(number_of_threads)
 193 {
 194     _status = Idle;
 195
 196     checker = NULL;
 197
 198     if (params->checker) {
 199 #if USE_CHECKER
 200         BaseCPU *temp_checker = params->checker;
 201         checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
 202         checker->setMemory(mem);
 203 #if FULL_SYSTEM
 204         checker->setSystem(params->system);
 205 #endif
 206 #else
 207         panic("Checker enabled but not compiled in!");
 208 #endif // USE_CHECKER
 209     }
 210
 211 #if !FULL_SYSTEM
 212     thread.resize(number_of_threads);
 213     tids.resize(number_of_threads);
 214 #endif
 215
 216     // The stages also need their CPU pointer setup.  However this
 217     // must be done at the upper level CPU because they have pointers
 218     // to the upper level CPU, and not this FullO3CPU.
 219
 220     // Set up Pointers to the activeThreads list for each stage
 221     fetch.setActiveThreads(&activeThreads);
 222     decode.setActiveThreads(&activeThreads);
 223     rename.setActiveThreads(&activeThreads);
 224     iew.setActiveThreads(&activeThreads);
 225     commit.setActiveThreads(&activeThreads);
 226
 227     // Give each of the stages the time buffer they will use.
 228     fetch.setTimeBuffer(&timeBuffer);
 229     decode.setTimeBuffer(&timeBuffer);
 230     rename.setTimeBuffer(&timeBuffer);
 231     iew.setTimeBuffer(&timeBuffer);
 232     commit.setTimeBuffer(&timeBuffer);
 233
 234     // Also setup each of the stages' queues.
 235     fetch.setFetchQueue(&fetchQueue);
 236     decode.setFetchQueue(&fetchQueue);
 237     commit.setFetchQueue(&fetchQueue);
 238     decode.setDecodeQueue(&decodeQueue);
 239     rename.setDecodeQueue(&decodeQueue);
 240     rename.setRenameQueue(&renameQueue);
 241     iew.setRenameQueue(&renameQueue);
 242     iew.setIEWQueue(&iewQueue);
 243     commit.setIEWQueue(&iewQueue);
 244     commit.setRenameQueue(&renameQueue);
 245
 246     commit.setIEWStage(&iew);
 247     rename.setIEWStage(&iew);
 248     rename.setCommitStage(&commit);
 249
 250 #if !FULL_SYSTEM
 251     int active_threads = params->workload.size();
 252
 253     if (active_threads > Impl::MaxThreads) {
 254         panic("Workload Size too large. Increase the 'MaxThreads'"
 255               "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
 256               "edit your workload size.");
 257     }
 258 #else
 259     int active_threads = 1;
 260 #endif
 261
 262     //Make Sure That this a Valid Architeture
 263     assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
 264     assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
 265
 266     rename.setScoreboard(&scoreboard);
 267     iew.setScoreboard(&scoreboard);
 268
 269     // Setup the rename map for whichever stages need it.
 270     PhysRegIndex lreg_idx = 0;
 271     PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
 272
 273     for (int tid=0; tid < numThreads; tid++) {
 274         bool bindRegs = (tid <= active_threads - 1);
 275
 276         commitRenameMap[tid].init(TheISA::NumIntRegs,
 277                                   params->numPhysIntRegs,
 278                                   lreg_idx,            //Index for Logical. Regs
 279
 280                                   TheISA::NumFloatRegs,
 281                                   params->numPhysFloatRegs,
 282                                   freg_idx,            //Index for Float Regs
 283
 284                                   TheISA::NumMiscRegs,
 285
 286                                   TheISA::ZeroReg,
 287                                   TheISA::ZeroReg,
 288
 289                                   tid,
 290                                   false);
 291
 292         renameMap[tid].init(TheISA::NumIntRegs,
 293                             params->numPhysIntRegs,
 294                             lreg_idx,                  //Index for Logical. Regs
 295
 296                             TheISA::NumFloatRegs,
 297                             params->numPhysFloatRegs,
 298                             freg_idx,                  //Index for Float Regs
 299
 300                             TheISA::NumMiscRegs,
 301
 302                             TheISA::ZeroReg,
 303                             TheISA::ZeroReg,
 304
 305                             tid,
 306                             bindRegs);
 307     }
 308
 309     rename.setRenameMap(renameMap);
 310     commit.setRenameMap(commitRenameMap);
 311
 312     // Give renameMap & rename stage access to the freeList;
 313     for (int i=0; i < numThreads; i++) {
 314         renameMap[i].setFreeList(&freeList);
 315     }
 316     rename.setFreeList(&freeList);
 317
 318     // Setup the ROB for whichever stages need it.
 319     commit.setROB(&rob);
 320
 321     lastRunningCycle = curTick;
 322
 323     lastActivatedCycle = -1;
 324
 325     contextSwitch = false;
 326 }
 327
 328 template <class Impl>
 329 FullO3CPU<Impl>::~FullO3CPU()
 330 {
 331 }
 332
 333 template <class Impl>
 334 void
 335 FullO3CPU<Impl>::fullCPURegStats()
 336 {
 337     BaseO3CPU::regStats();
 338
 339     // Register any of the O3CPU's stats here.
 340     timesIdled
 341         .name(name() + ".timesIdled")
 342         .desc("Number of times that the entire CPU went into an idle state and"
 343               " unscheduled itself")
 344         .prereq(timesIdled);
 345
 346     idleCycles
 347         .name(name() + ".idleCycles")
 348         .desc("Total number of cycles that the CPU has spent unscheduled due "
 349               "to idling")
 350         .prereq(idleCycles);
 351
 352     // Number of Instructions simulated
 353     // --------------------------------
 354     // Should probably be in Base CPU but need templated
 355     // MaxThreads so put in here instead
 356     committedInsts
 357         .init(numThreads)
 358         .name(name() + ".committedInsts")
 359         .desc("Number of Instructions Simulated");
 360
 361     totalCommittedInsts
 362         .name(name() + ".committedInsts_total")
 363         .desc("Number of Instructions Simulated");
 364
 365     cpi
 366         .name(name() + ".cpi")
 367         .desc("CPI: Cycles Per Instruction")
 368         .precision(6);
 369     cpi = simTicks / committedInsts;
 370
 371     totalCpi
 372         .name(name() + ".cpi_total")
 373         .desc("CPI: Total CPI of All Threads")
 374         .precision(6);
 375     totalCpi = simTicks / totalCommittedInsts;
 376
 377     ipc
 378         .name(name() + ".ipc")
 379         .desc("IPC: Instructions Per Cycle")
 380         .precision(6);
 381     ipc =  committedInsts / simTicks;
 382
 383     totalIpc
 384         .name(name() + ".ipc_total")
 385         .desc("IPC: Total IPC of All Threads")
 386         .precision(6);
 387     totalIpc =  totalCommittedInsts / simTicks;
 388
 389 }
 390
 391 template <class Impl>
 392 Port *
 393 FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
 394 {
 395     if (if_name == "dcache_port")
 396         return iew.getDcachePort();
 397     else if (if_name == "icache_port")
 398         return fetch.getIcachePort();
 399     else
 400         panic("No Such Port\n");
 401 }
 402
 403 template <class Impl>
 404 void
 405 FullO3CPU<Impl>::tick()
 406 {
 407     DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
 408
 409     ++numCycles;
 410
 411 //    activity = false;
 412
 413     //Tick each of the stages
 414     fetch.tick();
 415
 416     decode.tick();
 417
 418     rename.tick();
 419
 420     iew.tick();
 421
 422     commit.tick();
 423
 424 #if !FULL_SYSTEM
 425     doContextSwitch();
 426 #endif
 427
 428     // Now advance the time buffers
 429     timeBuffer.advance();
 430
 431     fetchQueue.advance();
 432     decodeQueue.advance();
 433     renameQueue.advance();
 434     iewQueue.advance();
 435
 436     activityRec.advance();
 437
 438     if (removeInstsThisCycle) {
 439         cleanUpRemovedInsts();
 440     }
 441
 442     if (!tickEvent.scheduled()) {
 443         if (_status == SwitchedOut ||
 444             getState() == SimObject::DrainedTiming) {
 445             // increment stat
 446             lastRunningCycle = curTick;
 447         } else if (!activityRec.active()) {
 448             lastRunningCycle = curTick;
 449             timesIdled++;
 450         } else {
 451             tickEvent.schedule(curTick + cycles(1));
 452         }
 453     }
 454
 455 #if !FULL_SYSTEM
 456     updateThreadPriority();
 457 #endif
 458
 459 }
 460
 461 template <class Impl>
 462 void
 463 FullO3CPU<Impl>::init()
 464 {
 465     if (!deferRegistration) {
 466         registerThreadContexts();
 467     }
 468
 469     // Set inSyscall so that the CPU doesn't squash when initially
 470     // setting up registers.
 471     for (int i = 0; i < number_of_threads; ++i)
 472         thread[i]->inSyscall = true;
 473
 474     for (int tid=0; tid < number_of_threads; tid++) {
 475 #if FULL_SYSTEM
 476         ThreadContext *src_tc = threadContexts[tid];
 477 #else
 478         ThreadContext *src_tc = thread[tid]->getTC();
 479 #endif
 480         // Threads start in the Suspended State
 481         if (src_tc->status() != ThreadContext::Suspended) {
 482             continue;
 483         }
 484
 485 #if FULL_SYSTEM
 486         TheISA::initCPU(src_tc, src_tc->readCpuId());
 487 #endif
 488     }
 489
 490     // Clear inSyscall.
 491     for (int i = 0; i < number_of_threads; ++i)
 492         thread[i]->inSyscall = false;
 493
 494     // Initialize stages.
 495     fetch.initStage();
 496     iew.initStage();
 497     rename.initStage();
 498     commit.initStage();
 499
 500     commit.setThreads(thread);
 501 }
 502
 503 template <class Impl>
 504 void
 505 FullO3CPU<Impl>::activateThread(unsigned tid)
 506 {
 507     list<unsigned>::iterator isActive = find(
 508         activeThreads.begin(), activeThreads.end(), tid);
 509
 510     if (isActive == activeThreads.end()) {
 511         DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
 512                 tid);
 513
 514         activeThreads.push_back(tid);
 515     }
 516 }
 517
 518 template <class Impl>
 519 void
 520 FullO3CPU<Impl>::deactivateThread(unsigned tid)
 521 {
 522     //Remove From Active List, if Active
 523     list<unsigned>::iterator thread_it =
 524         find(activeThreads.begin(), activeThreads.end(), tid);
 525
 526     if (thread_it != activeThreads.end()) {
 527         DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
 528                 tid);
 529         activeThreads.erase(thread_it);
 530     }
 531 }
 532
 533 template <class Impl>
 534 void
 535 FullO3CPU<Impl>::activateContext(int tid, int delay)
 536 {
 537     // Needs to set each stage to running as well.
 538     if (delay){
 539         DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
 540                 "on cycle %d\n", tid, curTick + cycles(delay));
 541         scheduleActivateThreadEvent(tid, delay);
 542     } else {
 543         activateThread(tid);
 544     }
 545
 546     if(lastActivatedCycle < curTick) {
 547         scheduleTickEvent(delay);
 548
 549         // Be sure to signal that there's some activity so the CPU doesn't
 550         // deschedule itself.
 551         activityRec.activity();
 552         fetch.wakeFromQuiesce();
 553
 554         lastActivatedCycle = curTick;
 555
 556         _status = Running;
 557     }
 558 }
 559
 560 template <class Impl>
 561 void
 562 FullO3CPU<Impl>::deallocateContext(int tid, int delay)
 563 {
 564     // Schedule removal of thread data from CPU
 565     if (delay){
 566         DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
 567                 "on cycle %d\n", tid, curTick + cycles(delay));
 568         scheduleDeallocateContextEvent(tid, delay);
 569     } else {
 570         deactivateThread(tid);
 571         removeThread(tid);
 572     }
 573 }
 574
 575 template <class Impl>
 576 void
 577 FullO3CPU<Impl>::suspendContext(int tid)
 578 {
 579     DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
 580     unscheduleTickEvent();
 581     _status = Idle;
 582 /*
 583     //Remove From Active List, if Active
 584     list<unsigned>::iterator isActive = find(
 585         activeThreads.begin(), activeThreads.end(), tid);
 586
 587     if (isActive != activeThreads.end()) {
 588         DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
 589                 tid);
 590         activeThreads.erase(isActive);
 591     }
 592 */
 593 }
 594
 595 template <class Impl>
 596 void
 597 FullO3CPU<Impl>::haltContext(int tid)
 598 {
 599     DPRINTF(O3CPU,"[tid:%i]: Halting Thread Context", tid);
 600 /*
 601     //Remove From Active List, if Active
 602     list<unsigned>::iterator isActive = find(
 603         activeThreads.begin(), activeThreads.end(), tid);
 604
 605     if (isActive != activeThreads.end()) {
 606         DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
 607                 tid);
 608         activeThreads.erase(isActive);
 609
 610         removeThread(tid);
 611     }
 612 */
 613 }
 614
 615 template <class Impl>
 616 void
 617 FullO3CPU<Impl>::insertThread(unsigned tid)
 618 {
 619     DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
 620     // Will change now that the PC and thread state is internal to the CPU
 621     // and not in the ThreadContext.
 622 #if FULL_SYSTEM
 623     ThreadContext *src_tc = system->threadContexts[tid];
 624 #else
 625     ThreadContext *src_tc = tcBase(tid);
 626 #endif
 627
 628     //Bind Int Regs to Rename Map
 629     for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
 630         PhysRegIndex phys_reg = freeList.getIntReg();
 631
 632         renameMap[tid].setEntry(ireg,phys_reg);
 633         scoreboard.setReg(phys_reg);
 634     }
 635
 636     //Bind Float Regs to Rename Map
 637     for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
 638         PhysRegIndex phys_reg = freeList.getFloatReg();
 639
 640         renameMap[tid].setEntry(freg,phys_reg);
 641         scoreboard.setReg(phys_reg);
 642     }
 643
 644     //Copy Thread Data Into RegFile
 645     //this->copyFromTC(tid);
 646
 647     //Set PC/NPC/NNPC
 648     setPC(src_tc->readPC(), tid);
 649     setNextPC(src_tc->readNextPC(), tid);
 650 #if THE_ISA != ALPHA_ISA
 651     setNextNPC(src_tc->readNextNPC(), tid);
 652 #endif
 653
 654     src_tc->setStatus(ThreadContext::Active);
 655
 656     activateContext(tid,1);
 657
 658     //Reset ROB/IQ/LSQ Entries
 659     commit.rob->resetEntries();
 660     iew.resetEntries();
 661 }
 662
 663 template <class Impl>
 664 void
 665 FullO3CPU<Impl>::removeThread(unsigned tid)
 666 {
 667     DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
 668
 669     // Copy Thread Data From RegFile
 670     // If thread is suspended, it might be re-allocated
 671     //this->copyToTC(tid);
 672
 673     // Unbind Int Regs from Rename Map
 674     for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
 675         PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
 676
 677         scoreboard.unsetReg(phys_reg);
 678         freeList.addReg(phys_reg);
 679     }
 680
 681     // Unbind Float Regs from Rename Map
 682     for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
 683         PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
 684
 685         scoreboard.unsetReg(phys_reg);
 686         freeList.addReg(phys_reg);
 687     }
 688
 689     // Squash Throughout Pipeline
 690     fetch.squash(0,tid);
 691     decode.squash(tid);
 692     rename.squash(tid);
 693     iew.squash(tid);
 694     commit.rob->squash(commit.rob->readHeadInst(tid)->seqNum, tid);
 695
 696     assert(iew.ldstQueue.getCount(tid) == 0);
 697
 698     // Reset ROB/IQ/LSQ Entries
 699     if (activeThreads.size() >= 1) {
 700         commit.rob->resetEntries();
 701         iew.resetEntries();
 702     }
 703 }
 704
 705
 706 template <class Impl>
 707 void
 708 FullO3CPU<Impl>::activateWhenReady(int tid)
 709 {
 710     DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
 711             "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
 712             tid);
 713
 714     bool ready = true;
 715
 716     if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
 717         DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
 718                 "Phys. Int. Regs.\n",
 719                 tid);
 720         ready = false;
 721     } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
 722         DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
 723                 "Phys. Float. Regs.\n",
 724                 tid);
 725         ready = false;
 726     } else if (commit.rob->numFreeEntries() >=
 727                commit.rob->entryAmount(activeThreads.size() + 1)) {
 728         DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
 729                 "ROB entries.\n",
 730                 tid);
 731         ready = false;
 732     } else if (iew.instQueue.numFreeEntries() >=
 733                iew.instQueue.entryAmount(activeThreads.size() + 1)) {
 734         DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
 735                 "IQ entries.\n",
 736                 tid);
 737         ready = false;
 738     } else if (iew.ldstQueue.numFreeEntries() >=
 739                iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
 740         DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
 741                 "LSQ entries.\n",
 742                 tid);
 743         ready = false;
 744     }
 745
 746     if (ready) {
 747         insertThread(tid);
 748
 749         contextSwitch = false;
 750
 751         cpuWaitList.remove(tid);
 752     } else {
 753         suspendContext(tid);
 754
 755         //blocks fetch
 756         contextSwitch = true;
 757
 758         //@todo: dont always add to waitlist
 759         //do waitlist
 760         cpuWaitList.push_back(tid);
 761     }
 762 }
 763
 764 template <class Impl>
 765 void
 766 FullO3CPU<Impl>::serialize(std::ostream &os)
 767 {
 768     SERIALIZE_ENUM(_status);
 769     BaseCPU::serialize(os);
 770     nameOut(os, csprintf("%s.tickEvent", name()));
 771     tickEvent.serialize(os);
 772
 773     // Use SimpleThread's ability to checkpoint to make it easier to
 774     // write out the registers.  Also make this static so it doesn't
 775     // get instantiated multiple times (causes a panic in statistics).
 776     static SimpleThread temp;
 777
 778     for (int i = 0; i < thread.size(); i++) {
 779         nameOut(os, csprintf("%s.xc.%i", name(), i));
 780         temp.copyTC(thread[i]->getTC());
 781         temp.serialize(os);
 782     }
 783 }
 784
 785 template <class Impl>
 786 void
 787 FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
 788 {
 789     UNSERIALIZE_ENUM(_status);
 790     BaseCPU::unserialize(cp, section);
 791     tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
 792
 793     // Use SimpleThread's ability to checkpoint to make it easier to
 794     // read in the registers.  Also make this static so it doesn't
 795     // get instantiated multiple times (causes a panic in statistics).
 796     static SimpleThread temp;
 797
 798     for (int i = 0; i < thread.size(); i++) {
 799         temp.copyTC(thread[i]->getTC());
 800         temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
 801         thread[i]->getTC()->copyArchRegs(temp.getTC());
 802     }
 803 }
 804
 805 template <class Impl>
 806 bool
 807 FullO3CPU<Impl>::drain(Event *drain_event)
 808 {
 809     drainCount = 0;
 810     fetch.drain();
 811     decode.drain();
 812     rename.drain();
 813     iew.drain();
 814     commit.drain();
 815
 816     // Wake the CPU and record activity so everything can drain out if
 817     // the CPU was not able to immediately drain.
 818     if (getState() != SimObject::DrainedTiming) {
 819         // A bit of a hack...set the drainEvent after all the drain()
 820         // calls have been made, that way if all of the stages drain
 821         // immediately, the signalDrained() function knows not to call
 822         // process on the drain event.
 823         drainEvent = drain_event;
 824
 825         wakeCPU();
 826         activityRec.activity();
 827
 828         return false;
 829     } else {
 830         return true;
 831     }
 832 }
 833
 834 template <class Impl>
 835 void
 836 FullO3CPU<Impl>::resume()
 837 {
 838     fetch.resume();
 839     decode.resume();
 840     rename.resume();
 841     iew.resume();
 842     commit.resume();
 843
 844     if (_status == SwitchedOut || _status == Idle)
 845         return;
 846
 847     if (!tickEvent.scheduled())
 848         tickEvent.schedule(curTick);
 849     _status = Running;
 850     changeState(SimObject::Timing);
 851 }
 852
 853 template <class Impl>
 854 void
 855 FullO3CPU<Impl>::signalDrained()
 856 {
 857     if (++drainCount == NumStages) {
 858         if (tickEvent.scheduled())
 859             tickEvent.squash();
 860
 861         changeState(SimObject::DrainedTiming);
 862
 863         if (drainEvent) {
 864             drainEvent->process();
 865             drainEvent = NULL;
 866         }
 867     }
 868     assert(drainCount <= 5);
 869 }
 870
 871 template <class Impl>
 872 void
 873 FullO3CPU<Impl>::switchOut()
 874 {
 875     fetch.switchOut();
 876     rename.switchOut();
 877     commit.switchOut();
 878     instList.clear();
 879     while (!removeList.empty()) {
 880         removeList.pop();
 881     }
 882
 883     _status = SwitchedOut;
 884 #if USE_CHECKER
 885     if (checker)
 886         checker->switchOut();
 887 #endif
 888 }
 889
 890 template <class Impl>
 891 void
 892 FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
 893 {
 894     // Flush out any old data from the time buffers.
 895     for (int i = 0; i < timeBuffer.getSize(); ++i) {
 896         timeBuffer.advance();
 897         fetchQueue.advance();
 898         decodeQueue.advance();
 899         renameQueue.advance();
 900         iewQueue.advance();
 901     }
 902
 903     activityRec.reset();
 904
 905     BaseCPU::takeOverFrom(oldCPU);
 906
 907     fetch.takeOverFrom();
 908     decode.takeOverFrom();
 909     rename.takeOverFrom();
 910     iew.takeOverFrom();
 911     commit.takeOverFrom();
 912
 913     assert(!tickEvent.scheduled());
 914
 915     // @todo: Figure out how to properly select the tid to put onto
 916     // the active threads list.
 917     int tid = 0;
 918
 919     list<unsigned>::iterator isActive = find(
 920         activeThreads.begin(), activeThreads.end(), tid);
 921
 922     if (isActive == activeThreads.end()) {
 923         //May Need to Re-code this if the delay variable is the delay
 924         //needed for thread to activate
 925         DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
 926                 tid);
 927
 928         activeThreads.push_back(tid);
 929     }
 930
 931     // Set all statuses to active, schedule the CPU's tick event.
 932     // @todo: Fix up statuses so this is handled properly
 933     for (int i = 0; i < threadContexts.size(); ++i) {
 934         ThreadContext *tc = threadContexts[i];
 935         if (tc->status() == ThreadContext::Active && _status != Running) {
 936             _status = Running;
 937             tickEvent.schedule(curTick);
 938         }
 939     }
 940     if (!tickEvent.scheduled())
 941         tickEvent.schedule(curTick);
 942 }
 943
 944 template <class Impl>
 945 uint64_t
 946 FullO3CPU<Impl>::readIntReg(int reg_idx)
 947 {
 948     return regFile.readIntReg(reg_idx);
 949 }
 950
 951 template <class Impl>
 952 FloatReg
 953 FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
 954 {
 955     return regFile.readFloatReg(reg_idx, width);
 956 }
 957
 958 template <class Impl>
 959 FloatReg
 960 FullO3CPU<Impl>::readFloatReg(int reg_idx)
 961 {
 962     return regFile.readFloatReg(reg_idx);
 963 }
 964
 965 template <class Impl>
 966 FloatRegBits
 967 FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
 968 {
 969     return regFile.readFloatRegBits(reg_idx, width);
 970 }
 971
 972 template <class Impl>
 973 FloatRegBits
 974 FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
 975 {
 976     return regFile.readFloatRegBits(reg_idx);
 977 }
 978
 979 template <class Impl>
 980 void
 981 FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
 982 {
 983     regFile.setIntReg(reg_idx, val);
 984 }
 985
 986 template <class Impl>
 987 void
 988 FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
 989 {
 990     regFile.setFloatReg(reg_idx, val, width);
 991 }
 992
 993 template <class Impl>
 994 void
 995 FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
 996 {
 997     regFile.setFloatReg(reg_idx, val);
 998 }
 999
1000 template <class Impl>
1001 void
1002 FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
1003 {
1004     regFile.setFloatRegBits(reg_idx, val, width);
1005 }
1006
1007 template <class Impl>
1008 void
1009 FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1010 {
1011     regFile.setFloatRegBits(reg_idx, val);
1012 }
1013
1014 template <class Impl>
1015 uint64_t
1016 FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid)
1017 {
1018     PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1019
1020     return regFile.readIntReg(phys_reg);
1021 }
1022
1023 template <class Impl>
1024 float
1025 FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid)
1026 {
1027     int idx = reg_idx + TheISA::FP_Base_DepTag;
1028     PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1029
1030     return regFile.readFloatReg(phys_reg);
1031 }
1032
1033 template <class Impl>
1034 double
1035 FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid)
1036 {
1037     int idx = reg_idx + TheISA::FP_Base_DepTag;
1038     PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1039
1040     return regFile.readFloatReg(phys_reg, 64);
1041 }
1042
1043 template <class Impl>
1044 uint64_t
1045 FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid)
1046 {
1047     int idx = reg_idx + TheISA::FP_Base_DepTag;
1048     PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1049
1050     return regFile.readFloatRegBits(phys_reg);
1051 }
1052
1053 template <class Impl>
1054 void
1055 FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid)
1056 {
1057     PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1058
1059     regFile.setIntReg(phys_reg, val);
1060 }
1061
1062 template <class Impl>
1063 void
1064 FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
1065 {
1066     PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1067
1068     regFile.setFloatReg(phys_reg, val);
1069 }
1070
1071 template <class Impl>
1072 void
1073 FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
1074 {
1075     PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1076
1077     regFile.setFloatReg(phys_reg, val, 64);
1078 }
1079
1080 template <class Impl>
1081 void
1082 FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
1083 {
1084     PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1085
1086     regFile.setFloatRegBits(phys_reg, val);
1087 }
1088
1089 template <class Impl>
1090 uint64_t
1091 FullO3CPU<Impl>::readPC(unsigned tid)
1092 {
1093     return commit.readPC(tid);
1094 }
1095
1096 template <class Impl>
1097 void
1098 FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid)
1099 {
1100     commit.setPC(new_PC, tid);
1101 }
1102
1103 template <class Impl>
1104 uint64_t
1105 FullO3CPU<Impl>::readNextPC(unsigned tid)
1106 {
1107     return commit.readNextPC(tid);
1108 }
1109
1110 template <class Impl>
1111 void
1112 FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
1113 {
1114     commit.setNextPC(val, tid);
1115 }
1116
1117 #if THE_ISA != ALPHA_ISA
1118 template <class Impl>
1119 uint64_t
1120 FullO3CPU<Impl>::readNextNPC(unsigned tid)
1121 {
1122     return commit.readNextNPC(tid);
1123 }
1124
1125 template <class Impl>
1126 void
1127 FullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid)
1128 {
1129     commit.setNextNPC(val, tid);
1130 }
1131 #endif
1132
1133 template <class Impl>
1134 typename FullO3CPU<Impl>::ListIt
1135 FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1136 {
1137     instList.push_back(inst);
1138
1139     return --(instList.end());
1140 }
1141
1142 template <class Impl>
1143 void
1144 FullO3CPU<Impl>::instDone(unsigned tid)
1145 {
1146     // Keep an instruction count.
1147     thread[tid]->numInst++;
1148     thread[tid]->numInsts++;
1149     committedInsts[tid]++;
1150     totalCommittedInsts++;
1151
1152     // Check for instruction-count-based events.
1153     comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1154 }
1155
1156 template <class Impl>
1157 void
1158 FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
1159 {
1160     removeInstsThisCycle = true;
1161
1162     removeList.push(inst->getInstListIt());
1163 }
1164
1165 template <class Impl>
1166 void
1167 FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1168 {
1169     DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
1170             "[sn:%lli]\n",
1171             inst->threadNumber, inst->readPC(), inst->seqNum);
1172
1173     removeInstsThisCycle = true;
1174
1175     // Remove the front instruction.
1176     removeList.push(inst->getInstListIt());
1177 }
1178
1179 template <class Impl>
1180 void
1181 FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
1182 {
1183     DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1184             " list.\n", tid);
1185
1186     ListIt end_it;
1187
1188     bool rob_empty = false;
1189
1190     if (instList.empty()) {
1191         return;
1192     } else if (rob.isEmpty(/*tid*/)) {
1193         DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1194         end_it = instList.begin();
1195         rob_empty = true;
1196     } else {
1197         end_it = (rob.readTailInst(tid))->getInstListIt();
1198         DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1199     }
1200
1201     removeInstsThisCycle = true;
1202
1203     ListIt inst_it = instList.end();
1204
1205     inst_it--;
1206
1207     // Walk through the instruction list, removing any instructions
1208     // that were inserted after the given instruction iterator, end_it.
1209     while (inst_it != end_it) {
1210         assert(!instList.empty());
1211
1212         squashInstIt(inst_it, tid);
1213
1214         inst_it--;
1215     }
1216
1217     // If the ROB was empty, then we actually need to remove the first
1218     // instruction as well.
1219     if (rob_empty) {
1220         squashInstIt(inst_it, tid);
1221     }
1222 }
1223
1224 template <class Impl>
1225 void
1226 FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
1227                                   unsigned tid)
1228 {
1229     assert(!instList.empty());
1230
1231     removeInstsThisCycle = true;
1232
1233     ListIt inst_iter = instList.end();
1234
1235     inst_iter--;
1236
1237     DPRINTF(O3CPU, "Deleting instructions from instruction "
1238             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1239             tid, seq_num, (*inst_iter)->seqNum);
1240
1241     while ((*inst_iter)->seqNum > seq_num) {
1242
1243         bool break_loop = (inst_iter == instList.begin());
1244
1245         squashInstIt(inst_iter, tid);
1246
1247         inst_iter--;
1248
1249         if (break_loop)
1250             break;
1251     }
1252 }
1253
1254 template <class Impl>
1255 inline void
1256 FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1257 {
1258     if ((*instIt)->threadNumber == tid) {
1259         DPRINTF(O3CPU, "Squashing instruction, "
1260                 "[tid:%i] [sn:%lli] PC %#x\n",
1261                 (*instIt)->threadNumber,
1262                 (*instIt)->seqNum,
1263                 (*instIt)->readPC());
1264
1265         // Mark it as squashed.
1266         (*instIt)->setSquashed();
1267
1268         // @todo: Formulate a consistent method for deleting
1269         // instructions from the instruction list
1270         // Remove the instruction from the list.
1271         removeList.push(instIt);
1272     }
1273 }
1274
1275 template <class Impl>
1276 void
1277 FullO3CPU<Impl>::cleanUpRemovedInsts()
1278 {
1279     while (!removeList.empty()) {
1280         DPRINTF(O3CPU, "Removing instruction, "
1281                 "[tid:%i] [sn:%lli] PC %#x\n",
1282                 (*removeList.front())->threadNumber,
1283                 (*removeList.front())->seqNum,
1284                 (*removeList.front())->readPC());
1285
1286         instList.erase(removeList.front());
1287
1288         removeList.pop();
1289     }
1290
1291     removeInstsThisCycle = false;
1292 }
1293 /*
1294 template <class Impl>
1295 void
1296 FullO3CPU<Impl>::removeAllInsts()
1297 {
1298     instList.clear();
1299 }
1300 */
1301 template <class Impl>
1302 void
1303 FullO3CPU<Impl>::dumpInsts()
1304 {
1305     int num = 0;
1306
1307     ListIt inst_list_it = instList.begin();
1308
1309     cprintf("Dumping Instruction List\n");
1310
1311     while (inst_list_it != instList.end()) {
1312         cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1313                 "Squashed:%i\n\n",
1314                 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
1315                 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1316                 (*inst_list_it)->isSquashed());
1317         inst_list_it++;
1318         ++num;
1319     }
1320 }
1321 /*
1322 template <class Impl>
1323 void
1324 FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1325 {
1326     iew.wakeDependents(inst);
1327 }
1328 */
1329 template <class Impl>
1330 void
1331 FullO3CPU<Impl>::wakeCPU()
1332 {
1333     if (activityRec.active() || tickEvent.scheduled()) {
1334         DPRINTF(Activity, "CPU already running.\n");
1335         return;
1336     }
1337
1338     DPRINTF(Activity, "Waking up CPU\n");
1339
1340     idleCycles += (curTick - 1) - lastRunningCycle;
1341
1342     tickEvent.schedule(curTick);
1343 }
1344
1345 template <class Impl>
1346 int
1347 FullO3CPU<Impl>::getFreeTid()
1348 {
1349     for (int i=0; i < numThreads; i++) {
1350         if (!tids[i]) {
1351             tids[i] = true;
1352             return i;
1353         }
1354     }
1355
1356     return -1;
1357 }
1358
1359 template <class Impl>
1360 void
1361 FullO3CPU<Impl>::doContextSwitch()
1362 {
1363     if (contextSwitch) {
1364
1365         //ADD CODE TO DEACTIVE THREAD HERE (???)
1366
1367         for (int tid=0; tid < cpuWaitList.size(); tid++) {
1368             activateWhenReady(tid);
1369         }
1370
1371         if (cpuWaitList.size() == 0)
1372             contextSwitch = true;
1373     }
1374 }
1375
1376 template <class Impl>
1377 void
1378 FullO3CPU<Impl>::updateThreadPriority()
1379 {
1380     if (activeThreads.size() > 1)
1381     {
1382         //DEFAULT TO ROUND ROBIN SCHEME
1383         //e.g. Move highest priority to end of thread list
1384         list<unsigned>::iterator list_begin = activeThreads.begin();
1385         list<unsigned>::iterator list_end   = activeThreads.end();
1386
1387         unsigned high_thread = *list_begin;
1388
1389         activeThreads.erase(list_begin);
1390
1391         activeThreads.push_back(high_thread);
1392     }
1393 }
1394
1395 // Forward declaration of FullO3CPU.
1396 template class FullO3CPU<O3CPUImpl>;