2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
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16 * Copyright (c) 2011 Regents of the University of California
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47 #include "arch/kernel_stats.hh"
48 #include "config/the_isa.hh"
49 #include "cpu/checker/cpu.hh"
50 #include "cpu/checker/thread_context.hh"
51 #include "cpu/o3/cpu.hh"
52 #include "cpu/o3/isa_specific.hh"
53 #include "cpu/o3/thread_context.hh"
54 #include "cpu/activity.hh"
55 #include "cpu/quiesce_event.hh"
56 #include "cpu/simple_thread.hh"
57 #include "cpu/thread_context.hh"
58 #include "debug/Activity.hh"
59 #include "debug/Drain.hh"
60 #include "debug/O3CPU.hh"
61 #include "debug/Quiesce.hh"
62 #include "enums/MemoryMode.hh"
63 #include "sim/core.hh"
64 #include "sim/full_system.hh"
65 #include "sim/process.hh"
66 #include "sim/stat_control.hh"
67 #include "sim/system.hh"
69 #if THE_ISA == ALPHA_ISA
70 #include "arch/alpha/osfpal.hh"
71 #include "debug/Activity.hh"
76 using namespace TheISA
;
79 BaseO3CPU::BaseO3CPU(BaseCPUParams
*params
)
92 FullO3CPU
<Impl
>::IcachePort::recvTimingResp(PacketPtr pkt
)
94 DPRINTF(O3CPU
, "Fetch unit received timing\n");
95 // We shouldn't ever get a block in ownership state
96 assert(!(pkt
->memInhibitAsserted() && !pkt
->sharedAsserted()));
97 fetch
->processCacheCompletion(pkt
);
104 FullO3CPU
<Impl
>::IcachePort::recvRetry()
109 template <class Impl
>
111 FullO3CPU
<Impl
>::DcachePort::recvTimingResp(PacketPtr pkt
)
113 return lsq
->recvTimingResp(pkt
);
116 template <class Impl
>
118 FullO3CPU
<Impl
>::DcachePort::recvTimingSnoopReq(PacketPtr pkt
)
120 lsq
->recvTimingSnoopReq(pkt
);
123 template <class Impl
>
125 FullO3CPU
<Impl
>::DcachePort::recvRetry()
130 template <class Impl
>
131 FullO3CPU
<Impl
>::TickEvent::TickEvent(FullO3CPU
<Impl
> *c
)
132 : Event(CPU_Tick_Pri
), cpu(c
)
136 template <class Impl
>
138 FullO3CPU
<Impl
>::TickEvent::process()
143 template <class Impl
>
145 FullO3CPU
<Impl
>::TickEvent::description() const
147 return "FullO3CPU tick";
150 template <class Impl
>
151 FullO3CPU
<Impl
>::FullO3CPU(DerivO3CPUParams
*params
)
159 removeInstsThisCycle(false),
161 decode(this, params
),
162 rename(this, params
),
164 commit(this, params
),
166 regFile(params
->numPhysIntRegs
,
167 params
->numPhysFloatRegs
,
168 params
->numPhysCCRegs
),
170 freeList(name() + ".freelist", ®File
),
174 scoreboard(name() + ".scoreboard",
175 regFile
.totalNumPhysRegs(), TheISA::NumMiscRegs
,
176 TheISA::ZeroReg
, TheISA::ZeroReg
),
178 isa(numThreads
, NULL
),
180 icachePort(&fetch
, this),
181 dcachePort(&iew
.ldstQueue
, this),
183 timeBuffer(params
->backComSize
, params
->forwardComSize
),
184 fetchQueue(params
->backComSize
, params
->forwardComSize
),
185 decodeQueue(params
->backComSize
, params
->forwardComSize
),
186 renameQueue(params
->backComSize
, params
->forwardComSize
),
187 iewQueue(params
->backComSize
, params
->forwardComSize
),
188 activityRec(name(), NumStages
,
189 params
->backComSize
+ params
->forwardComSize
,
193 system(params
->system
),
195 lastRunningCycle(curCycle())
197 if (!params
->switched_out
) {
200 _status
= SwitchedOut
;
203 if (params
->checker
) {
204 BaseCPU
*temp_checker
= params
->checker
;
205 checker
= dynamic_cast<Checker
<Impl
> *>(temp_checker
);
206 checker
->setIcachePort(&icachePort
);
207 checker
->setSystem(params
->system
);
213 thread
.resize(numThreads
);
214 tids
.resize(numThreads
);
217 // The stages also need their CPU pointer setup. However this
218 // must be done at the upper level CPU because they have pointers
219 // to the upper level CPU, and not this FullO3CPU.
221 // Set up Pointers to the activeThreads list for each stage
222 fetch
.setActiveThreads(&activeThreads
);
223 decode
.setActiveThreads(&activeThreads
);
224 rename
.setActiveThreads(&activeThreads
);
225 iew
.setActiveThreads(&activeThreads
);
226 commit
.setActiveThreads(&activeThreads
);
228 // Give each of the stages the time buffer they will use.
229 fetch
.setTimeBuffer(&timeBuffer
);
230 decode
.setTimeBuffer(&timeBuffer
);
231 rename
.setTimeBuffer(&timeBuffer
);
232 iew
.setTimeBuffer(&timeBuffer
);
233 commit
.setTimeBuffer(&timeBuffer
);
235 // Also setup each of the stages' queues.
236 fetch
.setFetchQueue(&fetchQueue
);
237 decode
.setFetchQueue(&fetchQueue
);
238 commit
.setFetchQueue(&fetchQueue
);
239 decode
.setDecodeQueue(&decodeQueue
);
240 rename
.setDecodeQueue(&decodeQueue
);
241 rename
.setRenameQueue(&renameQueue
);
242 iew
.setRenameQueue(&renameQueue
);
243 iew
.setIEWQueue(&iewQueue
);
244 commit
.setIEWQueue(&iewQueue
);
245 commit
.setRenameQueue(&renameQueue
);
247 commit
.setIEWStage(&iew
);
248 rename
.setIEWStage(&iew
);
249 rename
.setCommitStage(&commit
);
251 ThreadID active_threads
;
255 active_threads
= params
->workload
.size();
257 if (active_threads
> Impl::MaxThreads
) {
258 panic("Workload Size too large. Increase the 'MaxThreads' "
259 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
260 "or edit your workload size.");
264 //Make Sure That this a Valid Architeture
265 assert(params
->numPhysIntRegs
>= numThreads
* TheISA::NumIntRegs
);
266 assert(params
->numPhysFloatRegs
>= numThreads
* TheISA::NumFloatRegs
);
267 assert(params
->numPhysCCRegs
>= numThreads
* TheISA::NumCCRegs
);
269 rename
.setScoreboard(&scoreboard
);
270 iew
.setScoreboard(&scoreboard
);
272 // Setup the rename map for whichever stages need it.
273 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
274 isa
[tid
] = params
->isa
[tid
];
276 // Only Alpha has an FP zero register, so for other ISAs we
277 // use an invalid FP register index to avoid special treatment
278 // of any valid FP reg.
279 RegIndex invalidFPReg
= TheISA::NumFloatRegs
+ 1;
281 (THE_ISA
== ALPHA_ISA
) ? TheISA::ZeroReg
: invalidFPReg
;
283 commitRenameMap
[tid
].init(®File
, TheISA::ZeroReg
, fpZeroReg
,
286 renameMap
[tid
].init(®File
, TheISA::ZeroReg
, fpZeroReg
,
290 // Initialize rename map to assign physical registers to the
291 // architectural registers for active threads only.
292 for (ThreadID tid
= 0; tid
< active_threads
; tid
++) {
293 for (RegIndex ridx
= 0; ridx
< TheISA::NumIntRegs
; ++ridx
) {
294 // Note that we can't use the rename() method because we don't
295 // want special treatment for the zero register at this point
296 PhysRegIndex phys_reg
= freeList
.getIntReg();
297 renameMap
[tid
].setIntEntry(ridx
, phys_reg
);
298 commitRenameMap
[tid
].setIntEntry(ridx
, phys_reg
);
301 for (RegIndex ridx
= 0; ridx
< TheISA::NumFloatRegs
; ++ridx
) {
302 PhysRegIndex phys_reg
= freeList
.getFloatReg();
303 renameMap
[tid
].setFloatEntry(ridx
, phys_reg
);
304 commitRenameMap
[tid
].setFloatEntry(ridx
, phys_reg
);
307 for (RegIndex ridx
= 0; ridx
< TheISA::NumCCRegs
; ++ridx
) {
308 PhysRegIndex phys_reg
= freeList
.getCCReg();
309 renameMap
[tid
].setCCEntry(ridx
, phys_reg
);
310 commitRenameMap
[tid
].setCCEntry(ridx
, phys_reg
);
314 rename
.setRenameMap(renameMap
);
315 commit
.setRenameMap(commitRenameMap
);
316 rename
.setFreeList(&freeList
);
318 // Setup the ROB for whichever stages need it.
321 lastActivatedCycle
= 0;
323 // Give renameMap & rename stage access to the freeList;
324 for (ThreadID tid
= 0; tid
< numThreads
; tid
++)
325 globalSeqNum
[tid
] = 1;
328 DPRINTF(O3CPU
, "Creating O3CPU object.\n");
330 // Setup any thread state.
331 this->thread
.resize(this->numThreads
);
333 for (ThreadID tid
= 0; tid
< this->numThreads
; ++tid
) {
335 // SMT is not supported in FS mode yet.
336 assert(this->numThreads
== 1);
337 this->thread
[tid
] = new Thread(this, 0, NULL
);
339 if (tid
< params
->workload
.size()) {
340 DPRINTF(O3CPU
, "Workload[%i] process is %#x",
341 tid
, this->thread
[tid
]);
342 this->thread
[tid
] = new typename FullO3CPU
<Impl
>::Thread(
343 (typename
Impl::O3CPU
*)(this),
344 tid
, params
->workload
[tid
]);
346 //usedTids[tid] = true;
347 //threadMap[tid] = tid;
349 //Allocate Empty thread so M5 can use later
350 //when scheduling threads to CPU
351 Process
* dummy_proc
= NULL
;
353 this->thread
[tid
] = new typename FullO3CPU
<Impl
>::Thread(
354 (typename
Impl::O3CPU
*)(this),
356 //usedTids[tid] = false;
362 // Setup the TC that will serve as the interface to the threads/CPU.
363 O3ThreadContext
<Impl
> *o3_tc
= new O3ThreadContext
<Impl
>;
367 // If we're using a checker, then the TC should be the
368 // CheckerThreadContext.
369 if (params
->checker
) {
370 tc
= new CheckerThreadContext
<O3ThreadContext
<Impl
> >(
371 o3_tc
, this->checker
);
374 o3_tc
->cpu
= (typename
Impl::O3CPU
*)(this);
376 o3_tc
->thread
= this->thread
[tid
];
379 // Setup quiesce event.
380 this->thread
[tid
]->quiesceEvent
= new EndQuiesceEvent(tc
);
382 // Give the thread the TC.
383 this->thread
[tid
]->tc
= tc
;
385 // Add the TC to the CPU's list of TC's.
386 this->threadContexts
.push_back(tc
);
389 // FullO3CPU always requires an interrupt controller.
390 if (!params
->switched_out
&& !interrupts
) {
391 fatal("FullO3CPU %s has no interrupt controller.\n"
392 "Ensure createInterruptController() is called.\n", name());
395 for (ThreadID tid
= 0; tid
< this->numThreads
; tid
++)
396 this->thread
[tid
]->setFuncExeInst(0);
399 template <class Impl
>
400 FullO3CPU
<Impl
>::~FullO3CPU()
404 template <class Impl
>
406 FullO3CPU
<Impl
>::regProbePoints()
408 ppInstAccessComplete
= new ProbePointArg
<PacketPtr
>(getProbeManager(), "InstAccessComplete");
409 ppDataAccessComplete
= new ProbePointArg
<std::pair
<DynInstPtr
, PacketPtr
> >(getProbeManager(), "DataAccessComplete");
410 fetch
.regProbePoints();
411 iew
.regProbePoints();
412 commit
.regProbePoints();
415 template <class Impl
>
417 FullO3CPU
<Impl
>::regStats()
419 BaseO3CPU::regStats();
421 // Register any of the O3CPU's stats here.
423 .name(name() + ".timesIdled")
424 .desc("Number of times that the entire CPU went into an idle state and"
425 " unscheduled itself")
429 .name(name() + ".idleCycles")
430 .desc("Total number of cycles that the CPU has spent unscheduled due "
435 .name(name() + ".quiesceCycles")
436 .desc("Total number of cycles that CPU has spent quiesced or waiting "
438 .prereq(quiesceCycles
);
440 // Number of Instructions simulated
441 // --------------------------------
442 // Should probably be in Base CPU but need templated
443 // MaxThreads so put in here instead
446 .name(name() + ".committedInsts")
447 .desc("Number of Instructions Simulated")
448 .flags(Stats::total
);
452 .name(name() + ".committedOps")
453 .desc("Number of Ops (including micro ops) Simulated")
454 .flags(Stats::total
);
457 .name(name() + ".cpi")
458 .desc("CPI: Cycles Per Instruction")
460 cpi
= numCycles
/ committedInsts
;
463 .name(name() + ".cpi_total")
464 .desc("CPI: Total CPI of All Threads")
466 totalCpi
= numCycles
/ sum(committedInsts
);
469 .name(name() + ".ipc")
470 .desc("IPC: Instructions Per Cycle")
472 ipc
= committedInsts
/ numCycles
;
475 .name(name() + ".ipc_total")
476 .desc("IPC: Total IPC of All Threads")
478 totalIpc
= sum(committedInsts
) / numCycles
;
480 this->fetch
.regStats();
481 this->decode
.regStats();
482 this->rename
.regStats();
483 this->iew
.regStats();
484 this->commit
.regStats();
485 this->rob
.regStats();
488 .name(name() + ".int_regfile_reads")
489 .desc("number of integer regfile reads")
490 .prereq(intRegfileReads
);
493 .name(name() + ".int_regfile_writes")
494 .desc("number of integer regfile writes")
495 .prereq(intRegfileWrites
);
498 .name(name() + ".fp_regfile_reads")
499 .desc("number of floating regfile reads")
500 .prereq(fpRegfileReads
);
503 .name(name() + ".fp_regfile_writes")
504 .desc("number of floating regfile writes")
505 .prereq(fpRegfileWrites
);
508 .name(name() + ".cc_regfile_reads")
509 .desc("number of cc regfile reads")
510 .prereq(ccRegfileReads
);
513 .name(name() + ".cc_regfile_writes")
514 .desc("number of cc regfile writes")
515 .prereq(ccRegfileWrites
);
518 .name(name() + ".misc_regfile_reads")
519 .desc("number of misc regfile reads")
520 .prereq(miscRegfileReads
);
523 .name(name() + ".misc_regfile_writes")
524 .desc("number of misc regfile writes")
525 .prereq(miscRegfileWrites
);
528 template <class Impl
>
530 FullO3CPU
<Impl
>::tick()
532 DPRINTF(O3CPU
, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
533 assert(!switchedOut());
534 assert(getDrainState() != Drainable::Drained
);
540 //Tick each of the stages
551 // Now advance the time buffers
552 timeBuffer
.advance();
554 fetchQueue
.advance();
555 decodeQueue
.advance();
556 renameQueue
.advance();
559 activityRec
.advance();
561 if (removeInstsThisCycle
) {
562 cleanUpRemovedInsts();
565 if (!tickEvent
.scheduled()) {
566 if (_status
== SwitchedOut
) {
567 DPRINTF(O3CPU
, "Switched out!\n");
569 lastRunningCycle
= curCycle();
570 } else if (!activityRec
.active() || _status
== Idle
) {
571 DPRINTF(O3CPU
, "Idle!\n");
572 lastRunningCycle
= curCycle();
575 schedule(tickEvent
, clockEdge(Cycles(1)));
576 DPRINTF(O3CPU
, "Scheduling next tick!\n");
581 updateThreadPriority();
586 template <class Impl
>
588 FullO3CPU
<Impl
>::init()
592 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
593 // Set noSquashFromTC so that the CPU doesn't squash when initially
594 // setting up registers.
595 thread
[tid
]->noSquashFromTC
= true;
596 // Initialise the ThreadContext's memory proxies
597 thread
[tid
]->initMemProxies(thread
[tid
]->getTC());
600 if (FullSystem
&& !params()->switched_out
) {
601 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
602 ThreadContext
*src_tc
= threadContexts
[tid
];
603 TheISA::initCPU(src_tc
, src_tc
->contextId());
607 // Clear noSquashFromTC.
608 for (int tid
= 0; tid
< numThreads
; ++tid
)
609 thread
[tid
]->noSquashFromTC
= false;
611 commit
.setThreads(thread
);
614 template <class Impl
>
616 FullO3CPU
<Impl
>::startup()
619 for (int tid
= 0; tid
< numThreads
; ++tid
)
620 isa
[tid
]->startup(threadContexts
[tid
]);
622 fetch
.startupStage();
623 decode
.startupStage();
625 rename
.startupStage();
626 commit
.startupStage();
629 template <class Impl
>
631 FullO3CPU
<Impl
>::activateThread(ThreadID tid
)
633 list
<ThreadID
>::iterator isActive
=
634 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
636 DPRINTF(O3CPU
, "[tid:%i]: Calling activate thread.\n", tid
);
637 assert(!switchedOut());
639 if (isActive
== activeThreads
.end()) {
640 DPRINTF(O3CPU
, "[tid:%i]: Adding to active threads list\n",
643 activeThreads
.push_back(tid
);
647 template <class Impl
>
649 FullO3CPU
<Impl
>::deactivateThread(ThreadID tid
)
651 //Remove From Active List, if Active
652 list
<ThreadID
>::iterator thread_it
=
653 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
655 DPRINTF(O3CPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
656 assert(!switchedOut());
658 if (thread_it
!= activeThreads
.end()) {
659 DPRINTF(O3CPU
,"[tid:%i]: Removing from active threads list\n",
661 activeThreads
.erase(thread_it
);
664 fetch
.deactivateThread(tid
);
665 commit
.deactivateThread(tid
);
668 template <class Impl
>
670 FullO3CPU
<Impl
>::totalInsts() const
674 ThreadID size
= thread
.size();
675 for (ThreadID i
= 0; i
< size
; i
++)
676 total
+= thread
[i
]->numInst
;
681 template <class Impl
>
683 FullO3CPU
<Impl
>::totalOps() const
687 ThreadID size
= thread
.size();
688 for (ThreadID i
= 0; i
< size
; i
++)
689 total
+= thread
[i
]->numOp
;
694 template <class Impl
>
696 FullO3CPU
<Impl
>::activateContext(ThreadID tid
)
698 assert(!switchedOut());
700 // Needs to set each stage to running as well.
703 // We don't want to wake the CPU if it is drained. In that case,
704 // we just want to flag the thread as active and schedule the tick
705 // event from drainResume() instead.
706 if (getDrainState() == Drainable::Drained
)
709 // If we are time 0 or if the last activation time is in the past,
710 // schedule the next tick and wake up the fetch unit
711 if (lastActivatedCycle
== 0 || lastActivatedCycle
< curTick()) {
712 scheduleTickEvent(Cycles(0));
714 // Be sure to signal that there's some activity so the CPU doesn't
715 // deschedule itself.
716 activityRec
.activity();
717 fetch
.wakeFromQuiesce();
719 Cycles
cycles(curCycle() - lastRunningCycle
);
720 // @todo: This is an oddity that is only here to match the stats
723 quiesceCycles
+= cycles
;
725 lastActivatedCycle
= curTick();
731 template <class Impl
>
733 FullO3CPU
<Impl
>::suspendContext(ThreadID tid
)
735 DPRINTF(O3CPU
,"[tid: %i]: Suspending Thread Context.\n", tid
);
736 assert(!switchedOut());
738 deactivateThread(tid
);
740 // If this was the last thread then unschedule the tick event.
741 if (activeThreads
.size() == 0)
742 unscheduleTickEvent();
744 DPRINTF(Quiesce
, "Suspending Context\n");
745 lastRunningCycle
= curCycle();
749 template <class Impl
>
751 FullO3CPU
<Impl
>::haltContext(ThreadID tid
)
753 //For now, this is the same as deallocate
754 DPRINTF(O3CPU
,"[tid:%i]: Halt Context called. Deallocating", tid
);
755 assert(!switchedOut());
757 deactivateThread(tid
);
761 template <class Impl
>
763 FullO3CPU
<Impl
>::insertThread(ThreadID tid
)
765 DPRINTF(O3CPU
,"[tid:%i] Initializing thread into CPU");
766 // Will change now that the PC and thread state is internal to the CPU
767 // and not in the ThreadContext.
768 ThreadContext
*src_tc
;
770 src_tc
= system
->threadContexts
[tid
];
772 src_tc
= tcBase(tid
);
774 //Bind Int Regs to Rename Map
775 for (int ireg
= 0; ireg
< TheISA::NumIntRegs
; ireg
++) {
776 PhysRegIndex phys_reg
= freeList
.getIntReg();
778 renameMap
[tid
].setEntry(ireg
,phys_reg
);
779 scoreboard
.setReg(phys_reg
);
782 //Bind Float Regs to Rename Map
783 int max_reg
= TheISA::NumIntRegs
+ TheISA::NumFloatRegs
;
784 for (int freg
= TheISA::NumIntRegs
; freg
< max_reg
; freg
++) {
785 PhysRegIndex phys_reg
= freeList
.getFloatReg();
787 renameMap
[tid
].setEntry(freg
,phys_reg
);
788 scoreboard
.setReg(phys_reg
);
791 //Bind condition-code Regs to Rename Map
792 max_reg
= TheISA::NumIntRegs
+ TheISA::NumFloatRegs
+ TheISA::NumCCRegs
;
793 for (int creg
= TheISA::NumIntRegs
+ TheISA::NumFloatRegs
;
794 creg
< max_reg
; creg
++) {
795 PhysRegIndex phys_reg
= freeList
.getCCReg();
797 renameMap
[tid
].setEntry(creg
,phys_reg
);
798 scoreboard
.setReg(phys_reg
);
801 //Copy Thread Data Into RegFile
802 //this->copyFromTC(tid);
805 pcState(src_tc
->pcState(), tid
);
807 src_tc
->setStatus(ThreadContext::Active
);
809 activateContext(tid
);
811 //Reset ROB/IQ/LSQ Entries
812 commit
.rob
->resetEntries();
816 template <class Impl
>
818 FullO3CPU
<Impl
>::removeThread(ThreadID tid
)
820 DPRINTF(O3CPU
,"[tid:%i] Removing thread context from CPU.\n", tid
);
822 // Copy Thread Data From RegFile
823 // If thread is suspended, it might be re-allocated
824 // this->copyToTC(tid);
827 // @todo: 2-27-2008: Fix how we free up rename mappings
828 // here to alleviate the case for double-freeing registers
831 // Unbind Int Regs from Rename Map
832 for (int ireg
= 0; ireg
< TheISA::NumIntRegs
; ireg
++) {
833 PhysRegIndex phys_reg
= renameMap
[tid
].lookup(ireg
);
835 scoreboard
.unsetReg(phys_reg
);
836 freeList
.addReg(phys_reg
);
839 // Unbind Float Regs from Rename Map
840 int max_reg
= TheISA::NumIntRegs
+ TheISA::NumFloatRegs
;
841 for (int freg
= TheISA::NumIntRegs
; freg
< max_reg
; freg
++) {
842 PhysRegIndex phys_reg
= renameMap
[tid
].lookup(freg
);
844 scoreboard
.unsetReg(phys_reg
);
845 freeList
.addReg(phys_reg
);
848 // Unbind condition-code Regs from Rename Map
849 max_reg
= TheISA::NumIntRegs
+ TheISA::NumFloatRegs
+ TheISA::NumCCRegs
;
850 for (int creg
= TheISA::NumIntRegs
+ TheISA::NumFloatRegs
;
851 creg
< max_reg
; creg
++) {
852 PhysRegIndex phys_reg
= renameMap
[tid
].lookup(creg
);
854 scoreboard
.unsetReg(phys_reg
);
855 freeList
.addReg(phys_reg
);
858 // Squash Throughout Pipeline
859 DynInstPtr inst
= commit
.rob
->readHeadInst(tid
);
860 InstSeqNum squash_seq_num
= inst
->seqNum
;
861 fetch
.squash(0, squash_seq_num
, inst
, tid
);
863 rename
.squash(squash_seq_num
, tid
);
865 iew
.ldstQueue
.squash(squash_seq_num
, tid
);
866 commit
.rob
->squash(squash_seq_num
, tid
);
869 assert(iew
.instQueue
.getCount(tid
) == 0);
870 assert(iew
.ldstQueue
.getCount(tid
) == 0);
872 // Reset ROB/IQ/LSQ Entries
874 // Commented out for now. This should be possible to do by
875 // telling all the pipeline stages to drain first, and then
876 // checking until the drain completes. Once the pipeline is
877 // drained, call resetEntries(). - 10-09-06 ktlim
879 if (activeThreads.size() >= 1) {
880 commit.rob->resetEntries();
886 template <class Impl
>
888 FullO3CPU
<Impl
>::hwrei(ThreadID tid
)
890 #if THE_ISA == ALPHA_ISA
891 // Need to clear the lock flag upon returning from an interrupt.
892 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG
, false, tid
);
894 this->thread
[tid
]->kernelStats
->hwrei();
896 // FIXME: XXX check for interrupts? XXX
901 template <class Impl
>
903 FullO3CPU
<Impl
>::simPalCheck(int palFunc
, ThreadID tid
)
905 #if THE_ISA == ALPHA_ISA
906 if (this->thread
[tid
]->kernelStats
)
907 this->thread
[tid
]->kernelStats
->callpal(palFunc
,
908 this->threadContexts
[tid
]);
913 if (--System::numSystemsRunning
== 0)
914 exitSimLoop("all cpus halted");
919 if (this->system
->breakpoint())
927 template <class Impl
>
929 FullO3CPU
<Impl
>::getInterrupts()
931 // Check if there are any outstanding interrupts
932 return this->interrupts
->getInterrupt(this->threadContexts
[0]);
935 template <class Impl
>
937 FullO3CPU
<Impl
>::processInterrupts(const Fault
&interrupt
)
939 // Check for interrupts here. For now can copy the code that
940 // exists within isa_fullsys_traits.hh. Also assume that thread 0
941 // is the one that handles the interrupts.
942 // @todo: Possibly consolidate the interrupt checking code.
943 // @todo: Allow other threads to handle interrupts.
945 assert(interrupt
!= NoFault
);
946 this->interrupts
->updateIntrInfo(this->threadContexts
[0]);
948 DPRINTF(O3CPU
, "Interrupt %s being handled\n", interrupt
->name());
949 this->trap(interrupt
, 0, NULL
);
952 template <class Impl
>
954 FullO3CPU
<Impl
>::trap(const Fault
&fault
, ThreadID tid
, StaticInstPtr inst
)
956 // Pass the thread's TC into the invoke method.
957 fault
->invoke(this->threadContexts
[tid
], inst
);
960 template <class Impl
>
962 FullO3CPU
<Impl
>::syscall(int64_t callnum
, ThreadID tid
)
964 DPRINTF(O3CPU
, "[tid:%i] Executing syscall().\n\n", tid
);
966 DPRINTF(Activity
,"Activity: syscall() called.\n");
968 // Temporarily increase this by one to account for the syscall
970 ++(this->thread
[tid
]->funcExeInst
);
972 // Execute the actual syscall.
973 this->thread
[tid
]->syscall(callnum
);
975 // Decrease funcExeInst by one as the normal commit will handle
977 --(this->thread
[tid
]->funcExeInst
);
980 template <class Impl
>
982 FullO3CPU
<Impl
>::serializeThread(std::ostream
&os
, ThreadID tid
)
984 thread
[tid
]->serialize(os
);
987 template <class Impl
>
989 FullO3CPU
<Impl
>::unserializeThread(Checkpoint
*cp
, const std::string
§ion
,
992 thread
[tid
]->unserialize(cp
, section
);
995 template <class Impl
>
997 FullO3CPU
<Impl
>::drain(DrainManager
*drain_manager
)
999 // If the CPU isn't doing anything, then return immediately.
1000 if (switchedOut()) {
1001 setDrainState(Drainable::Drained
);
1005 DPRINTF(Drain
, "Draining...\n");
1006 setDrainState(Drainable::Draining
);
1008 // We only need to signal a drain to the commit stage as this
1009 // initiates squashing controls the draining. Once the commit
1010 // stage commits an instruction where it is safe to stop, it'll
1011 // squash the rest of the instructions in the pipeline and force
1012 // the fetch stage to stall. The pipeline will be drained once all
1013 // in-flight instructions have retired.
1016 // Wake the CPU and record activity so everything can drain out if
1017 // the CPU was not able to immediately drain.
1019 drainManager
= drain_manager
;
1022 activityRec
.activity();
1024 DPRINTF(Drain
, "CPU not drained\n");
1028 setDrainState(Drainable::Drained
);
1029 DPRINTF(Drain
, "CPU is already drained\n");
1030 if (tickEvent
.scheduled())
1031 deschedule(tickEvent
);
1033 // Flush out any old data from the time buffers. In
1034 // particular, there might be some data in flight from the
1035 // fetch stage that isn't visible in any of the CPU buffers we
1036 // test in isDrained().
1037 for (int i
= 0; i
< timeBuffer
.getSize(); ++i
) {
1038 timeBuffer
.advance();
1039 fetchQueue
.advance();
1040 decodeQueue
.advance();
1041 renameQueue
.advance();
1050 template <class Impl
>
1052 FullO3CPU
<Impl
>::tryDrain()
1054 if (!drainManager
|| !isDrained())
1057 if (tickEvent
.scheduled())
1058 deschedule(tickEvent
);
1060 DPRINTF(Drain
, "CPU done draining, processing drain event\n");
1061 drainManager
->signalDrainDone();
1062 drainManager
= NULL
;
1067 template <class Impl
>
1069 FullO3CPU
<Impl
>::drainSanityCheck() const
1071 assert(isDrained());
1072 fetch
.drainSanityCheck();
1073 decode
.drainSanityCheck();
1074 rename
.drainSanityCheck();
1075 iew
.drainSanityCheck();
1076 commit
.drainSanityCheck();
1079 template <class Impl
>
1081 FullO3CPU
<Impl
>::isDrained() const
1085 if (!instList
.empty() || !removeList
.empty()) {
1086 DPRINTF(Drain
, "Main CPU structures not drained.\n");
1090 if (!fetch
.isDrained()) {
1091 DPRINTF(Drain
, "Fetch not drained.\n");
1095 if (!decode
.isDrained()) {
1096 DPRINTF(Drain
, "Decode not drained.\n");
1100 if (!rename
.isDrained()) {
1101 DPRINTF(Drain
, "Rename not drained.\n");
1105 if (!iew
.isDrained()) {
1106 DPRINTF(Drain
, "IEW not drained.\n");
1110 if (!commit
.isDrained()) {
1111 DPRINTF(Drain
, "Commit not drained.\n");
1118 template <class Impl
>
1120 FullO3CPU
<Impl
>::commitDrained(ThreadID tid
)
1122 fetch
.drainStall(tid
);
1125 template <class Impl
>
1127 FullO3CPU
<Impl
>::drainResume()
1129 setDrainState(Drainable::Running
);
1133 DPRINTF(Drain
, "Resuming...\n");
1136 fetch
.drainResume();
1137 commit
.drainResume();
1140 for (ThreadID i
= 0; i
< thread
.size(); i
++) {
1141 if (thread
[i
]->status() == ThreadContext::Active
) {
1142 DPRINTF(Drain
, "Activating thread: %i\n", i
);
1148 assert(!tickEvent
.scheduled());
1149 if (_status
== Running
)
1150 schedule(tickEvent
, nextCycle());
1153 template <class Impl
>
1155 FullO3CPU
<Impl
>::switchOut()
1157 DPRINTF(O3CPU
, "Switching out\n");
1158 BaseCPU::switchOut();
1160 activityRec
.reset();
1162 _status
= SwitchedOut
;
1165 checker
->switchOut();
1168 template <class Impl
>
1170 FullO3CPU
<Impl
>::takeOverFrom(BaseCPU
*oldCPU
)
1172 BaseCPU::takeOverFrom(oldCPU
);
1174 fetch
.takeOverFrom();
1175 decode
.takeOverFrom();
1176 rename
.takeOverFrom();
1178 commit
.takeOverFrom();
1180 assert(!tickEvent
.scheduled());
1182 FullO3CPU
<Impl
> *oldO3CPU
= dynamic_cast<FullO3CPU
<Impl
>*>(oldCPU
);
1184 globalSeqNum
= oldO3CPU
->globalSeqNum
;
1186 lastRunningCycle
= curCycle();
1190 template <class Impl
>
1192 FullO3CPU
<Impl
>::verifyMemoryMode() const
1194 if (!system
->isTimingMode()) {
1195 fatal("The O3 CPU requires the memory system to be in "
1196 "'timing' mode.\n");
1200 template <class Impl
>
1202 FullO3CPU
<Impl
>::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1204 return this->isa
[tid
]->readMiscRegNoEffect(misc_reg
);
1207 template <class Impl
>
1209 FullO3CPU
<Impl
>::readMiscReg(int misc_reg
, ThreadID tid
)
1212 return this->isa
[tid
]->readMiscReg(misc_reg
, tcBase(tid
));
1215 template <class Impl
>
1217 FullO3CPU
<Impl
>::setMiscRegNoEffect(int misc_reg
,
1218 const TheISA::MiscReg
&val
, ThreadID tid
)
1220 this->isa
[tid
]->setMiscRegNoEffect(misc_reg
, val
);
1223 template <class Impl
>
1225 FullO3CPU
<Impl
>::setMiscReg(int misc_reg
,
1226 const TheISA::MiscReg
&val
, ThreadID tid
)
1228 miscRegfileWrites
++;
1229 this->isa
[tid
]->setMiscReg(misc_reg
, val
, tcBase(tid
));
1232 template <class Impl
>
1234 FullO3CPU
<Impl
>::readIntReg(int reg_idx
)
1237 return regFile
.readIntReg(reg_idx
);
1240 template <class Impl
>
1242 FullO3CPU
<Impl
>::readFloatReg(int reg_idx
)
1245 return regFile
.readFloatReg(reg_idx
);
1248 template <class Impl
>
1250 FullO3CPU
<Impl
>::readFloatRegBits(int reg_idx
)
1253 return regFile
.readFloatRegBits(reg_idx
);
1256 template <class Impl
>
1258 FullO3CPU
<Impl
>::readCCReg(int reg_idx
)
1261 return regFile
.readCCReg(reg_idx
);
1264 template <class Impl
>
1266 FullO3CPU
<Impl
>::setIntReg(int reg_idx
, uint64_t val
)
1269 regFile
.setIntReg(reg_idx
, val
);
1272 template <class Impl
>
1274 FullO3CPU
<Impl
>::setFloatReg(int reg_idx
, FloatReg val
)
1277 regFile
.setFloatReg(reg_idx
, val
);
1280 template <class Impl
>
1282 FullO3CPU
<Impl
>::setFloatRegBits(int reg_idx
, FloatRegBits val
)
1285 regFile
.setFloatRegBits(reg_idx
, val
);
1288 template <class Impl
>
1290 FullO3CPU
<Impl
>::setCCReg(int reg_idx
, CCReg val
)
1293 regFile
.setCCReg(reg_idx
, val
);
1296 template <class Impl
>
1298 FullO3CPU
<Impl
>::readArchIntReg(int reg_idx
, ThreadID tid
)
1301 PhysRegIndex phys_reg
= commitRenameMap
[tid
].lookupInt(reg_idx
);
1303 return regFile
.readIntReg(phys_reg
);
1306 template <class Impl
>
1308 FullO3CPU
<Impl
>::readArchFloatReg(int reg_idx
, ThreadID tid
)
1311 PhysRegIndex phys_reg
= commitRenameMap
[tid
].lookupFloat(reg_idx
);
1313 return regFile
.readFloatReg(phys_reg
);
1316 template <class Impl
>
1318 FullO3CPU
<Impl
>::readArchFloatRegInt(int reg_idx
, ThreadID tid
)
1321 PhysRegIndex phys_reg
= commitRenameMap
[tid
].lookupFloat(reg_idx
);
1323 return regFile
.readFloatRegBits(phys_reg
);
1326 template <class Impl
>
1328 FullO3CPU
<Impl
>::readArchCCReg(int reg_idx
, ThreadID tid
)
1331 PhysRegIndex phys_reg
= commitRenameMap
[tid
].lookupCC(reg_idx
);
1333 return regFile
.readCCReg(phys_reg
);
1336 template <class Impl
>
1338 FullO3CPU
<Impl
>::setArchIntReg(int reg_idx
, uint64_t val
, ThreadID tid
)
1341 PhysRegIndex phys_reg
= commitRenameMap
[tid
].lookupInt(reg_idx
);
1343 regFile
.setIntReg(phys_reg
, val
);
1346 template <class Impl
>
1348 FullO3CPU
<Impl
>::setArchFloatReg(int reg_idx
, float val
, ThreadID tid
)
1351 PhysRegIndex phys_reg
= commitRenameMap
[tid
].lookupFloat(reg_idx
);
1353 regFile
.setFloatReg(phys_reg
, val
);
1356 template <class Impl
>
1358 FullO3CPU
<Impl
>::setArchFloatRegInt(int reg_idx
, uint64_t val
, ThreadID tid
)
1361 PhysRegIndex phys_reg
= commitRenameMap
[tid
].lookupFloat(reg_idx
);
1363 regFile
.setFloatRegBits(phys_reg
, val
);
1366 template <class Impl
>
1368 FullO3CPU
<Impl
>::setArchCCReg(int reg_idx
, CCReg val
, ThreadID tid
)
1371 PhysRegIndex phys_reg
= commitRenameMap
[tid
].lookupCC(reg_idx
);
1373 regFile
.setCCReg(phys_reg
, val
);
1376 template <class Impl
>
1378 FullO3CPU
<Impl
>::pcState(ThreadID tid
)
1380 return commit
.pcState(tid
);
1383 template <class Impl
>
1385 FullO3CPU
<Impl
>::pcState(const TheISA::PCState
&val
, ThreadID tid
)
1387 commit
.pcState(val
, tid
);
1390 template <class Impl
>
1392 FullO3CPU
<Impl
>::instAddr(ThreadID tid
)
1394 return commit
.instAddr(tid
);
1397 template <class Impl
>
1399 FullO3CPU
<Impl
>::nextInstAddr(ThreadID tid
)
1401 return commit
.nextInstAddr(tid
);
1404 template <class Impl
>
1406 FullO3CPU
<Impl
>::microPC(ThreadID tid
)
1408 return commit
.microPC(tid
);
1411 template <class Impl
>
1413 FullO3CPU
<Impl
>::squashFromTC(ThreadID tid
)
1415 this->thread
[tid
]->noSquashFromTC
= true;
1416 this->commit
.generateTCEvent(tid
);
1419 template <class Impl
>
1420 typename FullO3CPU
<Impl
>::ListIt
1421 FullO3CPU
<Impl
>::addInst(DynInstPtr
&inst
)
1423 instList
.push_back(inst
);
1425 return --(instList
.end());
1428 template <class Impl
>
1430 FullO3CPU
<Impl
>::instDone(ThreadID tid
, DynInstPtr
&inst
)
1432 // Keep an instruction count.
1433 if (!inst
->isMicroop() || inst
->isLastMicroop()) {
1434 thread
[tid
]->numInst
++;
1435 thread
[tid
]->numInsts
++;
1436 committedInsts
[tid
]++;
1438 thread
[tid
]->numOp
++;
1439 thread
[tid
]->numOps
++;
1440 committedOps
[tid
]++;
1442 system
->totalNumInsts
++;
1443 // Check for instruction-count-based events.
1444 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numInst
);
1445 system
->instEventQueue
.serviceEvents(system
->totalNumInsts
);
1448 template <class Impl
>
1450 FullO3CPU
<Impl
>::removeFrontInst(DynInstPtr
&inst
)
1452 DPRINTF(O3CPU
, "Removing committed instruction [tid:%i] PC %s "
1454 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1456 removeInstsThisCycle
= true;
1458 // Remove the front instruction.
1459 removeList
.push(inst
->getInstListIt());
1462 template <class Impl
>
1464 FullO3CPU
<Impl
>::removeInstsNotInROB(ThreadID tid
)
1466 DPRINTF(O3CPU
, "Thread %i: Deleting instructions from instruction"
1471 bool rob_empty
= false;
1473 if (instList
.empty()) {
1475 } else if (rob
.isEmpty(tid
)) {
1476 DPRINTF(O3CPU
, "ROB is empty, squashing all insts.\n");
1477 end_it
= instList
.begin();
1480 end_it
= (rob
.readTailInst(tid
))->getInstListIt();
1481 DPRINTF(O3CPU
, "ROB is not empty, squashing insts not in ROB.\n");
1484 removeInstsThisCycle
= true;
1486 ListIt inst_it
= instList
.end();
1490 // Walk through the instruction list, removing any instructions
1491 // that were inserted after the given instruction iterator, end_it.
1492 while (inst_it
!= end_it
) {
1493 assert(!instList
.empty());
1495 squashInstIt(inst_it
, tid
);
1500 // If the ROB was empty, then we actually need to remove the first
1501 // instruction as well.
1503 squashInstIt(inst_it
, tid
);
1507 template <class Impl
>
1509 FullO3CPU
<Impl
>::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1511 assert(!instList
.empty());
1513 removeInstsThisCycle
= true;
1515 ListIt inst_iter
= instList
.end();
1519 DPRINTF(O3CPU
, "Deleting instructions from instruction "
1520 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1521 tid
, seq_num
, (*inst_iter
)->seqNum
);
1523 while ((*inst_iter
)->seqNum
> seq_num
) {
1525 bool break_loop
= (inst_iter
== instList
.begin());
1527 squashInstIt(inst_iter
, tid
);
1536 template <class Impl
>
1538 FullO3CPU
<Impl
>::squashInstIt(const ListIt
&instIt
, ThreadID tid
)
1540 if ((*instIt
)->threadNumber
== tid
) {
1541 DPRINTF(O3CPU
, "Squashing instruction, "
1542 "[tid:%i] [sn:%lli] PC %s\n",
1543 (*instIt
)->threadNumber
,
1545 (*instIt
)->pcState());
1547 // Mark it as squashed.
1548 (*instIt
)->setSquashed();
1550 // @todo: Formulate a consistent method for deleting
1551 // instructions from the instruction list
1552 // Remove the instruction from the list.
1553 removeList
.push(instIt
);
1557 template <class Impl
>
1559 FullO3CPU
<Impl
>::cleanUpRemovedInsts()
1561 while (!removeList
.empty()) {
1562 DPRINTF(O3CPU
, "Removing instruction, "
1563 "[tid:%i] [sn:%lli] PC %s\n",
1564 (*removeList
.front())->threadNumber
,
1565 (*removeList
.front())->seqNum
,
1566 (*removeList
.front())->pcState());
1568 instList
.erase(removeList
.front());
1573 removeInstsThisCycle
= false;
1576 template <class Impl>
1578 FullO3CPU<Impl>::removeAllInsts()
1583 template <class Impl
>
1585 FullO3CPU
<Impl
>::dumpInsts()
1589 ListIt inst_list_it
= instList
.begin();
1591 cprintf("Dumping Instruction List\n");
1593 while (inst_list_it
!= instList
.end()) {
1594 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1596 num
, (*inst_list_it
)->instAddr(), (*inst_list_it
)->threadNumber
,
1597 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1598 (*inst_list_it
)->isSquashed());
1604 template <class Impl>
1606 FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1608 iew.wakeDependents(inst);
1611 template <class Impl
>
1613 FullO3CPU
<Impl
>::wakeCPU()
1615 if (activityRec
.active() || tickEvent
.scheduled()) {
1616 DPRINTF(Activity
, "CPU already running.\n");
1620 DPRINTF(Activity
, "Waking up CPU\n");
1622 Cycles
cycles(curCycle() - lastRunningCycle
);
1623 // @todo: This is an oddity that is only here to match the stats
1626 idleCycles
+= cycles
;
1627 numCycles
+= cycles
;
1629 schedule(tickEvent
, clockEdge());
1632 template <class Impl
>
1634 FullO3CPU
<Impl
>::wakeup()
1636 if (this->thread
[0]->status() != ThreadContext::Suspended
)
1641 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1642 this->threadContexts
[0]->activate();
1645 template <class Impl
>
1647 FullO3CPU
<Impl
>::getFreeTid()
1649 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
1656 return InvalidThreadID
;
1659 template <class Impl
>
1661 FullO3CPU
<Impl
>::updateThreadPriority()
1663 if (activeThreads
.size() > 1) {
1664 //DEFAULT TO ROUND ROBIN SCHEME
1665 //e.g. Move highest priority to end of thread list
1666 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
1668 unsigned high_thread
= *list_begin
;
1670 activeThreads
.erase(list_begin
);
1672 activeThreads
.push_back(high_thread
);
1676 // Forward declaration of FullO3CPU.
1677 template class FullO3CPU
<O3CPUImpl
>;