2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include "config/full_system.hh"
33 #include "config/use_checker.hh"
36 #include "sim/system.hh"
38 #include "sim/process.hh"
41 #include "cpu/activity.hh"
42 #include "cpu/simple_thread.hh"
43 #include "cpu/thread_context.hh"
44 #include "cpu/o3/isa_specific.hh"
45 #include "cpu/o3/cpu.hh"
47 #include "sim/root.hh"
48 #include "sim/stat_control.hh"
51 #include "cpu/checker/cpu.hh"
55 using namespace TheISA
;
57 BaseO3CPU::BaseO3CPU(Params
*params
)
58 : BaseCPU(params
), cpu_id(0)
69 FullO3CPU
<Impl
>::TickEvent::TickEvent(FullO3CPU
<Impl
> *c
)
70 : Event(&mainEventQueue
, CPU_Tick_Pri
), cpu(c
)
76 FullO3CPU
<Impl
>::TickEvent::process()
83 FullO3CPU
<Impl
>::TickEvent::description()
85 return "FullO3CPU tick event";
89 FullO3CPU
<Impl
>::ActivateThreadEvent::ActivateThreadEvent()
90 : Event(&mainEventQueue
, CPU_Tick_Pri
)
96 FullO3CPU
<Impl
>::ActivateThreadEvent::init(int thread_num
,
97 FullO3CPU
<Impl
> *thread_cpu
)
103 template <class Impl
>
105 FullO3CPU
<Impl
>::ActivateThreadEvent::process()
107 cpu
->activateThread(tid
);
110 template <class Impl
>
112 FullO3CPU
<Impl
>::ActivateThreadEvent::description()
114 return "FullO3CPU \"Activate Thread\" event";
117 template <class Impl
>
118 FullO3CPU
<Impl
>::DeallocateContextEvent::DeallocateContextEvent()
119 : Event(&mainEventQueue
, CPU_Tick_Pri
)
123 template <class Impl
>
125 FullO3CPU
<Impl
>::DeallocateContextEvent::init(int thread_num
,
126 FullO3CPU
<Impl
> *thread_cpu
)
132 template <class Impl
>
134 FullO3CPU
<Impl
>::DeallocateContextEvent::process()
136 cpu
->deactivateThread(tid
);
137 cpu
->removeThread(tid
);
140 template <class Impl
>
142 FullO3CPU
<Impl
>::DeallocateContextEvent::description()
144 return "FullO3CPU \"Deallocate Context\" event";
147 template <class Impl
>
148 FullO3CPU
<Impl
>::FullO3CPU(Params
*params
)
151 removeInstsThisCycle(false),
158 regFile(params
->numPhysIntRegs
, params
->numPhysFloatRegs
),
160 freeList(params
->numberOfThreads
,
161 TheISA::NumIntRegs
, params
->numPhysIntRegs
,
162 TheISA::NumFloatRegs
, params
->numPhysFloatRegs
),
164 rob(params
->numROBEntries
, params
->squashWidth
,
165 params
->smtROBPolicy
, params
->smtROBThreshold
,
166 params
->numberOfThreads
),
168 scoreboard(params
->numberOfThreads
,
169 TheISA::NumIntRegs
, params
->numPhysIntRegs
,
170 TheISA::NumFloatRegs
, params
->numPhysFloatRegs
,
171 TheISA::NumMiscRegs
* number_of_threads
,
174 timeBuffer(params
->backComSize
, params
->forwardComSize
),
175 fetchQueue(params
->backComSize
, params
->forwardComSize
),
176 decodeQueue(params
->backComSize
, params
->forwardComSize
),
177 renameQueue(params
->backComSize
, params
->forwardComSize
),
178 iewQueue(params
->backComSize
, params
->forwardComSize
),
179 activityRec(NumStages
,
180 params
->backComSize
+ params
->forwardComSize
,
186 system(params
->system
),
187 physmem(system
->physmem
),
188 #endif // FULL_SYSTEM
191 deferRegistration(params
->deferRegistration
),
192 numThreads(number_of_threads
)
198 if (params
->checker
) {
200 BaseCPU
*temp_checker
= params
->checker
;
201 checker
= dynamic_cast<Checker
<DynInstPtr
> *>(temp_checker
);
202 checker
->setMemory(mem
);
204 checker
->setSystem(params
->system
);
207 panic("Checker enabled but not compiled in!");
208 #endif // USE_CHECKER
212 thread
.resize(number_of_threads
);
213 tids
.resize(number_of_threads
);
216 // The stages also need their CPU pointer setup. However this
217 // must be done at the upper level CPU because they have pointers
218 // to the upper level CPU, and not this FullO3CPU.
220 // Set up Pointers to the activeThreads list for each stage
221 fetch
.setActiveThreads(&activeThreads
);
222 decode
.setActiveThreads(&activeThreads
);
223 rename
.setActiveThreads(&activeThreads
);
224 iew
.setActiveThreads(&activeThreads
);
225 commit
.setActiveThreads(&activeThreads
);
227 // Give each of the stages the time buffer they will use.
228 fetch
.setTimeBuffer(&timeBuffer
);
229 decode
.setTimeBuffer(&timeBuffer
);
230 rename
.setTimeBuffer(&timeBuffer
);
231 iew
.setTimeBuffer(&timeBuffer
);
232 commit
.setTimeBuffer(&timeBuffer
);
234 // Also setup each of the stages' queues.
235 fetch
.setFetchQueue(&fetchQueue
);
236 decode
.setFetchQueue(&fetchQueue
);
237 commit
.setFetchQueue(&fetchQueue
);
238 decode
.setDecodeQueue(&decodeQueue
);
239 rename
.setDecodeQueue(&decodeQueue
);
240 rename
.setRenameQueue(&renameQueue
);
241 iew
.setRenameQueue(&renameQueue
);
242 iew
.setIEWQueue(&iewQueue
);
243 commit
.setIEWQueue(&iewQueue
);
244 commit
.setRenameQueue(&renameQueue
);
246 commit
.setIEWStage(&iew
);
247 rename
.setIEWStage(&iew
);
248 rename
.setCommitStage(&commit
);
251 int active_threads
= params
->workload
.size();
253 if (active_threads
> Impl::MaxThreads
) {
254 panic("Workload Size too large. Increase the 'MaxThreads'"
255 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
256 "edit your workload size.");
259 int active_threads
= 1;
262 //Make Sure That this a Valid Architeture
263 assert(params
->numPhysIntRegs
>= numThreads
* TheISA::NumIntRegs
);
264 assert(params
->numPhysFloatRegs
>= numThreads
* TheISA::NumFloatRegs
);
266 rename
.setScoreboard(&scoreboard
);
267 iew
.setScoreboard(&scoreboard
);
269 // Setup the rename map for whichever stages need it.
270 PhysRegIndex lreg_idx
= 0;
271 PhysRegIndex freg_idx
= params
->numPhysIntRegs
; //Index to 1 after int regs
273 for (int tid
=0; tid
< numThreads
; tid
++) {
274 bool bindRegs
= (tid
<= active_threads
- 1);
276 commitRenameMap
[tid
].init(TheISA::NumIntRegs
,
277 params
->numPhysIntRegs
,
278 lreg_idx
, //Index for Logical. Regs
280 TheISA::NumFloatRegs
,
281 params
->numPhysFloatRegs
,
282 freg_idx
, //Index for Float Regs
292 renameMap
[tid
].init(TheISA::NumIntRegs
,
293 params
->numPhysIntRegs
,
294 lreg_idx
, //Index for Logical. Regs
296 TheISA::NumFloatRegs
,
297 params
->numPhysFloatRegs
,
298 freg_idx
, //Index for Float Regs
309 rename
.setRenameMap(renameMap
);
310 commit
.setRenameMap(commitRenameMap
);
312 // Give renameMap & rename stage access to the freeList;
313 for (int i
=0; i
< numThreads
; i
++) {
314 renameMap
[i
].setFreeList(&freeList
);
316 rename
.setFreeList(&freeList
);
318 // Setup the ROB for whichever stages need it.
321 lastRunningCycle
= curTick
;
323 lastActivatedCycle
= -1;
325 contextSwitch
= false;
328 template <class Impl
>
329 FullO3CPU
<Impl
>::~FullO3CPU()
333 template <class Impl
>
335 FullO3CPU
<Impl
>::fullCPURegStats()
337 BaseO3CPU::regStats();
339 // Register any of the O3CPU's stats here.
341 .name(name() + ".timesIdled")
342 .desc("Number of times that the entire CPU went into an idle state and"
343 " unscheduled itself")
347 .name(name() + ".idleCycles")
348 .desc("Total number of cycles that the CPU has spent unscheduled due "
352 // Number of Instructions simulated
353 // --------------------------------
354 // Should probably be in Base CPU but need templated
355 // MaxThreads so put in here instead
358 .name(name() + ".committedInsts")
359 .desc("Number of Instructions Simulated");
362 .name(name() + ".committedInsts_total")
363 .desc("Number of Instructions Simulated");
366 .name(name() + ".cpi")
367 .desc("CPI: Cycles Per Instruction")
369 cpi
= simTicks
/ committedInsts
;
372 .name(name() + ".cpi_total")
373 .desc("CPI: Total CPI of All Threads")
375 totalCpi
= simTicks
/ totalCommittedInsts
;
378 .name(name() + ".ipc")
379 .desc("IPC: Instructions Per Cycle")
381 ipc
= committedInsts
/ simTicks
;
384 .name(name() + ".ipc_total")
385 .desc("IPC: Total IPC of All Threads")
387 totalIpc
= totalCommittedInsts
/ simTicks
;
391 template <class Impl
>
393 FullO3CPU
<Impl
>::getPort(const std::string
&if_name
, int idx
)
395 if (if_name
== "dcache_port")
396 return iew
.getDcachePort();
397 else if (if_name
== "icache_port")
398 return fetch
.getIcachePort();
400 panic("No Such Port\n");
403 template <class Impl
>
405 FullO3CPU
<Impl
>::tick()
407 DPRINTF(O3CPU
, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
413 //Tick each of the stages
428 // Now advance the time buffers
429 timeBuffer
.advance();
431 fetchQueue
.advance();
432 decodeQueue
.advance();
433 renameQueue
.advance();
436 activityRec
.advance();
438 if (removeInstsThisCycle
) {
439 cleanUpRemovedInsts();
442 if (!tickEvent
.scheduled()) {
443 if (_status
== SwitchedOut
||
444 getState() == SimObject::Drained
) {
446 lastRunningCycle
= curTick
;
447 } else if (!activityRec
.active()) {
448 lastRunningCycle
= curTick
;
451 tickEvent
.schedule(curTick
+ cycles(1));
456 updateThreadPriority();
461 template <class Impl
>
463 FullO3CPU
<Impl
>::init()
465 if (!deferRegistration
) {
466 registerThreadContexts();
469 // Set inSyscall so that the CPU doesn't squash when initially
470 // setting up registers.
471 for (int i
= 0; i
< number_of_threads
; ++i
)
472 thread
[i
]->inSyscall
= true;
474 for (int tid
=0; tid
< number_of_threads
; tid
++) {
476 ThreadContext
*src_tc
= threadContexts
[tid
];
478 ThreadContext
*src_tc
= thread
[tid
]->getTC();
480 // Threads start in the Suspended State
481 if (src_tc
->status() != ThreadContext::Suspended
) {
486 TheISA::initCPU(src_tc
, src_tc
->readCpuId());
491 for (int i
= 0; i
< number_of_threads
; ++i
)
492 thread
[i
]->inSyscall
= false;
494 // Initialize stages.
500 commit
.setThreads(thread
);
503 template <class Impl
>
505 FullO3CPU
<Impl
>::activateThread(unsigned tid
)
507 list
<unsigned>::iterator isActive
= find(
508 activeThreads
.begin(), activeThreads
.end(), tid
);
510 if (isActive
== activeThreads
.end()) {
511 DPRINTF(O3CPU
, "[tid:%i]: Adding to active threads list\n",
514 activeThreads
.push_back(tid
);
518 template <class Impl
>
520 FullO3CPU
<Impl
>::deactivateThread(unsigned tid
)
522 //Remove From Active List, if Active
523 list
<unsigned>::iterator thread_it
=
524 find(activeThreads
.begin(), activeThreads
.end(), tid
);
526 if (thread_it
!= activeThreads
.end()) {
527 DPRINTF(O3CPU
,"[tid:%i]: Removing from active threads list\n",
529 activeThreads
.erase(thread_it
);
533 template <class Impl
>
535 FullO3CPU
<Impl
>::activateContext(int tid
, int delay
)
537 // Needs to set each stage to running as well.
539 DPRINTF(O3CPU
, "[tid:%i]: Scheduling thread context to activate "
540 "on cycle %d\n", tid
, curTick
+ cycles(delay
));
541 scheduleActivateThreadEvent(tid
, delay
);
546 if(lastActivatedCycle
< curTick
) {
547 scheduleTickEvent(delay
);
549 // Be sure to signal that there's some activity so the CPU doesn't
550 // deschedule itself.
551 activityRec
.activity();
552 fetch
.wakeFromQuiesce();
554 lastActivatedCycle
= curTick
;
560 template <class Impl
>
562 FullO3CPU
<Impl
>::deallocateContext(int tid
, int delay
)
564 // Schedule removal of thread data from CPU
566 DPRINTF(O3CPU
, "[tid:%i]: Scheduling thread context to deallocate "
567 "on cycle %d\n", tid
, curTick
+ cycles(delay
));
568 scheduleDeallocateContextEvent(tid
, delay
);
570 deactivateThread(tid
);
575 template <class Impl
>
577 FullO3CPU
<Impl
>::suspendContext(int tid
)
579 DPRINTF(O3CPU
,"[tid: %i]: Suspending Thread Context.\n", tid
);
580 deactivateThread(tid
);
581 if (activeThreads
.size() == 0)
582 unscheduleTickEvent();
586 template <class Impl
>
588 FullO3CPU
<Impl
>::haltContext(int tid
)
590 //For now, this is the same as deallocate
591 DPRINTF(O3CPU
,"[tid:%i]: Halt Context called. Deallocating", tid
);
592 deallocateContext(tid
, 1);
595 template <class Impl
>
597 FullO3CPU
<Impl
>::insertThread(unsigned tid
)
599 DPRINTF(O3CPU
,"[tid:%i] Initializing thread into CPU");
600 // Will change now that the PC and thread state is internal to the CPU
601 // and not in the ThreadContext.
603 ThreadContext
*src_tc
= system
->threadContexts
[tid
];
605 ThreadContext
*src_tc
= tcBase(tid
);
608 //Bind Int Regs to Rename Map
609 for (int ireg
= 0; ireg
< TheISA::NumIntRegs
; ireg
++) {
610 PhysRegIndex phys_reg
= freeList
.getIntReg();
612 renameMap
[tid
].setEntry(ireg
,phys_reg
);
613 scoreboard
.setReg(phys_reg
);
616 //Bind Float Regs to Rename Map
617 for (int freg
= 0; freg
< TheISA::NumFloatRegs
; freg
++) {
618 PhysRegIndex phys_reg
= freeList
.getFloatReg();
620 renameMap
[tid
].setEntry(freg
,phys_reg
);
621 scoreboard
.setReg(phys_reg
);
624 //Copy Thread Data Into RegFile
625 //this->copyFromTC(tid);
628 setPC(src_tc
->readPC(), tid
);
629 setNextPC(src_tc
->readNextPC(), tid
);
630 #if THE_ISA != ALPHA_ISA
631 setNextNPC(src_tc
->readNextNPC(), tid
);
634 src_tc
->setStatus(ThreadContext::Active
);
636 activateContext(tid
,1);
638 //Reset ROB/IQ/LSQ Entries
639 commit
.rob
->resetEntries();
643 template <class Impl
>
645 FullO3CPU
<Impl
>::removeThread(unsigned tid
)
647 DPRINTF(O3CPU
,"[tid:%i] Removing thread context from CPU.\n", tid
);
649 // Copy Thread Data From RegFile
650 // If thread is suspended, it might be re-allocated
651 //this->copyToTC(tid);
653 // Unbind Int Regs from Rename Map
654 for (int ireg
= 0; ireg
< TheISA::NumIntRegs
; ireg
++) {
655 PhysRegIndex phys_reg
= renameMap
[tid
].lookup(ireg
);
657 scoreboard
.unsetReg(phys_reg
);
658 freeList
.addReg(phys_reg
);
661 // Unbind Float Regs from Rename Map
662 for (int freg
= 0; freg
< TheISA::NumFloatRegs
; freg
++) {
663 PhysRegIndex phys_reg
= renameMap
[tid
].lookup(freg
);
665 scoreboard
.unsetReg(phys_reg
);
666 freeList
.addReg(phys_reg
);
669 // Squash Throughout Pipeline
670 InstSeqNum squash_seq_num
= commit
.rob
->readHeadInst(tid
)->seqNum
;
671 fetch
.squash(0, squash_seq_num
, true, tid
);
673 rename
.squash(squash_seq_num
, tid
);
675 commit
.rob
->squash(squash_seq_num
, tid
);
677 assert(iew
.ldstQueue
.getCount(tid
) == 0);
679 // Reset ROB/IQ/LSQ Entries
680 if (activeThreads
.size() >= 1) {
681 commit
.rob
->resetEntries();
687 template <class Impl
>
689 FullO3CPU
<Impl
>::activateWhenReady(int tid
)
691 DPRINTF(O3CPU
,"[tid:%i]: Checking if resources are available for incoming"
692 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
697 if (freeList
.numFreeIntRegs() >= TheISA::NumIntRegs
) {
698 DPRINTF(O3CPU
,"[tid:%i] Suspending thread due to not enough "
699 "Phys. Int. Regs.\n",
702 } else if (freeList
.numFreeFloatRegs() >= TheISA::NumFloatRegs
) {
703 DPRINTF(O3CPU
,"[tid:%i] Suspending thread due to not enough "
704 "Phys. Float. Regs.\n",
707 } else if (commit
.rob
->numFreeEntries() >=
708 commit
.rob
->entryAmount(activeThreads
.size() + 1)) {
709 DPRINTF(O3CPU
,"[tid:%i] Suspending thread due to not enough "
713 } else if (iew
.instQueue
.numFreeEntries() >=
714 iew
.instQueue
.entryAmount(activeThreads
.size() + 1)) {
715 DPRINTF(O3CPU
,"[tid:%i] Suspending thread due to not enough "
719 } else if (iew
.ldstQueue
.numFreeEntries() >=
720 iew
.ldstQueue
.entryAmount(activeThreads
.size() + 1)) {
721 DPRINTF(O3CPU
,"[tid:%i] Suspending thread due to not enough "
730 contextSwitch
= false;
732 cpuWaitList
.remove(tid
);
737 contextSwitch
= true;
739 //@todo: dont always add to waitlist
741 cpuWaitList
.push_back(tid
);
745 template <class Impl
>
747 FullO3CPU
<Impl
>::serialize(std::ostream
&os
)
749 SimObject::State so_state
= SimObject::getState();
750 SERIALIZE_ENUM(so_state
);
751 BaseCPU::serialize(os
);
752 nameOut(os
, csprintf("%s.tickEvent", name()));
753 tickEvent
.serialize(os
);
755 // Use SimpleThread's ability to checkpoint to make it easier to
756 // write out the registers. Also make this static so it doesn't
757 // get instantiated multiple times (causes a panic in statistics).
758 static SimpleThread temp
;
760 for (int i
= 0; i
< thread
.size(); i
++) {
761 nameOut(os
, csprintf("%s.xc.%i", name(), i
));
762 temp
.copyTC(thread
[i
]->getTC());
767 template <class Impl
>
769 FullO3CPU
<Impl
>::unserialize(Checkpoint
*cp
, const std::string
§ion
)
771 SimObject::State so_state
;
772 UNSERIALIZE_ENUM(so_state
);
773 BaseCPU::unserialize(cp
, section
);
774 tickEvent
.unserialize(cp
, csprintf("%s.tickEvent", section
));
776 // Use SimpleThread's ability to checkpoint to make it easier to
777 // read in the registers. Also make this static so it doesn't
778 // get instantiated multiple times (causes a panic in statistics).
779 static SimpleThread temp
;
781 for (int i
= 0; i
< thread
.size(); i
++) {
782 temp
.copyTC(thread
[i
]->getTC());
783 temp
.unserialize(cp
, csprintf("%s.xc.%i", section
, i
));
784 thread
[i
]->getTC()->copyArchRegs(temp
.getTC());
788 template <class Impl
>
790 FullO3CPU
<Impl
>::drain(Event
*drain_event
)
799 // Wake the CPU and record activity so everything can drain out if
800 // the CPU was not able to immediately drain.
801 if (getState() != SimObject::Drained
) {
802 // A bit of a hack...set the drainEvent after all the drain()
803 // calls have been made, that way if all of the stages drain
804 // immediately, the signalDrained() function knows not to call
805 // process on the drain event.
806 drainEvent
= drain_event
;
809 activityRec
.activity();
817 template <class Impl
>
819 FullO3CPU
<Impl
>::resume()
821 assert(system
->getMemoryMode() == System::Timing
);
828 changeState(SimObject::Running
);
830 if (_status
== SwitchedOut
|| _status
== Idle
)
833 if (!tickEvent
.scheduled())
834 tickEvent
.schedule(curTick
);
838 template <class Impl
>
840 FullO3CPU
<Impl
>::signalDrained()
842 if (++drainCount
== NumStages
) {
843 if (tickEvent
.scheduled())
846 changeState(SimObject::Drained
);
849 drainEvent
->process();
853 assert(drainCount
<= 5);
856 template <class Impl
>
858 FullO3CPU
<Impl
>::switchOut()
864 while (!removeList
.empty()) {
868 _status
= SwitchedOut
;
871 checker
->switchOut();
875 template <class Impl
>
877 FullO3CPU
<Impl
>::takeOverFrom(BaseCPU
*oldCPU
)
879 // Flush out any old data from the time buffers.
880 for (int i
= 0; i
< timeBuffer
.getSize(); ++i
) {
881 timeBuffer
.advance();
882 fetchQueue
.advance();
883 decodeQueue
.advance();
884 renameQueue
.advance();
890 BaseCPU::takeOverFrom(oldCPU
);
892 fetch
.takeOverFrom();
893 decode
.takeOverFrom();
894 rename
.takeOverFrom();
896 commit
.takeOverFrom();
898 assert(!tickEvent
.scheduled());
900 // @todo: Figure out how to properly select the tid to put onto
901 // the active threads list.
904 list
<unsigned>::iterator isActive
= find(
905 activeThreads
.begin(), activeThreads
.end(), tid
);
907 if (isActive
== activeThreads
.end()) {
908 //May Need to Re-code this if the delay variable is the delay
909 //needed for thread to activate
910 DPRINTF(O3CPU
, "Adding Thread %i to active threads list\n",
913 activeThreads
.push_back(tid
);
916 // Set all statuses to active, schedule the CPU's tick event.
917 // @todo: Fix up statuses so this is handled properly
918 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
919 ThreadContext
*tc
= threadContexts
[i
];
920 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
922 tickEvent
.schedule(curTick
);
925 if (!tickEvent
.scheduled())
926 tickEvent
.schedule(curTick
);
929 template <class Impl
>
931 FullO3CPU
<Impl
>::readIntReg(int reg_idx
)
933 return regFile
.readIntReg(reg_idx
);
936 template <class Impl
>
938 FullO3CPU
<Impl
>::readFloatReg(int reg_idx
, int width
)
940 return regFile
.readFloatReg(reg_idx
, width
);
943 template <class Impl
>
945 FullO3CPU
<Impl
>::readFloatReg(int reg_idx
)
947 return regFile
.readFloatReg(reg_idx
);
950 template <class Impl
>
952 FullO3CPU
<Impl
>::readFloatRegBits(int reg_idx
, int width
)
954 return regFile
.readFloatRegBits(reg_idx
, width
);
957 template <class Impl
>
959 FullO3CPU
<Impl
>::readFloatRegBits(int reg_idx
)
961 return regFile
.readFloatRegBits(reg_idx
);
964 template <class Impl
>
966 FullO3CPU
<Impl
>::setIntReg(int reg_idx
, uint64_t val
)
968 regFile
.setIntReg(reg_idx
, val
);
971 template <class Impl
>
973 FullO3CPU
<Impl
>::setFloatReg(int reg_idx
, FloatReg val
, int width
)
975 regFile
.setFloatReg(reg_idx
, val
, width
);
978 template <class Impl
>
980 FullO3CPU
<Impl
>::setFloatReg(int reg_idx
, FloatReg val
)
982 regFile
.setFloatReg(reg_idx
, val
);
985 template <class Impl
>
987 FullO3CPU
<Impl
>::setFloatRegBits(int reg_idx
, FloatRegBits val
, int width
)
989 regFile
.setFloatRegBits(reg_idx
, val
, width
);
992 template <class Impl
>
994 FullO3CPU
<Impl
>::setFloatRegBits(int reg_idx
, FloatRegBits val
)
996 regFile
.setFloatRegBits(reg_idx
, val
);
999 template <class Impl
>
1001 FullO3CPU
<Impl
>::readArchIntReg(int reg_idx
, unsigned tid
)
1003 PhysRegIndex phys_reg
= commitRenameMap
[tid
].lookup(reg_idx
);
1005 return regFile
.readIntReg(phys_reg
);
1008 template <class Impl
>
1010 FullO3CPU
<Impl
>::readArchFloatRegSingle(int reg_idx
, unsigned tid
)
1012 int idx
= reg_idx
+ TheISA::FP_Base_DepTag
;
1013 PhysRegIndex phys_reg
= commitRenameMap
[tid
].lookup(idx
);
1015 return regFile
.readFloatReg(phys_reg
);
1018 template <class Impl
>
1020 FullO3CPU
<Impl
>::readArchFloatRegDouble(int reg_idx
, unsigned tid
)
1022 int idx
= reg_idx
+ TheISA::FP_Base_DepTag
;
1023 PhysRegIndex phys_reg
= commitRenameMap
[tid
].lookup(idx
);
1025 return regFile
.readFloatReg(phys_reg
, 64);
1028 template <class Impl
>
1030 FullO3CPU
<Impl
>::readArchFloatRegInt(int reg_idx
, unsigned tid
)
1032 int idx
= reg_idx
+ TheISA::FP_Base_DepTag
;
1033 PhysRegIndex phys_reg
= commitRenameMap
[tid
].lookup(idx
);
1035 return regFile
.readFloatRegBits(phys_reg
);
1038 template <class Impl
>
1040 FullO3CPU
<Impl
>::setArchIntReg(int reg_idx
, uint64_t val
, unsigned tid
)
1042 PhysRegIndex phys_reg
= commitRenameMap
[tid
].lookup(reg_idx
);
1044 regFile
.setIntReg(phys_reg
, val
);
1047 template <class Impl
>
1049 FullO3CPU
<Impl
>::setArchFloatRegSingle(int reg_idx
, float val
, unsigned tid
)
1051 int idx
= reg_idx
+ TheISA::FP_Base_DepTag
;
1052 PhysRegIndex phys_reg
= commitRenameMap
[tid
].lookup(idx
);
1054 regFile
.setFloatReg(phys_reg
, val
);
1057 template <class Impl
>
1059 FullO3CPU
<Impl
>::setArchFloatRegDouble(int reg_idx
, double val
, unsigned tid
)
1061 int idx
= reg_idx
+ TheISA::FP_Base_DepTag
;
1062 PhysRegIndex phys_reg
= commitRenameMap
[tid
].lookup(idx
);
1064 regFile
.setFloatReg(phys_reg
, val
, 64);
1067 template <class Impl
>
1069 FullO3CPU
<Impl
>::setArchFloatRegInt(int reg_idx
, uint64_t val
, unsigned tid
)
1071 int idx
= reg_idx
+ TheISA::FP_Base_DepTag
;
1072 PhysRegIndex phys_reg
= commitRenameMap
[tid
].lookup(idx
);
1074 regFile
.setFloatRegBits(phys_reg
, val
);
1077 template <class Impl
>
1079 FullO3CPU
<Impl
>::readPC(unsigned tid
)
1081 return commit
.readPC(tid
);
1084 template <class Impl
>
1086 FullO3CPU
<Impl
>::setPC(Addr new_PC
,unsigned tid
)
1088 commit
.setPC(new_PC
, tid
);
1091 template <class Impl
>
1093 FullO3CPU
<Impl
>::readNextPC(unsigned tid
)
1095 return commit
.readNextPC(tid
);
1098 template <class Impl
>
1100 FullO3CPU
<Impl
>::setNextPC(uint64_t val
,unsigned tid
)
1102 commit
.setNextPC(val
, tid
);
1105 template <class Impl
>
1107 FullO3CPU
<Impl
>::readNextNPC(unsigned tid
)
1109 return commit
.readNextNPC(tid
);
1112 template <class Impl
>
1114 FullO3CPU
<Impl
>::setNextNPC(uint64_t val
,unsigned tid
)
1116 commit
.setNextNPC(val
, tid
);
1119 template <class Impl
>
1120 typename FullO3CPU
<Impl
>::ListIt
1121 FullO3CPU
<Impl
>::addInst(DynInstPtr
&inst
)
1123 instList
.push_back(inst
);
1125 return --(instList
.end());
1128 template <class Impl
>
1130 FullO3CPU
<Impl
>::instDone(unsigned tid
)
1132 // Keep an instruction count.
1133 thread
[tid
]->numInst
++;
1134 thread
[tid
]->numInsts
++;
1135 committedInsts
[tid
]++;
1136 totalCommittedInsts
++;
1138 // Check for instruction-count-based events.
1139 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numInst
);
1142 template <class Impl
>
1144 FullO3CPU
<Impl
>::addToRemoveList(DynInstPtr
&inst
)
1146 removeInstsThisCycle
= true;
1148 removeList
.push(inst
->getInstListIt());
1151 template <class Impl
>
1153 FullO3CPU
<Impl
>::removeFrontInst(DynInstPtr
&inst
)
1155 DPRINTF(O3CPU
, "Removing committed instruction [tid:%i] PC %#x "
1157 inst
->threadNumber
, inst
->readPC(), inst
->seqNum
);
1159 removeInstsThisCycle
= true;
1161 // Remove the front instruction.
1162 removeList
.push(inst
->getInstListIt());
1165 template <class Impl
>
1167 FullO3CPU
<Impl
>::removeInstsNotInROB(unsigned tid
,
1168 bool squash_delay_slot
,
1169 const InstSeqNum
&delay_slot_seq_num
)
1171 DPRINTF(O3CPU
, "Thread %i: Deleting instructions from instruction"
1176 bool rob_empty
= false;
1178 if (instList
.empty()) {
1180 } else if (rob
.isEmpty(/*tid*/)) {
1181 DPRINTF(O3CPU
, "ROB is empty, squashing all insts.\n");
1182 end_it
= instList
.begin();
1185 end_it
= (rob
.readTailInst(tid
))->getInstListIt();
1186 DPRINTF(O3CPU
, "ROB is not empty, squashing insts not in ROB.\n");
1189 removeInstsThisCycle
= true;
1191 ListIt inst_it
= instList
.end();
1195 // Walk through the instruction list, removing any instructions
1196 // that were inserted after the given instruction iterator, end_it.
1197 while (inst_it
!= end_it
) {
1198 assert(!instList
.empty());
1200 #if THE_ISA != ALPHA_ISA
1201 if(!squash_delay_slot
&&
1202 delay_slot_seq_num
>= (*inst_it
)->seqNum
) {
1206 squashInstIt(inst_it
, tid
);
1211 // If the ROB was empty, then we actually need to remove the first
1212 // instruction as well.
1214 squashInstIt(inst_it
, tid
);
1218 template <class Impl
>
1220 FullO3CPU
<Impl
>::removeInstsUntil(const InstSeqNum
&seq_num
,
1223 assert(!instList
.empty());
1225 removeInstsThisCycle
= true;
1227 ListIt inst_iter
= instList
.end();
1231 DPRINTF(O3CPU
, "Deleting instructions from instruction "
1232 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1233 tid
, seq_num
, (*inst_iter
)->seqNum
);
1235 while ((*inst_iter
)->seqNum
> seq_num
) {
1237 bool break_loop
= (inst_iter
== instList
.begin());
1239 squashInstIt(inst_iter
, tid
);
1248 template <class Impl
>
1250 FullO3CPU
<Impl
>::squashInstIt(const ListIt
&instIt
, const unsigned &tid
)
1252 if ((*instIt
)->threadNumber
== tid
) {
1253 DPRINTF(O3CPU
, "Squashing instruction, "
1254 "[tid:%i] [sn:%lli] PC %#x\n",
1255 (*instIt
)->threadNumber
,
1257 (*instIt
)->readPC());
1259 // Mark it as squashed.
1260 (*instIt
)->setSquashed();
1262 // @todo: Formulate a consistent method for deleting
1263 // instructions from the instruction list
1264 // Remove the instruction from the list.
1265 removeList
.push(instIt
);
1269 template <class Impl
>
1271 FullO3CPU
<Impl
>::cleanUpRemovedInsts()
1273 while (!removeList
.empty()) {
1274 DPRINTF(O3CPU
, "Removing instruction, "
1275 "[tid:%i] [sn:%lli] PC %#x\n",
1276 (*removeList
.front())->threadNumber
,
1277 (*removeList
.front())->seqNum
,
1278 (*removeList
.front())->readPC());
1280 instList
.erase(removeList
.front());
1285 removeInstsThisCycle
= false;
1288 template <class Impl>
1290 FullO3CPU<Impl>::removeAllInsts()
1295 template <class Impl
>
1297 FullO3CPU
<Impl
>::dumpInsts()
1301 ListIt inst_list_it
= instList
.begin();
1303 cprintf("Dumping Instruction List\n");
1305 while (inst_list_it
!= instList
.end()) {
1306 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1308 num
, (*inst_list_it
)->readPC(), (*inst_list_it
)->threadNumber
,
1309 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1310 (*inst_list_it
)->isSquashed());
1316 template <class Impl>
1318 FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1320 iew.wakeDependents(inst);
1323 template <class Impl
>
1325 FullO3CPU
<Impl
>::wakeCPU()
1327 if (activityRec
.active() || tickEvent
.scheduled()) {
1328 DPRINTF(Activity
, "CPU already running.\n");
1332 DPRINTF(Activity
, "Waking up CPU\n");
1334 idleCycles
+= (curTick
- 1) - lastRunningCycle
;
1336 tickEvent
.schedule(curTick
);
1339 template <class Impl
>
1341 FullO3CPU
<Impl
>::getFreeTid()
1343 for (int i
=0; i
< numThreads
; i
++) {
1353 template <class Impl
>
1355 FullO3CPU
<Impl
>::doContextSwitch()
1357 if (contextSwitch
) {
1359 //ADD CODE TO DEACTIVE THREAD HERE (???)
1361 for (int tid
=0; tid
< cpuWaitList
.size(); tid
++) {
1362 activateWhenReady(tid
);
1365 if (cpuWaitList
.size() == 0)
1366 contextSwitch
= true;
1370 template <class Impl
>
1372 FullO3CPU
<Impl
>::updateThreadPriority()
1374 if (activeThreads
.size() > 1)
1376 //DEFAULT TO ROUND ROBIN SCHEME
1377 //e.g. Move highest priority to end of thread list
1378 list
<unsigned>::iterator list_begin
= activeThreads
.begin();
1379 list
<unsigned>::iterator list_end
= activeThreads
.end();
1381 unsigned high_thread
= *list_begin
;
1383 activeThreads
.erase(list_begin
);
1385 activeThreads
.push_back(high_thread
);
1389 // Forward declaration of FullO3CPU.
1390 template class FullO3CPU
<O3CPUImpl
>;