src/cpu/o3/cpu.hh

   1 /*
   2  * Copyright (c) 2011-2013, 2016-2019 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2004-2005 The Regents of The University of Michigan
  16  * Copyright (c) 2011 Regents of the University of California
  17  * All rights reserved.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are
  21  * met: redistributions of source code must retain the above copyright
  22  * notice, this list of conditions and the following disclaimer;
  23  * redistributions in binary form must reproduce the above copyright
  24  * notice, this list of conditions and the following disclaimer in the
  25  * documentation and/or other materials provided with the distribution;
  26  * neither the name of the copyright holders nor the names of its
  27  * contributors may be used to endorse or promote products derived from
  28  * this software without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  31  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  32  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  33  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  34  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  35  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  36  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  37  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  38  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  39  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  40  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  41  *
  42  * Authors: Kevin Lim
  43  *          Korey Sewell
  44  *          Rick Strong
  45  */
  46
  47 #ifndef __CPU_O3_CPU_HH__
  48 #define __CPU_O3_CPU_HH__
  49
  50 #include <iostream>
  51 #include <list>
  52 #include <queue>
  53 #include <set>
  54 #include <vector>
  55
  56 #include "arch/generic/types.hh"
  57 #include "arch/types.hh"
  58 #include "base/statistics.hh"
  59 #include "config/the_isa.hh"
  60 #include "cpu/o3/comm.hh"
  61 #include "cpu/o3/cpu_policy.hh"
  62 #include "cpu/o3/scoreboard.hh"
  63 #include "cpu/o3/thread_state.hh"
  64 #include "cpu/activity.hh"
  65 #include "cpu/base.hh"
  66 #include "cpu/simple_thread.hh"
  67 #include "cpu/timebuf.hh"
  68 //#include "cpu/o3/thread_context.hh"
  69 #include "params/DerivO3CPU.hh"
  70 #include "sim/process.hh"
  71
  72 template <class>
  73 class Checker;
  74 class ThreadContext;
  75 template <class>
  76 class O3ThreadContext;
  77
  78 class Checkpoint;
  79 class MemObject;
  80 class Process;
  81
  82 struct BaseCPUParams;
  83
  84 class BaseO3CPU : public BaseCPU
  85 {
  86     //Stuff that's pretty ISA independent will go here.
  87   public:
  88     BaseO3CPU(BaseCPUParams *params);
  89
  90     void regStats();
  91 };
  92
  93 /**
  94  * FullO3CPU class, has each of the stages (fetch through commit)
  95  * within it, as well as all of the time buffers between stages.  The
  96  * tick() function for the CPU is defined here.
  97  */
  98 template <class Impl>
  99 class FullO3CPU : public BaseO3CPU
 100 {
 101   public:
 102     // Typedefs from the Impl here.
 103     typedef typename Impl::CPUPol CPUPolicy;
 104     typedef typename Impl::DynInstPtr DynInstPtr;
 105     typedef typename Impl::O3CPU O3CPU;
 106
 107     using VecElem =  TheISA::VecElem;
 108     using VecRegContainer =  TheISA::VecRegContainer;
 109
 110     using VecPredRegContainer = TheISA::VecPredRegContainer;
 111
 112     typedef O3ThreadState<Impl> ImplState;
 113     typedef O3ThreadState<Impl> Thread;
 114
 115     typedef typename std::list<DynInstPtr>::iterator ListIt;
 116
 117     friend class O3ThreadContext<Impl>;
 118
 119   public:
 120     enum Status {
 121         Running,
 122         Idle,
 123         Halted,
 124         Blocked,
 125         SwitchedOut
 126     };
 127
 128     BaseTLB *itb;
 129     BaseTLB *dtb;
 130     using LSQRequest = typename LSQ<Impl>::LSQRequest;
 131
 132     /** Overall CPU status. */
 133     Status _status;
 134
 135   private:
 136
 137     /**
 138      * IcachePort class for instruction fetch.
 139      */
 140     class IcachePort : public MasterPort
 141     {
 142       protected:
 143         /** Pointer to fetch. */
 144         DefaultFetch<Impl> *fetch;
 145
 146       public:
 147         /** Default constructor. */
 148         IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
 149             : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
 150         { }
 151
 152       protected:
 153
 154         /** Timing version of receive.  Handles setting fetch to the
 155          * proper status to start fetching. */
 156         virtual bool recvTimingResp(PacketPtr pkt);
 157
 158         /** Handles doing a retry of a failed fetch. */
 159         virtual void recvReqRetry();
 160     };
 161
 162     /**
 163      * DcachePort class for the load/store queue.
 164      */
 165     class DcachePort : public MasterPort
 166     {
 167       protected:
 168
 169         /** Pointer to LSQ. */
 170         LSQ<Impl> *lsq;
 171         FullO3CPU<Impl> *cpu;
 172
 173       public:
 174         /** Default constructor. */
 175         DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
 176             : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq),
 177               cpu(_cpu)
 178         { }
 179
 180       protected:
 181
 182         /** Timing version of receive.  Handles writing back and
 183          * completing the load or store that has returned from
 184          * memory. */
 185         virtual bool recvTimingResp(PacketPtr pkt);
 186         virtual void recvTimingSnoopReq(PacketPtr pkt);
 187
 188         virtual void recvFunctionalSnoop(PacketPtr pkt)
 189         {
 190             // @todo: Is there a need for potential invalidation here?
 191         }
 192
 193         /** Handles doing a retry of the previous send. */
 194         virtual void recvReqRetry();
 195
 196         /**
 197          * As this CPU requires snooping to maintain the load store queue
 198          * change the behaviour from the base CPU port.
 199          *
 200          * @return true since we have to snoop
 201          */
 202         virtual bool isSnooping() const { return true; }
 203     };
 204
 205     /** The tick event used for scheduling CPU ticks. */
 206     EventFunctionWrapper tickEvent;
 207
 208     /** The exit event used for terminating all ready-to-exit threads */
 209     EventFunctionWrapper threadExitEvent;
 210
 211     /** Schedule tick event, regardless of its current state. */
 212     void scheduleTickEvent(Cycles delay)
 213     {
 214         if (tickEvent.squashed())
 215             reschedule(tickEvent, clockEdge(delay));
 216         else if (!tickEvent.scheduled())
 217             schedule(tickEvent, clockEdge(delay));
 218     }
 219
 220     /** Unschedule tick event, regardless of its current state. */
 221     void unscheduleTickEvent()
 222     {
 223         if (tickEvent.scheduled())
 224             tickEvent.squash();
 225     }
 226
 227     /**
 228      * Check if the pipeline has drained and signal drain done.
 229      *
 230      * This method checks if a drain has been requested and if the CPU
 231      * has drained successfully (i.e., there are no instructions in
 232      * the pipeline). If the CPU has drained, it deschedules the tick
 233      * event and signals the drain manager.
 234      *
 235      * @return False if a drain hasn't been requested or the CPU
 236      * hasn't drained, true otherwise.
 237      */
 238     bool tryDrain();
 239
 240     /**
 241      * Perform sanity checks after a drain.
 242      *
 243      * This method is called from drain() when it has determined that
 244      * the CPU is fully drained when gem5 is compiled with the NDEBUG
 245      * macro undefined. The intention of this method is to do more
 246      * extensive tests than the isDrained() method to weed out any
 247      * draining bugs.
 248      */
 249     void drainSanityCheck() const;
 250
 251     /** Check if a system is in a drained state. */
 252     bool isDrained() const;
 253
 254   public:
 255     /** Constructs a CPU with the given parameters. */
 256     FullO3CPU(DerivO3CPUParams *params);
 257     /** Destructor. */
 258     ~FullO3CPU();
 259
 260     /** Registers statistics. */
 261     void regStats() override;
 262
 263     ProbePointArg<PacketPtr> *ppInstAccessComplete;
 264     ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
 265
 266     /** Register probe points. */
 267     void regProbePoints() override;
 268
 269     void demapPage(Addr vaddr, uint64_t asn)
 270     {
 271         this->itb->demapPage(vaddr, asn);
 272         this->dtb->demapPage(vaddr, asn);
 273     }
 274
 275     void demapInstPage(Addr vaddr, uint64_t asn)
 276     {
 277         this->itb->demapPage(vaddr, asn);
 278     }
 279
 280     void demapDataPage(Addr vaddr, uint64_t asn)
 281     {
 282         this->dtb->demapPage(vaddr, asn);
 283     }
 284
 285     /** Ticks CPU, calling tick() on each stage, and checking the overall
 286      *  activity to see if the CPU should deschedule itself.
 287      */
 288     void tick();
 289
 290     /** Initialize the CPU */
 291     void init() override;
 292
 293     void startup() override;
 294
 295     /** Returns the Number of Active Threads in the CPU */
 296     int numActiveThreads()
 297     { return activeThreads.size(); }
 298
 299     /** Add Thread to Active Threads List */
 300     void activateThread(ThreadID tid);
 301
 302     /** Remove Thread from Active Threads List */
 303     void deactivateThread(ThreadID tid);
 304
 305     /** Setup CPU to insert a thread's context */
 306     void insertThread(ThreadID tid);
 307
 308     /** Remove all of a thread's context from CPU */
 309     void removeThread(ThreadID tid);
 310
 311     /** Count the Total Instructions Committed in the CPU. */
 312     Counter totalInsts() const override;
 313
 314     /** Count the Total Ops (including micro ops) committed in the CPU. */
 315     Counter totalOps() const override;
 316
 317     /** Add Thread to Active Threads List. */
 318     void activateContext(ThreadID tid) override;
 319
 320     /** Remove Thread from Active Threads List */
 321     void suspendContext(ThreadID tid) override;
 322
 323     /** Remove Thread from Active Threads List &&
 324      *  Remove Thread Context from CPU.
 325      */
 326     void haltContext(ThreadID tid) override;
 327
 328     /** Update The Order In Which We Process Threads. */
 329     void updateThreadPriority();
 330
 331     /** Is the CPU draining? */
 332     bool isDraining() const { return drainState() == DrainState::Draining; }
 333
 334     void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
 335     void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
 336
 337     /** Insert tid to the list of threads trying to exit */
 338     void addThreadToExitingList(ThreadID tid);
 339
 340     /** Is the thread trying to exit? */
 341     bool isThreadExiting(ThreadID tid) const;
 342
 343     /**
 344      *  If a thread is trying to exit and its corresponding trap event
 345      *  has been completed, schedule an event to terminate the thread.
 346      */
 347     void scheduleThreadExitEvent(ThreadID tid);
 348
 349     /** Terminate all threads that are ready to exit */
 350     void exitThreads();
 351
 352   public:
 353     /** Executes a syscall.
 354      * @todo: Determine if this needs to be virtual.
 355      */
 356     void syscall(int64_t callnum, ThreadID tid, Fault *fault);
 357
 358     /** Starts draining the CPU's pipeline of all instructions in
 359      * order to stop all memory accesses. */
 360     DrainState drain() override;
 361
 362     /** Resumes execution after a drain. */
 363     void drainResume() override;
 364
 365     /**
 366      * Commit has reached a safe point to drain a thread.
 367      *
 368      * Commit calls this method to inform the pipeline that it has
 369      * reached a point where it is not executed microcode and is about
 370      * to squash uncommitted instructions to fully drain the pipeline.
 371      */
 372     void commitDrained(ThreadID tid);
 373
 374     /** Switches out this CPU. */
 375     void switchOut() override;
 376
 377     /** Takes over from another CPU. */
 378     void takeOverFrom(BaseCPU *oldCPU) override;
 379
 380     void verifyMemoryMode() const override;
 381
 382     /** Get the current instruction sequence number, and increment it. */
 383     InstSeqNum getAndIncrementInstSeq()
 384     { return globalSeqNum++; }
 385
 386     /** Traps to handle given fault. */
 387     void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
 388
 389     /** HW return from error interrupt. */
 390     Fault hwrei(ThreadID tid);
 391
 392     bool simPalCheck(int palFunc, ThreadID tid);
 393
 394     /** Check if a change in renaming is needed for vector registers.
 395      * The vecMode variable is updated and propagated to rename maps.
 396      *
 397      * @param tid ThreadID
 398      * @param freelist list of free registers
 399      */
 400     void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist);
 401
 402     /** Returns the Fault for any valid interrupt. */
 403     Fault getInterrupts();
 404
 405     /** Processes any an interrupt fault. */
 406     void processInterrupts(const Fault &interrupt);
 407
 408     /** Halts the CPU. */
 409     void halt() { panic("Halt not implemented!\n"); }
 410
 411     /** Register accessors.  Index refers to the physical register index. */
 412
 413     /** Reads a miscellaneous register. */
 414     RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
 415
 416     /** Reads a misc. register, including any side effects the read
 417      * might have as defined by the architecture.
 418      */
 419     RegVal readMiscReg(int misc_reg, ThreadID tid);
 420
 421     /** Sets a miscellaneous register. */
 422     void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
 423
 424     /** Sets a misc. register, including any side effects the write
 425      * might have as defined by the architecture.
 426      */
 427     void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
 428
 429     RegVal readIntReg(PhysRegIdPtr phys_reg);
 430
 431     RegVal readFloatReg(PhysRegIdPtr phys_reg);
 432
 433     const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
 434
 435     /**
 436      * Read physical vector register for modification.
 437      */
 438     VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
 439
 440     /** Returns current vector renaming mode */
 441     Enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
 442
 443     /** Sets the current vector renaming mode */
 444     void vecRenameMode(Enums::VecRegRenameMode vec_mode)
 445     { vecMode = vec_mode; }
 446
 447     /**
 448      * Read physical vector register lane
 449      */
 450     template<typename VecElem, int LaneIdx>
 451     VecLaneT<VecElem, true>
 452     readVecLane(PhysRegIdPtr phys_reg) const
 453     {
 454         vecRegfileReads++;
 455         return regFile.readVecLane<VecElem, LaneIdx>(phys_reg);
 456     }
 457
 458     /**
 459      * Read physical vector register lane
 460      */
 461     template<typename VecElem>
 462     VecLaneT<VecElem, true>
 463     readVecLane(PhysRegIdPtr phys_reg) const
 464     {
 465         vecRegfileReads++;
 466         return regFile.readVecLane<VecElem>(phys_reg);
 467     }
 468
 469     /** Write a lane of the destination vector register. */
 470     template<typename LD>
 471     void
 472     setVecLane(PhysRegIdPtr phys_reg, const LD& val)
 473     {
 474         vecRegfileWrites++;
 475         return regFile.setVecLane(phys_reg, val);
 476     }
 477
 478     const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
 479
 480     const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const;
 481
 482     VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
 483
 484     RegVal readCCReg(PhysRegIdPtr phys_reg);
 485
 486     void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
 487
 488     void setFloatReg(PhysRegIdPtr phys_reg, RegVal val);
 489
 490     void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
 491
 492     void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);
 493
 494     void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val);
 495
 496     void setCCReg(PhysRegIdPtr phys_reg, RegVal val);
 497
 498     RegVal readArchIntReg(int reg_idx, ThreadID tid);
 499
 500     RegVal readArchFloatReg(int reg_idx, ThreadID tid);
 501
 502     const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
 503     /** Read architectural vector register for modification. */
 504     VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
 505
 506     /** Read architectural vector register lane. */
 507     template<typename VecElem>
 508     VecLaneT<VecElem, true>
 509     readArchVecLane(int reg_idx, int lId, ThreadID tid) const
 510     {
 511         PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
 512                     RegId(VecRegClass, reg_idx));
 513         return readVecLane<VecElem>(phys_reg);
 514     }
 515
 516
 517     /** Write a lane of the destination vector register. */
 518     template<typename LD>
 519     void
 520     setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val)
 521     {
 522         PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
 523                     RegId(VecRegClass, reg_idx));
 524         setVecLane(phys_reg, val);
 525     }
 526
 527     const VecElem& readArchVecElem(const RegIndex& reg_idx,
 528                                    const ElemIndex& ldx, ThreadID tid) const;
 529
 530     const VecPredRegContainer& readArchVecPredReg(int reg_idx,
 531                                                   ThreadID tid) const;
 532
 533     VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid);
 534
 535     RegVal readArchCCReg(int reg_idx, ThreadID tid);
 536
 537     /** Architectural register accessors.  Looks up in the commit
 538      * rename table to obtain the true physical index of the
 539      * architected register first, then accesses that physical
 540      * register.
 541      */
 542     void setArchIntReg(int reg_idx, RegVal val, ThreadID tid);
 543
 544     void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid);
 545
 546     void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
 547                            ThreadID tid);
 548
 549     void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
 550
 551     void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
 552                         const VecElem& val, ThreadID tid);
 553
 554     void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);
 555
 556     /** Sets the commit PC state of a specific thread. */
 557     void pcState(const TheISA::PCState &newPCState, ThreadID tid);
 558
 559     /** Reads the commit PC state of a specific thread. */
 560     TheISA::PCState pcState(ThreadID tid);
 561
 562     /** Reads the commit PC of a specific thread. */
 563     Addr instAddr(ThreadID tid);
 564
 565     /** Reads the commit micro PC of a specific thread. */
 566     MicroPC microPC(ThreadID tid);
 567
 568     /** Reads the next PC of a specific thread. */
 569     Addr nextInstAddr(ThreadID tid);
 570
 571     /** Initiates a squash of all in-flight instructions for a given
 572      * thread.  The source of the squash is an external update of
 573      * state through the TC.
 574      */
 575     void squashFromTC(ThreadID tid);
 576
 577     /** Function to add instruction onto the head of the list of the
 578      *  instructions.  Used when new instructions are fetched.
 579      */
 580     ListIt addInst(const DynInstPtr &inst);
 581
 582     /** Function to tell the CPU that an instruction has completed. */
 583     void instDone(ThreadID tid, const DynInstPtr &inst);
 584
 585     /** Remove an instruction from the front end of the list.  There's
 586      *  no restriction on location of the instruction.
 587      */
 588     void removeFrontInst(const DynInstPtr &inst);
 589
 590     /** Remove all instructions that are not currently in the ROB.
 591      *  There's also an option to not squash delay slot instructions.*/
 592     void removeInstsNotInROB(ThreadID tid);
 593
 594     /** Remove all instructions younger than the given sequence number. */
 595     void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
 596
 597     /** Removes the instruction pointed to by the iterator. */
 598     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 599
 600     /** Cleans up all instructions on the remove list. */
 601     void cleanUpRemovedInsts();
 602
 603     /** Debug function to print all instructions on the list. */
 604     void dumpInsts();
 605
 606   public:
 607 #ifndef NDEBUG
 608     /** Count of total number of dynamic instructions in flight. */
 609     int instcount;
 610 #endif
 611
 612     /** List of all the instructions in flight. */
 613     std::list<DynInstPtr> instList;
 614
 615     /** List of all the instructions that will be removed at the end of this
 616      *  cycle.
 617      */
 618     std::queue<ListIt> removeList;
 619
 620 #ifdef DEBUG
 621     /** Debug structure to keep track of the sequence numbers still in
 622      * flight.
 623      */
 624     std::set<InstSeqNum> snList;
 625 #endif
 626
 627     /** Records if instructions need to be removed this cycle due to
 628      *  being retired or squashed.
 629      */
 630     bool removeInstsThisCycle;
 631
 632   protected:
 633     /** The fetch stage. */
 634     typename CPUPolicy::Fetch fetch;
 635
 636     /** The decode stage. */
 637     typename CPUPolicy::Decode decode;
 638
 639     /** The dispatch stage. */
 640     typename CPUPolicy::Rename rename;
 641
 642     /** The issue/execute/writeback stages. */
 643     typename CPUPolicy::IEW iew;
 644
 645     /** The commit stage. */
 646     typename CPUPolicy::Commit commit;
 647
 648     /** The rename mode of the vector registers */
 649     Enums::VecRegRenameMode vecMode;
 650
 651     /** The register file. */
 652     PhysRegFile regFile;
 653
 654     /** The free list. */
 655     typename CPUPolicy::FreeList freeList;
 656
 657     /** The rename map. */
 658     typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
 659
 660     /** The commit rename map. */
 661     typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
 662
 663     /** The re-order buffer. */
 664     typename CPUPolicy::ROB rob;
 665
 666     /** Active Threads List */
 667     std::list<ThreadID> activeThreads;
 668
 669     /**
 670      *  This is a list of threads that are trying to exit. Each thread id
 671      *  is mapped to a boolean value denoting whether the thread is ready
 672      *  to exit.
 673      */
 674     std::unordered_map<ThreadID, bool> exitingThreads;
 675
 676     /** Integer Register Scoreboard */
 677     Scoreboard scoreboard;
 678
 679     std::vector<TheISA::ISA *> isa;
 680
 681     /** Instruction port. Note that it has to appear after the fetch stage. */
 682     IcachePort icachePort;
 683
 684     /** Data port. Note that it has to appear after the iew stages */
 685     DcachePort dcachePort;
 686
 687   public:
 688     /** Enum to give each stage a specific index, so when calling
 689      *  activateStage() or deactivateStage(), they can specify which stage
 690      *  is being activated/deactivated.
 691      */
 692     enum StageIdx {
 693         FetchIdx,
 694         DecodeIdx,
 695         RenameIdx,
 696         IEWIdx,
 697         CommitIdx,
 698         NumStages };
 699
 700     /** Typedefs from the Impl to get the structs that each of the
 701      *  time buffers should use.
 702      */
 703     typedef typename CPUPolicy::TimeStruct TimeStruct;
 704
 705     typedef typename CPUPolicy::FetchStruct FetchStruct;
 706
 707     typedef typename CPUPolicy::DecodeStruct DecodeStruct;
 708
 709     typedef typename CPUPolicy::RenameStruct RenameStruct;
 710
 711     typedef typename CPUPolicy::IEWStruct IEWStruct;
 712
 713     /** The main time buffer to do backwards communication. */
 714     TimeBuffer<TimeStruct> timeBuffer;
 715
 716     /** The fetch stage's instruction queue. */
 717     TimeBuffer<FetchStruct> fetchQueue;
 718
 719     /** The decode stage's instruction queue. */
 720     TimeBuffer<DecodeStruct> decodeQueue;
 721
 722     /** The rename stage's instruction queue. */
 723     TimeBuffer<RenameStruct> renameQueue;
 724
 725     /** The IEW stage's instruction queue. */
 726     TimeBuffer<IEWStruct> iewQueue;
 727
 728   private:
 729     /** The activity recorder; used to tell if the CPU has any
 730      * activity remaining or if it can go to idle and deschedule
 731      * itself.
 732      */
 733     ActivityRecorder activityRec;
 734
 735   public:
 736     /** Records that there was time buffer activity this cycle. */
 737     void activityThisCycle() { activityRec.activity(); }
 738
 739     /** Changes a stage's status to active within the activity recorder. */
 740     void activateStage(const StageIdx idx)
 741     { activityRec.activateStage(idx); }
 742
 743     /** Changes a stage's status to inactive within the activity recorder. */
 744     void deactivateStage(const StageIdx idx)
 745     { activityRec.deactivateStage(idx); }
 746
 747     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 748     void wakeCPU();
 749
 750     virtual void wakeup(ThreadID tid) override;
 751
 752     /** Gets a free thread id. Use if thread ids change across system. */
 753     ThreadID getFreeTid();
 754
 755   public:
 756     /** Returns a pointer to a thread context. */
 757     ThreadContext *
 758     tcBase(ThreadID tid)
 759     {
 760         return thread[tid]->getTC();
 761     }
 762
 763     /** The global sequence number counter. */
 764     InstSeqNum globalSeqNum;//[Impl::MaxThreads];
 765
 766     /** Pointer to the checker, which can dynamically verify
 767      * instruction results at run time.  This can be set to NULL if it
 768      * is not being used.
 769      */
 770     Checker<Impl> *checker;
 771
 772     /** Pointer to the system. */
 773     System *system;
 774
 775     /** Pointers to all of the threads in the CPU. */
 776     std::vector<Thread *> thread;
 777
 778     /** Threads Scheduled to Enter CPU */
 779     std::list<int> cpuWaitList;
 780
 781     /** The cycle that the CPU was last running, used for statistics. */
 782     Cycles lastRunningCycle;
 783
 784     /** The cycle that the CPU was last activated by a new thread*/
 785     Tick lastActivatedCycle;
 786
 787     /** Mapping for system thread id to cpu id */
 788     std::map<ThreadID, unsigned> threadMap;
 789
 790     /** Available thread ids in the cpu*/
 791     std::vector<ThreadID> tids;
 792
 793     /** CPU pushRequest function, forwards request to LSQ. */
 794     Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
 795                       unsigned int size, Addr addr, Request::Flags flags,
 796                       uint64_t *res, AtomicOpFunctor *amo_op = nullptr)
 797     {
 798         return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr,
 799                 flags, res, amo_op);
 800     }
 801
 802     /** CPU read function, forwards read to LSQ. */
 803     Fault read(LSQRequest* req, int load_idx)
 804     {
 805         return this->iew.ldstQueue.read(req, load_idx);
 806     }
 807
 808     /** CPU write function, forwards write to LSQ. */
 809     Fault write(LSQRequest* req, uint8_t *data, int store_idx)
 810     {
 811         return this->iew.ldstQueue.write(req, data, store_idx);
 812     }
 813
 814     /** Used by the fetch unit to get a hold of the instruction port. */
 815     MasterPort &getInstPort() override { return icachePort; }
 816
 817     /** Get the dcache port (used to find block size for translations). */
 818     MasterPort &getDataPort() override { return dcachePort; }
 819
 820     /** Stat for total number of times the CPU is descheduled. */
 821     Stats::Scalar timesIdled;
 822     /** Stat for total number of cycles the CPU spends descheduled. */
 823     Stats::Scalar idleCycles;
 824     /** Stat for total number of cycles the CPU spends descheduled due to a
 825      * quiesce operation or waiting for an interrupt. */
 826     Stats::Scalar quiesceCycles;
 827     /** Stat for the number of committed instructions per thread. */
 828     Stats::Vector committedInsts;
 829     /** Stat for the number of committed ops (including micro ops) per thread. */
 830     Stats::Vector committedOps;
 831     /** Stat for the CPI per thread. */
 832     Stats::Formula cpi;
 833     /** Stat for the total CPI. */
 834     Stats::Formula totalCpi;
 835     /** Stat for the IPC per thread. */
 836     Stats::Formula ipc;
 837     /** Stat for the total IPC. */
 838     Stats::Formula totalIpc;
 839
 840     //number of integer register file accesses
 841     Stats::Scalar intRegfileReads;
 842     Stats::Scalar intRegfileWrites;
 843     //number of float register file accesses
 844     Stats::Scalar fpRegfileReads;
 845     Stats::Scalar fpRegfileWrites;
 846     //number of vector register file accesses
 847     mutable Stats::Scalar vecRegfileReads;
 848     Stats::Scalar vecRegfileWrites;
 849     //number of predicate register file accesses
 850     mutable Stats::Scalar vecPredRegfileReads;
 851     Stats::Scalar vecPredRegfileWrites;
 852     //number of CC register file accesses
 853     Stats::Scalar ccRegfileReads;
 854     Stats::Scalar ccRegfileWrites;
 855     //number of misc
 856     Stats::Scalar miscRegfileReads;
 857     Stats::Scalar miscRegfileWrites;
 858 };
 859
 860 #endif // __CPU_O3_CPU_HH__