src/cpu/o3/cpu.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Korey Sewell
  30  */
  31
  32 #ifndef __CPU_O3_CPU_HH__
  33 #define __CPU_O3_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/types.hh"
  42 #include "base/statistics.hh"
  43 #include "base/timebuf.hh"
  44 #include "config/full_system.hh"
  45 #include "cpu/activity.hh"
  46 #include "cpu/base.hh"
  47 #include "cpu/simple_thread.hh"
  48 #include "cpu/o3/comm.hh"
  49 #include "cpu/o3/cpu_policy.hh"
  50 #include "cpu/o3/scoreboard.hh"
  51 #include "cpu/o3/thread_state.hh"
  52 //#include "cpu/o3/thread_context.hh"
  53 #include "sim/process.hh"
  54
  55 template <class>
  56 class Checker;
  57 class ThreadContext;
  58 template <class>
  59 class O3ThreadContext;
  60
  61 class Checkpoint;
  62 class MemObject;
  63 class Process;
  64
  65 class BaseO3CPU : public BaseCPU
  66 {
  67     //Stuff that's pretty ISA independent will go here.
  68   public:
  69     typedef BaseCPU::Params Params;
  70
  71     BaseO3CPU(Params *params);
  72
  73     void regStats();
  74
  75     /** Sets this CPU's ID. */
  76     void setCpuId(int id) { cpu_id = id; }
  77
  78     /** Reads this CPU's ID. */
  79     int readCpuId() { return cpu_id; }
  80
  81   protected:
  82     int cpu_id;
  83 };
  84
  85 /**
  86  * FullO3CPU class, has each of the stages (fetch through commit)
  87  * within it, as well as all of the time buffers between stages.  The
  88  * tick() function for the CPU is defined here.
  89  */
  90 template <class Impl>
  91 class FullO3CPU : public BaseO3CPU
  92 {
  93   public:
  94     // Typedefs from the Impl here.
  95     typedef typename Impl::CPUPol CPUPolicy;
  96     typedef typename Impl::Params Params;
  97     typedef typename Impl::DynInstPtr DynInstPtr;
  98
  99     typedef O3ThreadState<Impl> Thread;
 100
 101     typedef typename std::list<DynInstPtr>::iterator ListIt;
 102
 103     friend class O3ThreadContext<Impl>;
 104
 105   public:
 106     enum Status {
 107         Running,
 108         Idle,
 109         Halted,
 110         Blocked,
 111         SwitchedOut
 112     };
 113
 114 #if FULL_SYSTEM
 115     TheISA::ITB * itb;
 116     TheISA::DTB * dtb;
 117 #endif
 118
 119     /** Overall CPU status. */
 120     Status _status;
 121
 122     /** Per-thread status in CPU, used for SMT.  */
 123     Status _threadStatus[Impl::MaxThreads];
 124
 125   private:
 126     class TickEvent : public Event
 127     {
 128       private:
 129         /** Pointer to the CPU. */
 130         FullO3CPU<Impl> *cpu;
 131
 132       public:
 133         /** Constructs a tick event. */
 134         TickEvent(FullO3CPU<Impl> *c);
 135
 136         /** Processes a tick event, calling tick() on the CPU. */
 137         void process();
 138         /** Returns the description of the tick event. */
 139         const char *description();
 140     };
 141
 142     /** The tick event used for scheduling CPU ticks. */
 143     TickEvent tickEvent;
 144
 145     /** Schedule tick event, regardless of its current state. */
 146     void scheduleTickEvent(int delay)
 147     {
 148         if (tickEvent.squashed())
 149             tickEvent.reschedule(curTick + cycles(delay));
 150         else if (!tickEvent.scheduled())
 151             tickEvent.schedule(curTick + cycles(delay));
 152     }
 153
 154     /** Unschedule tick event, regardless of its current state. */
 155     void unscheduleTickEvent()
 156     {
 157         if (tickEvent.scheduled())
 158             tickEvent.squash();
 159     }
 160
 161     class ActivateThreadEvent : public Event
 162     {
 163       private:
 164         /** Number of Thread to Activate */
 165         int tid;
 166
 167         /** Pointer to the CPU. */
 168         FullO3CPU<Impl> *cpu;
 169
 170       public:
 171         /** Constructs the event. */
 172         ActivateThreadEvent();
 173
 174         /** Initialize Event */
 175         void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
 176
 177         /** Processes the event, calling activateThread() on the CPU. */
 178         void process();
 179
 180         /** Returns the description of the event. */
 181         const char *description();
 182     };
 183
 184     /** Schedule thread to activate , regardless of its current state. */
 185     void scheduleActivateThreadEvent(int tid, int delay)
 186     {
 187         // Schedule thread to activate, regardless of its current state.
 188         if (activateThreadEvent[tid].squashed())
 189             activateThreadEvent[tid].reschedule(curTick + cycles(delay));
 190         else if (!activateThreadEvent[tid].scheduled())
 191             activateThreadEvent[tid].schedule(curTick + cycles(delay));
 192     }
 193
 194     /** Unschedule actiavte thread event, regardless of its current state. */
 195     void unscheduleActivateThreadEvent(int tid)
 196     {
 197         if (activateThreadEvent[tid].scheduled())
 198             activateThreadEvent[tid].squash();
 199     }
 200
 201     /** The tick event used for scheduling CPU ticks. */
 202     ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
 203
 204     class DeallocateContextEvent : public Event
 205     {
 206       private:
 207         /** Number of Thread to deactivate */
 208         int tid;
 209
 210         /** Should the thread be removed from the CPU? */
 211         bool remove;
 212
 213         /** Pointer to the CPU. */
 214         FullO3CPU<Impl> *cpu;
 215
 216       public:
 217         /** Constructs the event. */
 218         DeallocateContextEvent();
 219
 220         /** Initialize Event */
 221         void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
 222
 223         /** Processes the event, calling activateThread() on the CPU. */
 224         void process();
 225
 226         /** Sets whether the thread should also be removed from the CPU. */
 227         void setRemove(bool _remove) { remove = _remove; }
 228
 229         /** Returns the description of the event. */
 230         const char *description();
 231     };
 232
 233     /** Schedule cpu to deallocate thread context.*/
 234     void scheduleDeallocateContextEvent(int tid, bool remove, int delay)
 235     {
 236         // Schedule thread to activate, regardless of its current state.
 237         if (deallocateContextEvent[tid].squashed())
 238             deallocateContextEvent[tid].reschedule(curTick + cycles(delay));
 239         else if (!deallocateContextEvent[tid].scheduled())
 240             deallocateContextEvent[tid].schedule(curTick + cycles(delay));
 241     }
 242
 243     /** Unschedule thread deallocation in CPU */
 244     void unscheduleDeallocateContextEvent(int tid)
 245     {
 246         if (deallocateContextEvent[tid].scheduled())
 247             deallocateContextEvent[tid].squash();
 248     }
 249
 250     /** The tick event used for scheduling CPU ticks. */
 251     DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
 252
 253   public:
 254     /** Constructs a CPU with the given parameters. */
 255     FullO3CPU(Params *params);
 256     /** Destructor. */
 257     ~FullO3CPU();
 258
 259     /** Registers statistics. */
 260     void fullCPURegStats();
 261
 262     /** Returns a specific port. */
 263     Port *getPort(const std::string &if_name, int idx);
 264
 265     /** Ticks CPU, calling tick() on each stage, and checking the overall
 266      *  activity to see if the CPU should deschedule itself.
 267      */
 268     void tick();
 269
 270     /** Initialize the CPU */
 271     void init();
 272
 273     /** Returns the Number of Active Threads in the CPU */
 274     int numActiveThreads()
 275     { return activeThreads.size(); }
 276
 277     /** Add Thread to Active Threads List */
 278     void activateThread(unsigned tid);
 279
 280     /** Remove Thread from Active Threads List */
 281     void deactivateThread(unsigned tid);
 282
 283     /** Setup CPU to insert a thread's context */
 284     void insertThread(unsigned tid);
 285
 286     /** Remove all of a thread's context from CPU */
 287     void removeThread(unsigned tid);
 288
 289     /** Count the Total Instructions Committed in the CPU. */
 290     virtual Counter totalInstructions() const
 291     {
 292         Counter total(0);
 293
 294         for (int i=0; i < thread.size(); i++)
 295             total += thread[i]->numInst;
 296
 297         return total;
 298     }
 299
 300     /** Add Thread to Active Threads List. */
 301     void activateContext(int tid, int delay);
 302
 303     /** Remove Thread from Active Threads List */
 304     void suspendContext(int tid);
 305
 306     /** Remove Thread from Active Threads List &&
 307      *  Possibly Remove Thread Context from CPU.
 308      */
 309     bool deallocateContext(int tid, bool remove, int delay = 1);
 310
 311     /** Remove Thread from Active Threads List &&
 312      *  Remove Thread Context from CPU.
 313      */
 314     void haltContext(int tid);
 315
 316     /** Activate a Thread When CPU Resources are Available. */
 317     void activateWhenReady(int tid);
 318
 319     /** Add or Remove a Thread Context in the CPU. */
 320     void doContextSwitch();
 321
 322     /** Update The Order In Which We Process Threads. */
 323     void updateThreadPriority();
 324
 325     /** Serialize state. */
 326     virtual void serialize(std::ostream &os);
 327
 328     /** Unserialize from a checkpoint. */
 329     virtual void unserialize(Checkpoint *cp, const std::string &section);
 330
 331   public:
 332     /** Executes a syscall on this cycle.
 333      *  ---------------------------------------
 334      *  Note: this is a virtual function. CPU-Specific
 335      *  functionality defined in derived classes
 336      */
 337     virtual void syscall(int tid) { panic("Unimplemented!"); }
 338
 339     /** Starts draining the CPU's pipeline of all instructions in
 340      * order to stop all memory accesses. */
 341     virtual unsigned int drain(Event *drain_event);
 342
 343     /** Resumes execution after a drain. */
 344     virtual void resume();
 345
 346     /** Signals to this CPU that a stage has completed switching out. */
 347     void signalDrained();
 348
 349     /** Switches out this CPU. */
 350     virtual void switchOut();
 351
 352     /** Takes over from another CPU. */
 353     virtual void takeOverFrom(BaseCPU *oldCPU);
 354
 355     /** Get the current instruction sequence number, and increment it. */
 356     InstSeqNum getAndIncrementInstSeq()
 357     { return globalSeqNum++; }
 358
 359 #if FULL_SYSTEM
 360     /** Check if this address is a valid instruction address. */
 361     bool validInstAddr(Addr addr) { return true; }
 362
 363     /** Check if this address is a valid data address. */
 364     bool validDataAddr(Addr addr) { return true; }
 365
 366     /** Get instruction asid. */
 367     int getInstAsid(unsigned tid)
 368     { return regFile.miscRegs[tid].getInstAsid(); }
 369
 370     /** Get data asid. */
 371     int getDataAsid(unsigned tid)
 372     { return regFile.miscRegs[tid].getDataAsid(); }
 373 #else
 374     /** Get instruction asid. */
 375     int getInstAsid(unsigned tid)
 376     { return thread[tid]->getInstAsid(); }
 377
 378     /** Get data asid. */
 379     int getDataAsid(unsigned tid)
 380     { return thread[tid]->getDataAsid(); }
 381
 382 #endif
 383
 384     /** Register accessors.  Index refers to the physical register index. */
 385     uint64_t readIntReg(int reg_idx);
 386
 387     TheISA::FloatReg readFloatReg(int reg_idx);
 388
 389     TheISA::FloatReg readFloatReg(int reg_idx, int width);
 390
 391     TheISA::FloatRegBits readFloatRegBits(int reg_idx);
 392
 393     TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
 394
 395     void setIntReg(int reg_idx, uint64_t val);
 396
 397     void setFloatReg(int reg_idx, TheISA::FloatReg val);
 398
 399     void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
 400
 401     void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
 402
 403     void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
 404
 405     uint64_t readArchIntReg(int reg_idx, unsigned tid);
 406
 407     float readArchFloatRegSingle(int reg_idx, unsigned tid);
 408
 409     double readArchFloatRegDouble(int reg_idx, unsigned tid);
 410
 411     uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
 412
 413     /** Architectural register accessors.  Looks up in the commit
 414      * rename table to obtain the true physical index of the
 415      * architected register first, then accesses that physical
 416      * register.
 417      */
 418     void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
 419
 420     void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
 421
 422     void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
 423
 424     void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
 425
 426     /** Reads the commit PC of a specific thread. */
 427     uint64_t readPC(unsigned tid);
 428
 429     /** Sets the commit PC of a specific thread. */
 430     void setPC(Addr new_PC, unsigned tid);
 431
 432     /** Reads the next PC of a specific thread. */
 433     uint64_t readNextPC(unsigned tid);
 434
 435     /** Sets the next PC of a specific thread. */
 436     void setNextPC(uint64_t val, unsigned tid);
 437
 438     /** Reads the next NPC of a specific thread. */
 439     uint64_t readNextNPC(unsigned tid);
 440
 441     /** Sets the next NPC of a specific thread. */
 442     void setNextNPC(uint64_t val, unsigned tid);
 443
 444     /** Function to add instruction onto the head of the list of the
 445      *  instructions.  Used when new instructions are fetched.
 446      */
 447     ListIt addInst(DynInstPtr &inst);
 448
 449     /** Function to tell the CPU that an instruction has completed. */
 450     void instDone(unsigned tid);
 451
 452     /** Add Instructions to the CPU Remove List*/
 453     void addToRemoveList(DynInstPtr &inst);
 454
 455     /** Remove an instruction from the front end of the list.  There's
 456      *  no restriction on location of the instruction.
 457      */
 458     void removeFrontInst(DynInstPtr &inst);
 459
 460     /** Remove all instructions that are not currently in the ROB.
 461      *  There's also an option to not squash delay slot instructions.*/
 462     void removeInstsNotInROB(unsigned tid, bool squash_delay_slot,
 463                              const InstSeqNum &delay_slot_seq_num);
 464
 465     /** Remove all instructions younger than the given sequence number. */
 466     void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
 467
 468     /** Removes the instruction pointed to by the iterator. */
 469     inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
 470
 471     /** Cleans up all instructions on the remove list. */
 472     void cleanUpRemovedInsts();
 473
 474     /** Debug function to print all instructions on the list. */
 475     void dumpInsts();
 476
 477   public:
 478     /** List of all the instructions in flight. */
 479     std::list<DynInstPtr> instList;
 480
 481     /** List of all the instructions that will be removed at the end of this
 482      *  cycle.
 483      */
 484     std::queue<ListIt> removeList;
 485
 486 #ifdef DEBUG
 487     /** Debug structure to keep track of the sequence numbers still in
 488      * flight.
 489      */
 490     std::set<InstSeqNum> snList;
 491 #endif
 492
 493     /** Records if instructions need to be removed this cycle due to
 494      *  being retired or squashed.
 495      */
 496     bool removeInstsThisCycle;
 497
 498   protected:
 499     /** The fetch stage. */
 500     typename CPUPolicy::Fetch fetch;
 501
 502     /** The decode stage. */
 503     typename CPUPolicy::Decode decode;
 504
 505     /** The dispatch stage. */
 506     typename CPUPolicy::Rename rename;
 507
 508     /** The issue/execute/writeback stages. */
 509     typename CPUPolicy::IEW iew;
 510
 511     /** The commit stage. */
 512     typename CPUPolicy::Commit commit;
 513
 514     /** The register file. */
 515     typename CPUPolicy::RegFile regFile;
 516
 517     /** The free list. */
 518     typename CPUPolicy::FreeList freeList;
 519
 520     /** The rename map. */
 521     typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
 522
 523     /** The commit rename map. */
 524     typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
 525
 526     /** The re-order buffer. */
 527     typename CPUPolicy::ROB rob;
 528
 529     /** Active Threads List */
 530     std::list<unsigned> activeThreads;
 531
 532     /** Integer Register Scoreboard */
 533     Scoreboard scoreboard;
 534
 535   public:
 536     /** Enum to give each stage a specific index, so when calling
 537      *  activateStage() or deactivateStage(), they can specify which stage
 538      *  is being activated/deactivated.
 539      */
 540     enum StageIdx {
 541         FetchIdx,
 542         DecodeIdx,
 543         RenameIdx,
 544         IEWIdx,
 545         CommitIdx,
 546         NumStages };
 547
 548     /** Typedefs from the Impl to get the structs that each of the
 549      *  time buffers should use.
 550      */
 551     typedef typename CPUPolicy::TimeStruct TimeStruct;
 552
 553     typedef typename CPUPolicy::FetchStruct FetchStruct;
 554
 555     typedef typename CPUPolicy::DecodeStruct DecodeStruct;
 556
 557     typedef typename CPUPolicy::RenameStruct RenameStruct;
 558
 559     typedef typename CPUPolicy::IEWStruct IEWStruct;
 560
 561     /** The main time buffer to do backwards communication. */
 562     TimeBuffer<TimeStruct> timeBuffer;
 563
 564     /** The fetch stage's instruction queue. */
 565     TimeBuffer<FetchStruct> fetchQueue;
 566
 567     /** The decode stage's instruction queue. */
 568     TimeBuffer<DecodeStruct> decodeQueue;
 569
 570     /** The rename stage's instruction queue. */
 571     TimeBuffer<RenameStruct> renameQueue;
 572
 573     /** The IEW stage's instruction queue. */
 574     TimeBuffer<IEWStruct> iewQueue;
 575
 576   private:
 577     /** The activity recorder; used to tell if the CPU has any
 578      * activity remaining or if it can go to idle and deschedule
 579      * itself.
 580      */
 581     ActivityRecorder activityRec;
 582
 583   public:
 584     /** Records that there was time buffer activity this cycle. */
 585     void activityThisCycle() { activityRec.activity(); }
 586
 587     /** Changes a stage's status to active within the activity recorder. */
 588     void activateStage(const StageIdx idx)
 589     { activityRec.activateStage(idx); }
 590
 591     /** Changes a stage's status to inactive within the activity recorder. */
 592     void deactivateStage(const StageIdx idx)
 593     { activityRec.deactivateStage(idx); }
 594
 595     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 596     void wakeCPU();
 597
 598     /** Gets a free thread id. Use if thread ids change across system. */
 599     int getFreeTid();
 600
 601   public:
 602     /** Returns a pointer to a thread context. */
 603     ThreadContext *tcBase(unsigned tid)
 604     {
 605         return thread[tid]->getTC();
 606     }
 607
 608     /** The global sequence number counter. */
 609     InstSeqNum globalSeqNum;//[Impl::MaxThreads];
 610
 611     /** Pointer to the checker, which can dynamically verify
 612      * instruction results at run time.  This can be set to NULL if it
 613      * is not being used.
 614      */
 615     Checker<DynInstPtr> *checker;
 616
 617 #if FULL_SYSTEM
 618     /** Pointer to the system. */
 619     System *system;
 620
 621     /** Pointer to physical memory. */
 622     PhysicalMemory *physmem;
 623 #endif
 624
 625     /** Event to call process() on once draining has completed. */
 626     Event *drainEvent;
 627
 628     /** Counter of how many stages have completed draining. */
 629     int drainCount;
 630
 631     /** Pointers to all of the threads in the CPU. */
 632     std::vector<Thread *> thread;
 633
 634     /** Whether or not the CPU should defer its registration. */
 635     bool deferRegistration;
 636
 637     /** Is there a context switch pending? */
 638     bool contextSwitch;
 639
 640     /** Threads Scheduled to Enter CPU */
 641     std::list<int> cpuWaitList;
 642
 643     /** The cycle that the CPU was last running, used for statistics. */
 644     Tick lastRunningCycle;
 645
 646     /** The cycle that the CPU was last activated by a new thread*/
 647     Tick lastActivatedCycle;
 648
 649     /** Number of Threads CPU can process */
 650     unsigned numThreads;
 651
 652     /** Mapping for system thread id to cpu id */
 653     std::map<unsigned,unsigned> threadMap;
 654
 655     /** Available thread ids in the cpu*/
 656     std::vector<unsigned> tids;
 657
 658     /** Stat for total number of times the CPU is descheduled. */
 659     Stats::Scalar<> timesIdled;
 660     /** Stat for total number of cycles the CPU spends descheduled. */
 661     Stats::Scalar<> idleCycles;
 662     /** Stat for the number of committed instructions per thread. */
 663     Stats::Vector<> committedInsts;
 664     /** Stat for the total number of committed instructions. */
 665     Stats::Scalar<> totalCommittedInsts;
 666     /** Stat for the CPI per thread. */
 667     Stats::Formula cpi;
 668     /** Stat for the total CPI. */
 669     Stats::Formula totalCpi;
 670     /** Stat for the IPC per thread. */
 671     Stats::Formula ipc;
 672     /** Stat for the total IPC. */
 673     Stats::Formula totalIpc;
 674 };
 675
 676 #endif // __CPU_O3_CPU_HH__