src/cpu/o3/cpu.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Korey Sewell
  30  */
  31
  32 #ifndef __CPU_O3_CPU_HH__
  33 #define __CPU_O3_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/types.hh"
  42 #include "base/statistics.hh"
  43 #include "base/timebuf.hh"
  44 #include "config/full_system.hh"
  45 #include "config/use_checker.hh"
  46 #include "cpu/activity.hh"
  47 #include "cpu/base.hh"
  48 #include "cpu/simple_thread.hh"
  49 #include "cpu/o3/comm.hh"
  50 #include "cpu/o3/cpu_policy.hh"
  51 #include "cpu/o3/scoreboard.hh"
  52 #include "cpu/o3/thread_state.hh"
  53 //#include "cpu/o3/thread_context.hh"
  54 #include "sim/process.hh"
  55
  56 #include "params/DerivO3CPU.hh"
  57
  58 template <class>
  59 class Checker;
  60 class ThreadContext;
  61 template <class>
  62 class O3ThreadContext;
  63
  64 class Checkpoint;
  65 class MemObject;
  66 class Process;
  67
  68 class BaseCPUParams;
  69
  70 class BaseO3CPU : public BaseCPU
  71 {
  72     //Stuff that's pretty ISA independent will go here.
  73   public:
  74     BaseO3CPU(BaseCPUParams *params);
  75
  76     void regStats();
  77 };
  78
  79 /**
  80  * FullO3CPU class, has each of the stages (fetch through commit)
  81  * within it, as well as all of the time buffers between stages.  The
  82  * tick() function for the CPU is defined here.
  83  */
  84 template <class Impl>
  85 class FullO3CPU : public BaseO3CPU
  86 {
  87   public:
  88     // Typedefs from the Impl here.
  89     typedef typename Impl::CPUPol CPUPolicy;
  90     typedef typename Impl::DynInstPtr DynInstPtr;
  91     typedef typename Impl::O3CPU O3CPU;
  92
  93     typedef O3ThreadState<Impl> ImplState;
  94     typedef O3ThreadState<Impl> Thread;
  95
  96     typedef typename std::list<DynInstPtr>::iterator ListIt;
  97
  98     friend class O3ThreadContext<Impl>;
  99
 100   public:
 101     enum Status {
 102         Running,
 103         Idle,
 104         Halted,
 105         Blocked,
 106         SwitchedOut
 107     };
 108
 109     TheISA::TLB * itb;
 110     TheISA::TLB * dtb;
 111
 112     /** Overall CPU status. */
 113     Status _status;
 114
 115     /** Per-thread status in CPU, used for SMT.  */
 116     Status _threadStatus[Impl::MaxThreads];
 117
 118   private:
 119     class TickEvent : public Event
 120     {
 121       private:
 122         /** Pointer to the CPU. */
 123         FullO3CPU<Impl> *cpu;
 124
 125       public:
 126         /** Constructs a tick event. */
 127         TickEvent(FullO3CPU<Impl> *c);
 128
 129         /** Processes a tick event, calling tick() on the CPU. */
 130         void process();
 131         /** Returns the description of the tick event. */
 132         const char *description() const;
 133     };
 134
 135     /** The tick event used for scheduling CPU ticks. */
 136     TickEvent tickEvent;
 137
 138     /** Schedule tick event, regardless of its current state. */
 139     void scheduleTickEvent(int delay)
 140     {
 141         if (tickEvent.squashed())
 142             reschedule(tickEvent, nextCycle(curTick + ticks(delay)));
 143         else if (!tickEvent.scheduled())
 144             schedule(tickEvent, nextCycle(curTick + ticks(delay)));
 145     }
 146
 147     /** Unschedule tick event, regardless of its current state. */
 148     void unscheduleTickEvent()
 149     {
 150         if (tickEvent.scheduled())
 151             tickEvent.squash();
 152     }
 153
 154     class ActivateThreadEvent : public Event
 155     {
 156       private:
 157         /** Number of Thread to Activate */
 158         ThreadID tid;
 159
 160         /** Pointer to the CPU. */
 161         FullO3CPU<Impl> *cpu;
 162
 163       public:
 164         /** Constructs the event. */
 165         ActivateThreadEvent();
 166
 167         /** Initialize Event */
 168         void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
 169
 170         /** Processes the event, calling activateThread() on the CPU. */
 171         void process();
 172
 173         /** Returns the description of the event. */
 174         const char *description() const;
 175     };
 176
 177     /** Schedule thread to activate , regardless of its current state. */
 178     void
 179     scheduleActivateThreadEvent(ThreadID tid, int delay)
 180     {
 181         // Schedule thread to activate, regardless of its current state.
 182         if (activateThreadEvent[tid].squashed())
 183             reschedule(activateThreadEvent[tid],
 184                 nextCycle(curTick + ticks(delay)));
 185         else if (!activateThreadEvent[tid].scheduled())
 186             schedule(activateThreadEvent[tid],
 187                 nextCycle(curTick + ticks(delay)));
 188     }
 189
 190     /** Unschedule actiavte thread event, regardless of its current state. */
 191     void
 192     unscheduleActivateThreadEvent(ThreadID tid)
 193     {
 194         if (activateThreadEvent[tid].scheduled())
 195             activateThreadEvent[tid].squash();
 196     }
 197
 198     /** The tick event used for scheduling CPU ticks. */
 199     ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
 200
 201     class DeallocateContextEvent : public Event
 202     {
 203       private:
 204         /** Number of Thread to deactivate */
 205         ThreadID tid;
 206
 207         /** Should the thread be removed from the CPU? */
 208         bool remove;
 209
 210         /** Pointer to the CPU. */
 211         FullO3CPU<Impl> *cpu;
 212
 213       public:
 214         /** Constructs the event. */
 215         DeallocateContextEvent();
 216
 217         /** Initialize Event */
 218         void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
 219
 220         /** Processes the event, calling activateThread() on the CPU. */
 221         void process();
 222
 223         /** Sets whether the thread should also be removed from the CPU. */
 224         void setRemove(bool _remove) { remove = _remove; }
 225
 226         /** Returns the description of the event. */
 227         const char *description() const;
 228     };
 229
 230     /** Schedule cpu to deallocate thread context.*/
 231     void
 232     scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay)
 233     {
 234         // Schedule thread to activate, regardless of its current state.
 235         if (deallocateContextEvent[tid].squashed())
 236             reschedule(deallocateContextEvent[tid],
 237                 nextCycle(curTick + ticks(delay)));
 238         else if (!deallocateContextEvent[tid].scheduled())
 239             schedule(deallocateContextEvent[tid],
 240                 nextCycle(curTick + ticks(delay)));
 241     }
 242
 243     /** Unschedule thread deallocation in CPU */
 244     void
 245     unscheduleDeallocateContextEvent(ThreadID tid)
 246     {
 247         if (deallocateContextEvent[tid].scheduled())
 248             deallocateContextEvent[tid].squash();
 249     }
 250
 251     /** The tick event used for scheduling CPU ticks. */
 252     DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
 253
 254   public:
 255     /** Constructs a CPU with the given parameters. */
 256     FullO3CPU(DerivO3CPUParams *params);
 257     /** Destructor. */
 258     ~FullO3CPU();
 259
 260     /** Registers statistics. */
 261     void regStats();
 262
 263     void demapPage(Addr vaddr, uint64_t asn)
 264     {
 265         this->itb->demapPage(vaddr, asn);
 266         this->dtb->demapPage(vaddr, asn);
 267     }
 268
 269     void demapInstPage(Addr vaddr, uint64_t asn)
 270     {
 271         this->itb->demapPage(vaddr, asn);
 272     }
 273
 274     void demapDataPage(Addr vaddr, uint64_t asn)
 275     {
 276         this->dtb->demapPage(vaddr, asn);
 277     }
 278
 279     /** Returns a specific port. */
 280     Port *getPort(const std::string &if_name, int idx);
 281
 282     /** Ticks CPU, calling tick() on each stage, and checking the overall
 283      *  activity to see if the CPU should deschedule itself.
 284      */
 285     void tick();
 286
 287     /** Initialize the CPU */
 288     void init();
 289
 290     /** Returns the Number of Active Threads in the CPU */
 291     int numActiveThreads()
 292     { return activeThreads.size(); }
 293
 294     /** Add Thread to Active Threads List */
 295     void activateThread(ThreadID tid);
 296
 297     /** Remove Thread from Active Threads List */
 298     void deactivateThread(ThreadID tid);
 299
 300     /** Setup CPU to insert a thread's context */
 301     void insertThread(ThreadID tid);
 302
 303     /** Remove all of a thread's context from CPU */
 304     void removeThread(ThreadID tid);
 305
 306     /** Count the Total Instructions Committed in the CPU. */
 307     virtual Counter totalInstructions() const;
 308
 309     /** Add Thread to Active Threads List. */
 310     void activateContext(ThreadID tid, int delay);
 311
 312     /** Remove Thread from Active Threads List */
 313     void suspendContext(ThreadID tid);
 314
 315     /** Remove Thread from Active Threads List &&
 316      *  Possibly Remove Thread Context from CPU.
 317      */
 318     bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
 319
 320     /** Remove Thread from Active Threads List &&
 321      *  Remove Thread Context from CPU.
 322      */
 323     void haltContext(ThreadID tid);
 324
 325     /** Activate a Thread When CPU Resources are Available. */
 326     void activateWhenReady(ThreadID tid);
 327
 328     /** Add or Remove a Thread Context in the CPU. */
 329     void doContextSwitch();
 330
 331     /** Update The Order In Which We Process Threads. */
 332     void updateThreadPriority();
 333
 334     /** Serialize state. */
 335     virtual void serialize(std::ostream &os);
 336
 337     /** Unserialize from a checkpoint. */
 338     virtual void unserialize(Checkpoint *cp, const std::string &section);
 339
 340   public:
 341 #if !FULL_SYSTEM
 342     /** Executes a syscall.
 343      * @todo: Determine if this needs to be virtual.
 344      */
 345     void syscall(int64_t callnum, ThreadID tid);
 346 #endif
 347
 348     /** Starts draining the CPU's pipeline of all instructions in
 349      * order to stop all memory accesses. */
 350     virtual unsigned int drain(Event *drain_event);
 351
 352     /** Resumes execution after a drain. */
 353     virtual void resume();
 354
 355     /** Signals to this CPU that a stage has completed switching out. */
 356     void signalDrained();
 357
 358     /** Switches out this CPU. */
 359     virtual void switchOut();
 360
 361     /** Takes over from another CPU. */
 362     virtual void takeOverFrom(BaseCPU *oldCPU);
 363
 364     /** Get the current instruction sequence number, and increment it. */
 365     InstSeqNum getAndIncrementInstSeq()
 366     { return globalSeqNum++; }
 367
 368     /** Traps to handle given fault. */
 369     void trap(Fault fault, ThreadID tid);
 370
 371 #if FULL_SYSTEM
 372     /** HW return from error interrupt. */
 373     Fault hwrei(ThreadID tid);
 374
 375     bool simPalCheck(int palFunc, ThreadID tid);
 376
 377     /** Returns the Fault for any valid interrupt. */
 378     Fault getInterrupts();
 379
 380     /** Processes any an interrupt fault. */
 381     void processInterrupts(Fault interrupt);
 382
 383     /** Halts the CPU. */
 384     void halt() { panic("Halt not implemented!\n"); }
 385
 386     /** Update the Virt and Phys ports of all ThreadContexts to
 387      * reflect change in memory connections. */
 388     void updateMemPorts();
 389
 390     /** Check if this address is a valid instruction address. */
 391     bool validInstAddr(Addr addr) { return true; }
 392
 393     /** Check if this address is a valid data address. */
 394     bool validDataAddr(Addr addr) { return true; }
 395
 396     /** Get instruction asid. */
 397     int getInstAsid(ThreadID tid)
 398     { return isa[tid].instAsid(); }
 399
 400     /** Get data asid. */
 401     int getDataAsid(ThreadID tid)
 402     { return isa[tid].dataAsid(); }
 403 #else
 404     /** Get instruction asid. */
 405     int getInstAsid(ThreadID tid)
 406     { return thread[tid]->getInstAsid(); }
 407
 408     /** Get data asid. */
 409     int getDataAsid(ThreadID tid)
 410     { return thread[tid]->getDataAsid(); }
 411
 412 #endif
 413
 414     /** Register accessors.  Index refers to the physical register index. */
 415
 416     /** Reads a miscellaneous register. */
 417     TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
 418
 419     /** Reads a misc. register, including any side effects the read
 420      * might have as defined by the architecture.
 421      */
 422     TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
 423
 424     /** Sets a miscellaneous register. */
 425     void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
 426             ThreadID tid);
 427
 428     /** Sets a misc. register, including any side effects the write
 429      * might have as defined by the architecture.
 430      */
 431     void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
 432             ThreadID tid);
 433
 434     uint64_t readIntReg(int reg_idx);
 435
 436     TheISA::FloatReg readFloatReg(int reg_idx);
 437
 438     TheISA::FloatReg readFloatReg(int reg_idx, int width);
 439
 440     TheISA::FloatRegBits readFloatRegBits(int reg_idx);
 441
 442     TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
 443
 444     void setIntReg(int reg_idx, uint64_t val);
 445
 446     void setFloatReg(int reg_idx, TheISA::FloatReg val);
 447
 448     void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
 449
 450     void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
 451
 452     void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
 453
 454     uint64_t readArchIntReg(int reg_idx, ThreadID tid);
 455
 456     float readArchFloatRegSingle(int reg_idx, ThreadID tid);
 457
 458     double readArchFloatRegDouble(int reg_idx, ThreadID tid);
 459
 460     uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
 461
 462     /** Architectural register accessors.  Looks up in the commit
 463      * rename table to obtain the true physical index of the
 464      * architected register first, then accesses that physical
 465      * register.
 466      */
 467     void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
 468
 469     void setArchFloatRegSingle(int reg_idx, float val, ThreadID tid);
 470
 471     void setArchFloatRegDouble(int reg_idx, double val, ThreadID tid);
 472
 473     void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
 474
 475     /** Reads the commit PC of a specific thread. */
 476     Addr readPC(ThreadID tid);
 477
 478     /** Sets the commit PC of a specific thread. */
 479     void setPC(Addr new_PC, ThreadID tid);
 480
 481     /** Reads the commit micro PC of a specific thread. */
 482     Addr readMicroPC(ThreadID tid);
 483
 484     /** Sets the commmit micro PC of a specific thread. */
 485     void setMicroPC(Addr new_microPC, ThreadID tid);
 486
 487     /** Reads the next PC of a specific thread. */
 488     Addr readNextPC(ThreadID tid);
 489
 490     /** Sets the next PC of a specific thread. */
 491     void setNextPC(Addr val, ThreadID tid);
 492
 493     /** Reads the next NPC of a specific thread. */
 494     Addr readNextNPC(ThreadID tid);
 495
 496     /** Sets the next NPC of a specific thread. */
 497     void setNextNPC(Addr val, ThreadID tid);
 498
 499     /** Reads the commit next micro PC of a specific thread. */
 500     Addr readNextMicroPC(ThreadID tid);
 501
 502     /** Sets the commit next micro PC of a specific thread. */
 503     void setNextMicroPC(Addr val, ThreadID tid);
 504
 505     /** Initiates a squash of all in-flight instructions for a given
 506      * thread.  The source of the squash is an external update of
 507      * state through the TC.
 508      */
 509     void squashFromTC(ThreadID tid);
 510
 511     /** Function to add instruction onto the head of the list of the
 512      *  instructions.  Used when new instructions are fetched.
 513      */
 514     ListIt addInst(DynInstPtr &inst);
 515
 516     /** Function to tell the CPU that an instruction has completed. */
 517     void instDone(ThreadID tid);
 518
 519     /** Add Instructions to the CPU Remove List*/
 520     void addToRemoveList(DynInstPtr &inst);
 521
 522     /** Remove an instruction from the front end of the list.  There's
 523      *  no restriction on location of the instruction.
 524      */
 525     void removeFrontInst(DynInstPtr &inst);
 526
 527     /** Remove all instructions that are not currently in the ROB.
 528      *  There's also an option to not squash delay slot instructions.*/
 529     void removeInstsNotInROB(ThreadID tid);
 530
 531     /** Remove all instructions younger than the given sequence number. */
 532     void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
 533
 534     /** Removes the instruction pointed to by the iterator. */
 535     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 536
 537     /** Cleans up all instructions on the remove list. */
 538     void cleanUpRemovedInsts();
 539
 540     /** Debug function to print all instructions on the list. */
 541     void dumpInsts();
 542
 543   public:
 544 #ifndef NDEBUG
 545     /** Count of total number of dynamic instructions in flight. */
 546     int instcount;
 547 #endif
 548
 549     /** List of all the instructions in flight. */
 550     std::list<DynInstPtr> instList;
 551
 552     /** List of all the instructions that will be removed at the end of this
 553      *  cycle.
 554      */
 555     std::queue<ListIt> removeList;
 556
 557 #ifdef DEBUG
 558     /** Debug structure to keep track of the sequence numbers still in
 559      * flight.
 560      */
 561     std::set<InstSeqNum> snList;
 562 #endif
 563
 564     /** Records if instructions need to be removed this cycle due to
 565      *  being retired or squashed.
 566      */
 567     bool removeInstsThisCycle;
 568
 569   protected:
 570     /** The fetch stage. */
 571     typename CPUPolicy::Fetch fetch;
 572
 573     /** The decode stage. */
 574     typename CPUPolicy::Decode decode;
 575
 576     /** The dispatch stage. */
 577     typename CPUPolicy::Rename rename;
 578
 579     /** The issue/execute/writeback stages. */
 580     typename CPUPolicy::IEW iew;
 581
 582     /** The commit stage. */
 583     typename CPUPolicy::Commit commit;
 584
 585     /** The register file. */
 586     typename CPUPolicy::RegFile regFile;
 587
 588     /** The free list. */
 589     typename CPUPolicy::FreeList freeList;
 590
 591     /** The rename map. */
 592     typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
 593
 594     /** The commit rename map. */
 595     typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
 596
 597     /** The re-order buffer. */
 598     typename CPUPolicy::ROB rob;
 599
 600     /** Active Threads List */
 601     std::list<ThreadID> activeThreads;
 602
 603     /** Integer Register Scoreboard */
 604     Scoreboard scoreboard;
 605
 606     TheISA::ISA isa[Impl::MaxThreads];
 607
 608   public:
 609     /** Enum to give each stage a specific index, so when calling
 610      *  activateStage() or deactivateStage(), they can specify which stage
 611      *  is being activated/deactivated.
 612      */
 613     enum StageIdx {
 614         FetchIdx,
 615         DecodeIdx,
 616         RenameIdx,
 617         IEWIdx,
 618         CommitIdx,
 619         NumStages };
 620
 621     /** Typedefs from the Impl to get the structs that each of the
 622      *  time buffers should use.
 623      */
 624     typedef typename CPUPolicy::TimeStruct TimeStruct;
 625
 626     typedef typename CPUPolicy::FetchStruct FetchStruct;
 627
 628     typedef typename CPUPolicy::DecodeStruct DecodeStruct;
 629
 630     typedef typename CPUPolicy::RenameStruct RenameStruct;
 631
 632     typedef typename CPUPolicy::IEWStruct IEWStruct;
 633
 634     /** The main time buffer to do backwards communication. */
 635     TimeBuffer<TimeStruct> timeBuffer;
 636
 637     /** The fetch stage's instruction queue. */
 638     TimeBuffer<FetchStruct> fetchQueue;
 639
 640     /** The decode stage's instruction queue. */
 641     TimeBuffer<DecodeStruct> decodeQueue;
 642
 643     /** The rename stage's instruction queue. */
 644     TimeBuffer<RenameStruct> renameQueue;
 645
 646     /** The IEW stage's instruction queue. */
 647     TimeBuffer<IEWStruct> iewQueue;
 648
 649   private:
 650     /** The activity recorder; used to tell if the CPU has any
 651      * activity remaining or if it can go to idle and deschedule
 652      * itself.
 653      */
 654     ActivityRecorder activityRec;
 655
 656   public:
 657     /** Records that there was time buffer activity this cycle. */
 658     void activityThisCycle() { activityRec.activity(); }
 659
 660     /** Changes a stage's status to active within the activity recorder. */
 661     void activateStage(const StageIdx idx)
 662     { activityRec.activateStage(idx); }
 663
 664     /** Changes a stage's status to inactive within the activity recorder. */
 665     void deactivateStage(const StageIdx idx)
 666     { activityRec.deactivateStage(idx); }
 667
 668     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 669     void wakeCPU();
 670
 671 #if FULL_SYSTEM
 672     virtual void wakeup();
 673 #endif
 674
 675     /** Gets a free thread id. Use if thread ids change across system. */
 676     ThreadID getFreeTid();
 677
 678   public:
 679     /** Returns a pointer to a thread context. */
 680     ThreadContext *
 681     tcBase(ThreadID tid)
 682     {
 683         return thread[tid]->getTC();
 684     }
 685
 686     /** The global sequence number counter. */
 687     InstSeqNum globalSeqNum;//[Impl::MaxThreads];
 688
 689 #if USE_CHECKER
 690     /** Pointer to the checker, which can dynamically verify
 691      * instruction results at run time.  This can be set to NULL if it
 692      * is not being used.
 693      */
 694     Checker<DynInstPtr> *checker;
 695 #endif
 696
 697 #if FULL_SYSTEM
 698     /** Pointer to the system. */
 699     System *system;
 700
 701     /** Pointer to physical memory. */
 702     PhysicalMemory *physmem;
 703 #endif
 704
 705     /** Event to call process() on once draining has completed. */
 706     Event *drainEvent;
 707
 708     /** Counter of how many stages have completed draining. */
 709     int drainCount;
 710
 711     /** Pointers to all of the threads in the CPU. */
 712     std::vector<Thread *> thread;
 713
 714     /** Whether or not the CPU should defer its registration. */
 715     bool deferRegistration;
 716
 717     /** Is there a context switch pending? */
 718     bool contextSwitch;
 719
 720     /** Threads Scheduled to Enter CPU */
 721     std::list<int> cpuWaitList;
 722
 723     /** The cycle that the CPU was last running, used for statistics. */
 724     Tick lastRunningCycle;
 725
 726     /** The cycle that the CPU was last activated by a new thread*/
 727     Tick lastActivatedCycle;
 728
 729     /** Mapping for system thread id to cpu id */
 730     std::map<ThreadID, unsigned> threadMap;
 731
 732     /** Available thread ids in the cpu*/
 733     std::vector<ThreadID> tids;
 734
 735     /** CPU read function, forwards read to LSQ. */
 736     template <class T>
 737     Fault read(RequestPtr &req, T &data, int load_idx)
 738     {
 739         return this->iew.ldstQueue.read(req, data, load_idx);
 740     }
 741
 742     /** CPU write function, forwards write to LSQ. */
 743     template <class T>
 744     Fault write(RequestPtr &req, T &data, int store_idx)
 745     {
 746         return this->iew.ldstQueue.write(req, data, store_idx);
 747     }
 748
 749     Addr lockAddr;
 750
 751     /** Temporary fix for the lock flag, works in the UP case. */
 752     bool lockFlag;
 753
 754     /** Stat for total number of times the CPU is descheduled. */
 755     Stats::Scalar timesIdled;
 756     /** Stat for total number of cycles the CPU spends descheduled. */
 757     Stats::Scalar idleCycles;
 758     /** Stat for the number of committed instructions per thread. */
 759     Stats::Vector committedInsts;
 760     /** Stat for the total number of committed instructions. */
 761     Stats::Scalar totalCommittedInsts;
 762     /** Stat for the CPI per thread. */
 763     Stats::Formula cpi;
 764     /** Stat for the total CPI. */
 765     Stats::Formula totalCpi;
 766     /** Stat for the IPC per thread. */
 767     Stats::Formula ipc;
 768     /** Stat for the total IPC. */
 769     Stats::Formula totalIpc;
 770 };
 771
 772 #endif // __CPU_O3_CPU_HH__