2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
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34 #ifndef __CPU_O3_CPU_HH__
35 #define __CPU_O3_CPU_HH__
43 #include "arch/types.hh"
44 #include "base/statistics.hh"
45 #include "config/full_system.hh"
46 #include "config/the_isa.hh"
47 #include "config/use_checker.hh"
48 #include "cpu/o3/comm.hh"
49 #include "cpu/o3/cpu_policy.hh"
50 #include "cpu/o3/scoreboard.hh"
51 #include "cpu/o3/thread_state.hh"
52 #include "cpu/activity.hh"
53 #include "cpu/base.hh"
54 #include "cpu/simple_thread.hh"
55 #include "cpu/timebuf.hh"
56 //#include "cpu/o3/thread_context.hh"
57 #include "params/DerivO3CPU.hh"
58 #include "sim/process.hh"
64 class O3ThreadContext;
72 class BaseO3CPU : public BaseCPU
74 //Stuff that's pretty ISA independent will go here.
76 BaseO3CPU(BaseCPUParams *params);
82 * FullO3CPU class, has each of the stages (fetch through commit)
83 * within it, as well as all of the time buffers between stages. The
84 * tick() function for the CPU is defined here.
87 class FullO3CPU : public BaseO3CPU
90 // Typedefs from the Impl here.
91 typedef typename Impl::CPUPol CPUPolicy;
92 typedef typename Impl::DynInstPtr DynInstPtr;
93 typedef typename Impl::O3CPU O3CPU;
95 typedef O3ThreadState<Impl> ImplState;
96 typedef O3ThreadState<Impl> Thread;
98 typedef typename std::list<DynInstPtr>::iterator ListIt;
100 friend class O3ThreadContext<Impl>;
114 /** Overall CPU status. */
117 /** Per-thread status in CPU, used for SMT. */
118 Status _threadStatus[Impl::MaxThreads];
121 class TickEvent : public Event
124 /** Pointer to the CPU. */
125 FullO3CPU<Impl> *cpu;
128 /** Constructs a tick event. */
129 TickEvent(FullO3CPU<Impl> *c);
131 /** Processes a tick event, calling tick() on the CPU. */
133 /** Returns the description of the tick event. */
134 const char *description() const;
137 /** The tick event used for scheduling CPU ticks. */
140 /** Schedule tick event, regardless of its current state. */
141 void scheduleTickEvent(int delay)
143 if (tickEvent.squashed())
144 reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
145 else if (!tickEvent.scheduled())
146 schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
149 /** Unschedule tick event, regardless of its current state. */
150 void unscheduleTickEvent()
152 if (tickEvent.scheduled())
156 class ActivateThreadEvent : public Event
159 /** Number of Thread to Activate */
162 /** Pointer to the CPU. */
163 FullO3CPU<Impl> *cpu;
166 /** Constructs the event. */
167 ActivateThreadEvent();
169 /** Initialize Event */
170 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
172 /** Processes the event, calling activateThread() on the CPU. */
175 /** Returns the description of the event. */
176 const char *description() const;
179 /** Schedule thread to activate , regardless of its current state. */
181 scheduleActivateThreadEvent(ThreadID tid, int delay)
183 // Schedule thread to activate, regardless of its current state.
184 if (activateThreadEvent[tid].squashed())
185 reschedule(activateThreadEvent[tid],
186 nextCycle(curTick() + ticks(delay)));
187 else if (!activateThreadEvent[tid].scheduled())
188 schedule(activateThreadEvent[tid],
189 nextCycle(curTick() + ticks(delay)));
192 /** Unschedule actiavte thread event, regardless of its current state. */
194 unscheduleActivateThreadEvent(ThreadID tid)
196 if (activateThreadEvent[tid].scheduled())
197 activateThreadEvent[tid].squash();
200 /** The tick event used for scheduling CPU ticks. */
201 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
203 class DeallocateContextEvent : public Event
206 /** Number of Thread to deactivate */
209 /** Should the thread be removed from the CPU? */
212 /** Pointer to the CPU. */
213 FullO3CPU<Impl> *cpu;
216 /** Constructs the event. */
217 DeallocateContextEvent();
219 /** Initialize Event */
220 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
222 /** Processes the event, calling activateThread() on the CPU. */
225 /** Sets whether the thread should also be removed from the CPU. */
226 void setRemove(bool _remove) { remove = _remove; }
228 /** Returns the description of the event. */
229 const char *description() const;
232 /** Schedule cpu to deallocate thread context.*/
234 scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay)
236 // Schedule thread to activate, regardless of its current state.
237 if (deallocateContextEvent[tid].squashed())
238 reschedule(deallocateContextEvent[tid],
239 nextCycle(curTick() + ticks(delay)));
240 else if (!deallocateContextEvent[tid].scheduled())
241 schedule(deallocateContextEvent[tid],
242 nextCycle(curTick() + ticks(delay)));
245 /** Unschedule thread deallocation in CPU */
247 unscheduleDeallocateContextEvent(ThreadID tid)
249 if (deallocateContextEvent[tid].scheduled())
250 deallocateContextEvent[tid].squash();
253 /** The tick event used for scheduling CPU ticks. */
254 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
257 /** Constructs a CPU with the given parameters. */
258 FullO3CPU(DerivO3CPUParams *params);
262 /** Registers statistics. */
265 void demapPage(Addr vaddr, uint64_t asn)
267 this->itb->demapPage(vaddr, asn);
268 this->dtb->demapPage(vaddr, asn);
271 void demapInstPage(Addr vaddr, uint64_t asn)
273 this->itb->demapPage(vaddr, asn);
276 void demapDataPage(Addr vaddr, uint64_t asn)
278 this->dtb->demapPage(vaddr, asn);
281 /** Returns a specific port. */
282 Port *getPort(const std::string &if_name, int idx);
284 /** Ticks CPU, calling tick() on each stage, and checking the overall
285 * activity to see if the CPU should deschedule itself.
289 /** Initialize the CPU */
292 /** Returns the Number of Active Threads in the CPU */
293 int numActiveThreads()
294 { return activeThreads.size(); }
296 /** Add Thread to Active Threads List */
297 void activateThread(ThreadID tid);
299 /** Remove Thread from Active Threads List */
300 void deactivateThread(ThreadID tid);
302 /** Setup CPU to insert a thread's context */
303 void insertThread(ThreadID tid);
305 /** Remove all of a thread's context from CPU */
306 void removeThread(ThreadID tid);
308 /** Count the Total Instructions Committed in the CPU. */
309 virtual Counter totalInstructions() const;
311 /** Add Thread to Active Threads List. */
312 void activateContext(ThreadID tid, int delay);
314 /** Remove Thread from Active Threads List */
315 void suspendContext(ThreadID tid);
317 /** Remove Thread from Active Threads List &&
318 * Possibly Remove Thread Context from CPU.
320 bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
322 /** Remove Thread from Active Threads List &&
323 * Remove Thread Context from CPU.
325 void haltContext(ThreadID tid);
327 /** Activate a Thread When CPU Resources are Available. */
328 void activateWhenReady(ThreadID tid);
330 /** Add or Remove a Thread Context in the CPU. */
331 void doContextSwitch();
333 /** Update The Order In Which We Process Threads. */
334 void updateThreadPriority();
336 /** Serialize state. */
337 virtual void serialize(std::ostream &os);
339 /** Unserialize from a checkpoint. */
340 virtual void unserialize(Checkpoint *cp, const std::string §ion);
344 /** Executes a syscall.
345 * @todo: Determine if this needs to be virtual.
347 void syscall(int64_t callnum, ThreadID tid);
350 /** Starts draining the CPU's pipeline of all instructions in
351 * order to stop all memory accesses. */
352 virtual unsigned int drain(Event *drain_event);
354 /** Resumes execution after a drain. */
355 virtual void resume();
357 /** Signals to this CPU that a stage has completed switching out. */
358 void signalDrained();
360 /** Switches out this CPU. */
361 virtual void switchOut();
363 /** Takes over from another CPU. */
364 virtual void takeOverFrom(BaseCPU *oldCPU);
366 /** Get the current instruction sequence number, and increment it. */
367 InstSeqNum getAndIncrementInstSeq()
368 { return globalSeqNum++; }
370 /** Traps to handle given fault. */
371 void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
374 /** HW return from error interrupt. */
375 Fault hwrei(ThreadID tid);
377 bool simPalCheck(int palFunc, ThreadID tid);
379 /** Returns the Fault for any valid interrupt. */
380 Fault getInterrupts();
382 /** Processes any an interrupt fault. */
383 void processInterrupts(Fault interrupt);
385 /** Halts the CPU. */
386 void halt() { panic("Halt not implemented!\n"); }
388 /** Update the Virt and Phys ports of all ThreadContexts to
389 * reflect change in memory connections. */
390 void updateMemPorts();
392 /** Check if this address is a valid instruction address. */
393 bool validInstAddr(Addr addr) { return true; }
395 /** Check if this address is a valid data address. */
396 bool validDataAddr(Addr addr) { return true; }
399 /** Register accessors. Index refers to the physical register index. */
401 /** Reads a miscellaneous register. */
402 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
404 /** Reads a misc. register, including any side effects the read
405 * might have as defined by the architecture.
407 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
409 /** Sets a miscellaneous register. */
410 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
413 /** Sets a misc. register, including any side effects the write
414 * might have as defined by the architecture.
416 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
419 uint64_t readIntReg(int reg_idx);
421 TheISA::FloatReg readFloatReg(int reg_idx);
423 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
425 void setIntReg(int reg_idx, uint64_t val);
427 void setFloatReg(int reg_idx, TheISA::FloatReg val);
429 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
431 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
433 float readArchFloatReg(int reg_idx, ThreadID tid);
435 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
437 /** Architectural register accessors. Looks up in the commit
438 * rename table to obtain the true physical index of the
439 * architected register first, then accesses that physical
442 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
444 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
446 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
448 /** Sets the commit PC state of a specific thread. */
449 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
451 /** Reads the commit PC state of a specific thread. */
452 TheISA::PCState pcState(ThreadID tid);
454 /** Reads the commit PC of a specific thread. */
455 Addr instAddr(ThreadID tid);
457 /** Reads the commit micro PC of a specific thread. */
458 MicroPC microPC(ThreadID tid);
460 /** Reads the next PC of a specific thread. */
461 Addr nextInstAddr(ThreadID tid);
463 /** Initiates a squash of all in-flight instructions for a given
464 * thread. The source of the squash is an external update of
465 * state through the TC.
467 void squashFromTC(ThreadID tid);
469 /** Function to add instruction onto the head of the list of the
470 * instructions. Used when new instructions are fetched.
472 ListIt addInst(DynInstPtr &inst);
474 /** Function to tell the CPU that an instruction has completed. */
475 void instDone(ThreadID tid);
477 /** Remove an instruction from the front end of the list. There's
478 * no restriction on location of the instruction.
480 void removeFrontInst(DynInstPtr &inst);
482 /** Remove all instructions that are not currently in the ROB.
483 * There's also an option to not squash delay slot instructions.*/
484 void removeInstsNotInROB(ThreadID tid);
486 /** Remove all instructions younger than the given sequence number. */
487 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
489 /** Removes the instruction pointed to by the iterator. */
490 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
492 /** Cleans up all instructions on the remove list. */
493 void cleanUpRemovedInsts();
495 /** Debug function to print all instructions on the list. */
500 /** Count of total number of dynamic instructions in flight. */
504 /** List of all the instructions in flight. */
505 std::list<DynInstPtr> instList;
507 /** List of all the instructions that will be removed at the end of this
510 std::queue<ListIt> removeList;
513 /** Debug structure to keep track of the sequence numbers still in
516 std::set<InstSeqNum> snList;
519 /** Records if instructions need to be removed this cycle due to
520 * being retired or squashed.
522 bool removeInstsThisCycle;
525 /** The fetch stage. */
526 typename CPUPolicy::Fetch fetch;
528 /** The decode stage. */
529 typename CPUPolicy::Decode decode;
531 /** The dispatch stage. */
532 typename CPUPolicy::Rename rename;
534 /** The issue/execute/writeback stages. */
535 typename CPUPolicy::IEW iew;
537 /** The commit stage. */
538 typename CPUPolicy::Commit commit;
540 /** The register file. */
541 typename CPUPolicy::RegFile regFile;
543 /** The free list. */
544 typename CPUPolicy::FreeList freeList;
546 /** The rename map. */
547 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
549 /** The commit rename map. */
550 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
552 /** The re-order buffer. */
553 typename CPUPolicy::ROB rob;
555 /** Active Threads List */
556 std::list<ThreadID> activeThreads;
558 /** Integer Register Scoreboard */
559 Scoreboard scoreboard;
561 TheISA::ISA isa[Impl::MaxThreads];
564 /** Enum to give each stage a specific index, so when calling
565 * activateStage() or deactivateStage(), they can specify which stage
566 * is being activated/deactivated.
576 /** Typedefs from the Impl to get the structs that each of the
577 * time buffers should use.
579 typedef typename CPUPolicy::TimeStruct TimeStruct;
581 typedef typename CPUPolicy::FetchStruct FetchStruct;
583 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
585 typedef typename CPUPolicy::RenameStruct RenameStruct;
587 typedef typename CPUPolicy::IEWStruct IEWStruct;
589 /** The main time buffer to do backwards communication. */
590 TimeBuffer<TimeStruct> timeBuffer;
592 /** The fetch stage's instruction queue. */
593 TimeBuffer<FetchStruct> fetchQueue;
595 /** The decode stage's instruction queue. */
596 TimeBuffer<DecodeStruct> decodeQueue;
598 /** The rename stage's instruction queue. */
599 TimeBuffer<RenameStruct> renameQueue;
601 /** The IEW stage's instruction queue. */
602 TimeBuffer<IEWStruct> iewQueue;
605 /** The activity recorder; used to tell if the CPU has any
606 * activity remaining or if it can go to idle and deschedule
609 ActivityRecorder activityRec;
612 /** Records that there was time buffer activity this cycle. */
613 void activityThisCycle() { activityRec.activity(); }
615 /** Changes a stage's status to active within the activity recorder. */
616 void activateStage(const StageIdx idx)
617 { activityRec.activateStage(idx); }
619 /** Changes a stage's status to inactive within the activity recorder. */
620 void deactivateStage(const StageIdx idx)
621 { activityRec.deactivateStage(idx); }
623 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
627 virtual void wakeup();
630 /** Gets a free thread id. Use if thread ids change across system. */
631 ThreadID getFreeTid();
634 /** Returns a pointer to a thread context. */
638 return thread[tid]->getTC();
641 /** The global sequence number counter. */
642 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
645 /** Pointer to the checker, which can dynamically verify
646 * instruction results at run time. This can be set to NULL if it
649 Checker<DynInstPtr> *checker;
652 /** Pointer to the system. */
655 /** Event to call process() on once draining has completed. */
658 /** Counter of how many stages have completed draining. */
661 /** Pointers to all of the threads in the CPU. */
662 std::vector<Thread *> thread;
664 /** Whether or not the CPU should defer its registration. */
665 bool deferRegistration;
667 /** Is there a context switch pending? */
670 /** Threads Scheduled to Enter CPU */
671 std::list<int> cpuWaitList;
673 /** The cycle that the CPU was last running, used for statistics. */
674 Tick lastRunningCycle;
676 /** The cycle that the CPU was last activated by a new thread*/
677 Tick lastActivatedCycle;
679 /** Mapping for system thread id to cpu id */
680 std::map<ThreadID, unsigned> threadMap;
682 /** Available thread ids in the cpu*/
683 std::vector<ThreadID> tids;
685 /** CPU read function, forwards read to LSQ. */
686 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
687 uint8_t *data, int load_idx)
689 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
693 /** CPU write function, forwards write to LSQ. */
694 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
695 uint8_t *data, int store_idx)
697 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
701 /** Get the dcache port (used to find block size for translations). */
702 Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); }
706 /** Temporary fix for the lock flag, works in the UP case. */
709 /** Stat for total number of times the CPU is descheduled. */
710 Stats::Scalar timesIdled;
711 /** Stat for total number of cycles the CPU spends descheduled. */
712 Stats::Scalar idleCycles;
713 /** Stat for the number of committed instructions per thread. */
714 Stats::Vector committedInsts;
715 /** Stat for the total number of committed instructions. */
716 Stats::Scalar totalCommittedInsts;
717 /** Stat for the CPI per thread. */
719 /** Stat for the total CPI. */
720 Stats::Formula totalCpi;
721 /** Stat for the IPC per thread. */
723 /** Stat for the total IPC. */
724 Stats::Formula totalIpc;
726 //number of integer register file accesses
727 Stats::Scalar intRegfileReads;
728 Stats::Scalar intRegfileWrites;
729 //number of float register file accesses
730 Stats::Scalar fpRegfileReads;
731 Stats::Scalar fpRegfileWrites;
733 Stats::Scalar miscRegfileReads;
734 Stats::Scalar miscRegfileWrites;
737 #endif // __CPU_O3_CPU_HH__