src/cpu/o3/cpu.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2011 Regents of the University of California
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Kevin Lim
  30  *          Korey Sewell
  31  *          Rick Strong
  32  */
  33
  34 #ifndef __CPU_O3_CPU_HH__
  35 #define __CPU_O3_CPU_HH__
  36
  37 #include <iostream>
  38 #include <list>
  39 #include <queue>
  40 #include <set>
  41 #include <vector>
  42
  43 #include "arch/types.hh"
  44 #include "base/statistics.hh"
  45 #include "config/full_system.hh"
  46 #include "config/the_isa.hh"
  47 #include "config/use_checker.hh"
  48 #include "cpu/o3/comm.hh"
  49 #include "cpu/o3/cpu_policy.hh"
  50 #include "cpu/o3/scoreboard.hh"
  51 #include "cpu/o3/thread_state.hh"
  52 #include "cpu/activity.hh"
  53 #include "cpu/base.hh"
  54 #include "cpu/simple_thread.hh"
  55 #include "cpu/timebuf.hh"
  56 //#include "cpu/o3/thread_context.hh"
  57 #include "params/DerivO3CPU.hh"
  58 #include "sim/process.hh"
  59
  60 template <class>
  61 class Checker;
  62 class ThreadContext;
  63 template <class>
  64 class O3ThreadContext;
  65
  66 class Checkpoint;
  67 class MemObject;
  68 class Process;
  69
  70 class BaseCPUParams;
  71
  72 class BaseO3CPU : public BaseCPU
  73 {
  74     //Stuff that's pretty ISA independent will go here.
  75   public:
  76     BaseO3CPU(BaseCPUParams *params);
  77
  78     void regStats();
  79 };
  80
  81 /**
  82  * FullO3CPU class, has each of the stages (fetch through commit)
  83  * within it, as well as all of the time buffers between stages.  The
  84  * tick() function for the CPU is defined here.
  85  */
  86 template <class Impl>
  87 class FullO3CPU : public BaseO3CPU
  88 {
  89   public:
  90     // Typedefs from the Impl here.
  91     typedef typename Impl::CPUPol CPUPolicy;
  92     typedef typename Impl::DynInstPtr DynInstPtr;
  93     typedef typename Impl::O3CPU O3CPU;
  94
  95     typedef O3ThreadState<Impl> ImplState;
  96     typedef O3ThreadState<Impl> Thread;
  97
  98     typedef typename std::list<DynInstPtr>::iterator ListIt;
  99
 100     friend class O3ThreadContext<Impl>;
 101
 102   public:
 103     enum Status {
 104         Running,
 105         Idle,
 106         Halted,
 107         Blocked,
 108         SwitchedOut
 109     };
 110
 111     TheISA::TLB * itb;
 112     TheISA::TLB * dtb;
 113
 114     /** Overall CPU status. */
 115     Status _status;
 116
 117     /** Per-thread status in CPU, used for SMT.  */
 118     Status _threadStatus[Impl::MaxThreads];
 119
 120   private:
 121     class TickEvent : public Event
 122     {
 123       private:
 124         /** Pointer to the CPU. */
 125         FullO3CPU<Impl> *cpu;
 126
 127       public:
 128         /** Constructs a tick event. */
 129         TickEvent(FullO3CPU<Impl> *c);
 130
 131         /** Processes a tick event, calling tick() on the CPU. */
 132         void process();
 133         /** Returns the description of the tick event. */
 134         const char *description() const;
 135     };
 136
 137     /** The tick event used for scheduling CPU ticks. */
 138     TickEvent tickEvent;
 139
 140     /** Schedule tick event, regardless of its current state. */
 141     void scheduleTickEvent(int delay)
 142     {
 143         if (tickEvent.squashed())
 144             reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
 145         else if (!tickEvent.scheduled())
 146             schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
 147     }
 148
 149     /** Unschedule tick event, regardless of its current state. */
 150     void unscheduleTickEvent()
 151     {
 152         if (tickEvent.scheduled())
 153             tickEvent.squash();
 154     }
 155
 156     class ActivateThreadEvent : public Event
 157     {
 158       private:
 159         /** Number of Thread to Activate */
 160         ThreadID tid;
 161
 162         /** Pointer to the CPU. */
 163         FullO3CPU<Impl> *cpu;
 164
 165       public:
 166         /** Constructs the event. */
 167         ActivateThreadEvent();
 168
 169         /** Initialize Event */
 170         void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
 171
 172         /** Processes the event, calling activateThread() on the CPU. */
 173         void process();
 174
 175         /** Returns the description of the event. */
 176         const char *description() const;
 177     };
 178
 179     /** Schedule thread to activate , regardless of its current state. */
 180     void
 181     scheduleActivateThreadEvent(ThreadID tid, int delay)
 182     {
 183         // Schedule thread to activate, regardless of its current state.
 184         if (activateThreadEvent[tid].squashed())
 185             reschedule(activateThreadEvent[tid],
 186                 nextCycle(curTick() + ticks(delay)));
 187         else if (!activateThreadEvent[tid].scheduled()) {
 188             Tick when = nextCycle(curTick() + ticks(delay));
 189
 190             // Check if the deallocateEvent is also scheduled, and make
 191             // sure they do not happen at same time causing a sleep that
 192             // is never woken from.
 193             if (deallocateContextEvent[tid].scheduled() &&
 194                 deallocateContextEvent[tid].when() == when) {
 195                 when++;
 196             }
 197
 198             schedule(activateThreadEvent[tid], when);
 199         }
 200     }
 201
 202     /** Unschedule actiavte thread event, regardless of its current state. */
 203     void
 204     unscheduleActivateThreadEvent(ThreadID tid)
 205     {
 206         if (activateThreadEvent[tid].scheduled())
 207             activateThreadEvent[tid].squash();
 208     }
 209
 210     /** The tick event used for scheduling CPU ticks. */
 211     ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
 212
 213     class DeallocateContextEvent : public Event
 214     {
 215       private:
 216         /** Number of Thread to deactivate */
 217         ThreadID tid;
 218
 219         /** Should the thread be removed from the CPU? */
 220         bool remove;
 221
 222         /** Pointer to the CPU. */
 223         FullO3CPU<Impl> *cpu;
 224
 225       public:
 226         /** Constructs the event. */
 227         DeallocateContextEvent();
 228
 229         /** Initialize Event */
 230         void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
 231
 232         /** Processes the event, calling activateThread() on the CPU. */
 233         void process();
 234
 235         /** Sets whether the thread should also be removed from the CPU. */
 236         void setRemove(bool _remove) { remove = _remove; }
 237
 238         /** Returns the description of the event. */
 239         const char *description() const;
 240     };
 241
 242     /** Schedule cpu to deallocate thread context.*/
 243     void
 244     scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay)
 245     {
 246         // Schedule thread to activate, regardless of its current state.
 247         if (deallocateContextEvent[tid].squashed())
 248             reschedule(deallocateContextEvent[tid],
 249                 nextCycle(curTick() + ticks(delay)));
 250         else if (!deallocateContextEvent[tid].scheduled())
 251             schedule(deallocateContextEvent[tid],
 252                 nextCycle(curTick() + ticks(delay)));
 253     }
 254
 255     /** Unschedule thread deallocation in CPU */
 256     void
 257     unscheduleDeallocateContextEvent(ThreadID tid)
 258     {
 259         if (deallocateContextEvent[tid].scheduled())
 260             deallocateContextEvent[tid].squash();
 261     }
 262
 263     /** The tick event used for scheduling CPU ticks. */
 264     DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
 265
 266   public:
 267     /** Constructs a CPU with the given parameters. */
 268     FullO3CPU(DerivO3CPUParams *params);
 269     /** Destructor. */
 270     ~FullO3CPU();
 271
 272     /** Registers statistics. */
 273     void regStats();
 274
 275     void demapPage(Addr vaddr, uint64_t asn)
 276     {
 277         this->itb->demapPage(vaddr, asn);
 278         this->dtb->demapPage(vaddr, asn);
 279     }
 280
 281     void demapInstPage(Addr vaddr, uint64_t asn)
 282     {
 283         this->itb->demapPage(vaddr, asn);
 284     }
 285
 286     void demapDataPage(Addr vaddr, uint64_t asn)
 287     {
 288         this->dtb->demapPage(vaddr, asn);
 289     }
 290
 291     /** Returns a specific port. */
 292     Port *getPort(const std::string &if_name, int idx);
 293
 294     /** Ticks CPU, calling tick() on each stage, and checking the overall
 295      *  activity to see if the CPU should deschedule itself.
 296      */
 297     void tick();
 298
 299     /** Initialize the CPU */
 300     void init();
 301
 302     /** Returns the Number of Active Threads in the CPU */
 303     int numActiveThreads()
 304     { return activeThreads.size(); }
 305
 306     /** Add Thread to Active Threads List */
 307     void activateThread(ThreadID tid);
 308
 309     /** Remove Thread from Active Threads List */
 310     void deactivateThread(ThreadID tid);
 311
 312     /** Setup CPU to insert a thread's context */
 313     void insertThread(ThreadID tid);
 314
 315     /** Remove all of a thread's context from CPU */
 316     void removeThread(ThreadID tid);
 317
 318     /** Count the Total Instructions Committed in the CPU. */
 319     virtual Counter totalInstructions() const;
 320
 321     /** Add Thread to Active Threads List. */
 322     void activateContext(ThreadID tid, int delay);
 323
 324     /** Remove Thread from Active Threads List */
 325     void suspendContext(ThreadID tid);
 326
 327     /** Remove Thread from Active Threads List &&
 328      *  Possibly Remove Thread Context from CPU.
 329      */
 330     bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
 331
 332     /** Remove Thread from Active Threads List &&
 333      *  Remove Thread Context from CPU.
 334      */
 335     void haltContext(ThreadID tid);
 336
 337     /** Activate a Thread When CPU Resources are Available. */
 338     void activateWhenReady(ThreadID tid);
 339
 340     /** Add or Remove a Thread Context in the CPU. */
 341     void doContextSwitch();
 342
 343     /** Update The Order In Which We Process Threads. */
 344     void updateThreadPriority();
 345
 346     /** Serialize state. */
 347     virtual void serialize(std::ostream &os);
 348
 349     /** Unserialize from a checkpoint. */
 350     virtual void unserialize(Checkpoint *cp, const std::string &section);
 351
 352   public:
 353     /** Executes a syscall.
 354      * @todo: Determine if this needs to be virtual.
 355      */
 356     void syscall(int64_t callnum, ThreadID tid);
 357
 358     /** Starts draining the CPU's pipeline of all instructions in
 359      * order to stop all memory accesses. */
 360     virtual unsigned int drain(Event *drain_event);
 361
 362     /** Resumes execution after a drain. */
 363     virtual void resume();
 364
 365     /** Signals to this CPU that a stage has completed switching out. */
 366     void signalDrained();
 367
 368     /** Switches out this CPU. */
 369     virtual void switchOut();
 370
 371     /** Takes over from another CPU. */
 372     virtual void takeOverFrom(BaseCPU *oldCPU);
 373
 374     /** Get the current instruction sequence number, and increment it. */
 375     InstSeqNum getAndIncrementInstSeq()
 376     { return globalSeqNum++; }
 377
 378     /** Traps to handle given fault. */
 379     void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
 380
 381 #if FULL_SYSTEM
 382     /** HW return from error interrupt. */
 383     Fault hwrei(ThreadID tid);
 384
 385     bool simPalCheck(int palFunc, ThreadID tid);
 386
 387     /** Returns the Fault for any valid interrupt. */
 388     Fault getInterrupts();
 389
 390     /** Processes any an interrupt fault. */
 391     void processInterrupts(Fault interrupt);
 392
 393     /** Halts the CPU. */
 394     void halt() { panic("Halt not implemented!\n"); }
 395
 396     /** Update the Virt and Phys ports of all ThreadContexts to
 397      * reflect change in memory connections. */
 398     void updateMemPorts();
 399
 400     /** Check if this address is a valid instruction address. */
 401     bool validInstAddr(Addr addr) { return true; }
 402
 403     /** Check if this address is a valid data address. */
 404     bool validDataAddr(Addr addr) { return true; }
 405 #endif
 406
 407     /** Register accessors.  Index refers to the physical register index. */
 408
 409     /** Reads a miscellaneous register. */
 410     TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
 411
 412     /** Reads a misc. register, including any side effects the read
 413      * might have as defined by the architecture.
 414      */
 415     TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
 416
 417     /** Sets a miscellaneous register. */
 418     void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
 419             ThreadID tid);
 420
 421     /** Sets a misc. register, including any side effects the write
 422      * might have as defined by the architecture.
 423      */
 424     void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
 425             ThreadID tid);
 426
 427     uint64_t readIntReg(int reg_idx);
 428
 429     TheISA::FloatReg readFloatReg(int reg_idx);
 430
 431     TheISA::FloatRegBits readFloatRegBits(int reg_idx);
 432
 433     void setIntReg(int reg_idx, uint64_t val);
 434
 435     void setFloatReg(int reg_idx, TheISA::FloatReg val);
 436
 437     void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
 438
 439     uint64_t readArchIntReg(int reg_idx, ThreadID tid);
 440
 441     float readArchFloatReg(int reg_idx, ThreadID tid);
 442
 443     uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
 444
 445     /** Architectural register accessors.  Looks up in the commit
 446      * rename table to obtain the true physical index of the
 447      * architected register first, then accesses that physical
 448      * register.
 449      */
 450     void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
 451
 452     void setArchFloatReg(int reg_idx, float val, ThreadID tid);
 453
 454     void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
 455
 456     /** Sets the commit PC state of a specific thread. */
 457     void pcState(const TheISA::PCState &newPCState, ThreadID tid);
 458
 459     /** Reads the commit PC state of a specific thread. */
 460     TheISA::PCState pcState(ThreadID tid);
 461
 462     /** Reads the commit PC of a specific thread. */
 463     Addr instAddr(ThreadID tid);
 464
 465     /** Reads the commit micro PC of a specific thread. */
 466     MicroPC microPC(ThreadID tid);
 467
 468     /** Reads the next PC of a specific thread. */
 469     Addr nextInstAddr(ThreadID tid);
 470
 471     /** Initiates a squash of all in-flight instructions for a given
 472      * thread.  The source of the squash is an external update of
 473      * state through the TC.
 474      */
 475     void squashFromTC(ThreadID tid);
 476
 477     /** Function to add instruction onto the head of the list of the
 478      *  instructions.  Used when new instructions are fetched.
 479      */
 480     ListIt addInst(DynInstPtr &inst);
 481
 482     /** Function to tell the CPU that an instruction has completed. */
 483     void instDone(ThreadID tid);
 484
 485     /** Remove an instruction from the front end of the list.  There's
 486      *  no restriction on location of the instruction.
 487      */
 488     void removeFrontInst(DynInstPtr &inst);
 489
 490     /** Remove all instructions that are not currently in the ROB.
 491      *  There's also an option to not squash delay slot instructions.*/
 492     void removeInstsNotInROB(ThreadID tid);
 493
 494     /** Remove all instructions younger than the given sequence number. */
 495     void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
 496
 497     /** Removes the instruction pointed to by the iterator. */
 498     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 499
 500     /** Cleans up all instructions on the remove list. */
 501     void cleanUpRemovedInsts();
 502
 503     /** Debug function to print all instructions on the list. */
 504     void dumpInsts();
 505
 506   public:
 507 #ifndef NDEBUG
 508     /** Count of total number of dynamic instructions in flight. */
 509     int instcount;
 510 #endif
 511
 512     /** List of all the instructions in flight. */
 513     std::list<DynInstPtr> instList;
 514
 515     /** List of all the instructions that will be removed at the end of this
 516      *  cycle.
 517      */
 518     std::queue<ListIt> removeList;
 519
 520 #ifdef DEBUG
 521     /** Debug structure to keep track of the sequence numbers still in
 522      * flight.
 523      */
 524     std::set<InstSeqNum> snList;
 525 #endif
 526
 527     /** Records if instructions need to be removed this cycle due to
 528      *  being retired or squashed.
 529      */
 530     bool removeInstsThisCycle;
 531
 532   protected:
 533     /** The fetch stage. */
 534     typename CPUPolicy::Fetch fetch;
 535
 536     /** The decode stage. */
 537     typename CPUPolicy::Decode decode;
 538
 539     /** The dispatch stage. */
 540     typename CPUPolicy::Rename rename;
 541
 542     /** The issue/execute/writeback stages. */
 543     typename CPUPolicy::IEW iew;
 544
 545     /** The commit stage. */
 546     typename CPUPolicy::Commit commit;
 547
 548     /** The register file. */
 549     typename CPUPolicy::RegFile regFile;
 550
 551     /** The free list. */
 552     typename CPUPolicy::FreeList freeList;
 553
 554     /** The rename map. */
 555     typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
 556
 557     /** The commit rename map. */
 558     typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
 559
 560     /** The re-order buffer. */
 561     typename CPUPolicy::ROB rob;
 562
 563     /** Active Threads List */
 564     std::list<ThreadID> activeThreads;
 565
 566     /** Integer Register Scoreboard */
 567     Scoreboard scoreboard;
 568
 569     TheISA::ISA isa[Impl::MaxThreads];
 570
 571   public:
 572     /** Enum to give each stage a specific index, so when calling
 573      *  activateStage() or deactivateStage(), they can specify which stage
 574      *  is being activated/deactivated.
 575      */
 576     enum StageIdx {
 577         FetchIdx,
 578         DecodeIdx,
 579         RenameIdx,
 580         IEWIdx,
 581         CommitIdx,
 582         NumStages };
 583
 584     /** Typedefs from the Impl to get the structs that each of the
 585      *  time buffers should use.
 586      */
 587     typedef typename CPUPolicy::TimeStruct TimeStruct;
 588
 589     typedef typename CPUPolicy::FetchStruct FetchStruct;
 590
 591     typedef typename CPUPolicy::DecodeStruct DecodeStruct;
 592
 593     typedef typename CPUPolicy::RenameStruct RenameStruct;
 594
 595     typedef typename CPUPolicy::IEWStruct IEWStruct;
 596
 597     /** The main time buffer to do backwards communication. */
 598     TimeBuffer<TimeStruct> timeBuffer;
 599
 600     /** The fetch stage's instruction queue. */
 601     TimeBuffer<FetchStruct> fetchQueue;
 602
 603     /** The decode stage's instruction queue. */
 604     TimeBuffer<DecodeStruct> decodeQueue;
 605
 606     /** The rename stage's instruction queue. */
 607     TimeBuffer<RenameStruct> renameQueue;
 608
 609     /** The IEW stage's instruction queue. */
 610     TimeBuffer<IEWStruct> iewQueue;
 611
 612   private:
 613     /** The activity recorder; used to tell if the CPU has any
 614      * activity remaining or if it can go to idle and deschedule
 615      * itself.
 616      */
 617     ActivityRecorder activityRec;
 618
 619   public:
 620     /** Records that there was time buffer activity this cycle. */
 621     void activityThisCycle() { activityRec.activity(); }
 622
 623     /** Changes a stage's status to active within the activity recorder. */
 624     void activateStage(const StageIdx idx)
 625     { activityRec.activateStage(idx); }
 626
 627     /** Changes a stage's status to inactive within the activity recorder. */
 628     void deactivateStage(const StageIdx idx)
 629     { activityRec.deactivateStage(idx); }
 630
 631     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 632     void wakeCPU();
 633
 634 #if FULL_SYSTEM
 635     virtual void wakeup();
 636 #endif
 637
 638     /** Gets a free thread id. Use if thread ids change across system. */
 639     ThreadID getFreeTid();
 640
 641   public:
 642     /** Returns a pointer to a thread context. */
 643     ThreadContext *
 644     tcBase(ThreadID tid)
 645     {
 646         return thread[tid]->getTC();
 647     }
 648
 649     /** The global sequence number counter. */
 650     InstSeqNum globalSeqNum;//[Impl::MaxThreads];
 651
 652 #if USE_CHECKER
 653     /** Pointer to the checker, which can dynamically verify
 654      * instruction results at run time.  This can be set to NULL if it
 655      * is not being used.
 656      */
 657     Checker<DynInstPtr> *checker;
 658 #endif
 659
 660     /** Pointer to the system. */
 661     System *system;
 662
 663     /** Event to call process() on once draining has completed. */
 664     Event *drainEvent;
 665
 666     /** Counter of how many stages have completed draining. */
 667     int drainCount;
 668
 669     /** Pointers to all of the threads in the CPU. */
 670     std::vector<Thread *> thread;
 671
 672     /** Whether or not the CPU should defer its registration. */
 673     bool deferRegistration;
 674
 675     /** Is there a context switch pending? */
 676     bool contextSwitch;
 677
 678     /** Threads Scheduled to Enter CPU */
 679     std::list<int> cpuWaitList;
 680
 681     /** The cycle that the CPU was last running, used for statistics. */
 682     Tick lastRunningCycle;
 683
 684     /** The cycle that the CPU was last activated by a new thread*/
 685     Tick lastActivatedCycle;
 686
 687     /** Mapping for system thread id to cpu id */
 688     std::map<ThreadID, unsigned> threadMap;
 689
 690     /** Available thread ids in the cpu*/
 691     std::vector<ThreadID> tids;
 692
 693     /** CPU read function, forwards read to LSQ. */
 694     Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
 695                uint8_t *data, int load_idx)
 696     {
 697         return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
 698                                         data, load_idx);
 699     }
 700
 701     /** CPU write function, forwards write to LSQ. */
 702     Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
 703                 uint8_t *data, int store_idx)
 704     {
 705         return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
 706                                          data, store_idx);
 707     }
 708
 709     /** Get the dcache port (used to find block size for translations). */
 710     Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); }
 711
 712     Addr lockAddr;
 713
 714     /** Temporary fix for the lock flag, works in the UP case. */
 715     bool lockFlag;
 716
 717     /** Stat for total number of times the CPU is descheduled. */
 718     Stats::Scalar timesIdled;
 719     /** Stat for total number of cycles the CPU spends descheduled. */
 720     Stats::Scalar idleCycles;
 721     /** Stat for the number of committed instructions per thread. */
 722     Stats::Vector committedInsts;
 723     /** Stat for the total number of committed instructions. */
 724     Stats::Scalar totalCommittedInsts;
 725     /** Stat for the CPI per thread. */
 726     Stats::Formula cpi;
 727     /** Stat for the total CPI. */
 728     Stats::Formula totalCpi;
 729     /** Stat for the IPC per thread. */
 730     Stats::Formula ipc;
 731     /** Stat for the total IPC. */
 732     Stats::Formula totalIpc;
 733
 734     //number of integer register file accesses
 735     Stats::Scalar intRegfileReads;
 736     Stats::Scalar intRegfileWrites;
 737     //number of float register file accesses
 738     Stats::Scalar fpRegfileReads;
 739     Stats::Scalar fpRegfileWrites;
 740     //number of misc
 741     Stats::Scalar miscRegfileReads;
 742     Stats::Scalar miscRegfileWrites;
 743 };
 744
 745 #endif // __CPU_O3_CPU_HH__