src/cpu/o3/cpu.hh

   1 /*
   2  * Copyright (c) 2011-2013, 2016 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2004-2005 The Regents of The University of Michigan
  16  * Copyright (c) 2011 Regents of the University of California
  17  * All rights reserved.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are
  21  * met: redistributions of source code must retain the above copyright
  22  * notice, this list of conditions and the following disclaimer;
  23  * redistributions in binary form must reproduce the above copyright
  24  * notice, this list of conditions and the following disclaimer in the
  25  * documentation and/or other materials provided with the distribution;
  26  * neither the name of the copyright holders nor the names of its
  27  * contributors may be used to endorse or promote products derived from
  28  * this software without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  31  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  32  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  33  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  34  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  35  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  36  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  37  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  38  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  39  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  40  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  41  *
  42  * Authors: Kevin Lim
  43  *          Korey Sewell
  44  *          Rick Strong
  45  */
  46
  47 #ifndef __CPU_O3_CPU_HH__
  48 #define __CPU_O3_CPU_HH__
  49
  50 #include <iostream>
  51 #include <list>
  52 #include <queue>
  53 #include <set>
  54 #include <vector>
  55
  56 #include "arch/generic/types.hh"
  57 #include "arch/types.hh"
  58 #include "base/statistics.hh"
  59 #include "config/the_isa.hh"
  60 #include "cpu/o3/comm.hh"
  61 #include "cpu/o3/cpu_policy.hh"
  62 #include "cpu/o3/scoreboard.hh"
  63 #include "cpu/o3/thread_state.hh"
  64 #include "cpu/activity.hh"
  65 #include "cpu/base.hh"
  66 #include "cpu/simple_thread.hh"
  67 #include "cpu/timebuf.hh"
  68 //#include "cpu/o3/thread_context.hh"
  69 #include "params/DerivO3CPU.hh"
  70 #include "sim/process.hh"
  71
  72 template <class>
  73 class Checker;
  74 class ThreadContext;
  75 template <class>
  76 class O3ThreadContext;
  77
  78 class Checkpoint;
  79 class MemObject;
  80 class Process;
  81
  82 struct BaseCPUParams;
  83
  84 class BaseO3CPU : public BaseCPU
  85 {
  86     //Stuff that's pretty ISA independent will go here.
  87   public:
  88     BaseO3CPU(BaseCPUParams *params);
  89
  90     void regStats();
  91 };
  92
  93 /**
  94  * FullO3CPU class, has each of the stages (fetch through commit)
  95  * within it, as well as all of the time buffers between stages.  The
  96  * tick() function for the CPU is defined here.
  97  */
  98 template <class Impl>
  99 class FullO3CPU : public BaseO3CPU
 100 {
 101   public:
 102     // Typedefs from the Impl here.
 103     typedef typename Impl::CPUPol CPUPolicy;
 104     typedef typename Impl::DynInstPtr DynInstPtr;
 105     typedef typename Impl::O3CPU O3CPU;
 106
 107     using VecElem =  TheISA::VecElem;
 108     using VecRegContainer =  TheISA::VecRegContainer;
 109
 110     typedef O3ThreadState<Impl> ImplState;
 111     typedef O3ThreadState<Impl> Thread;
 112
 113     typedef typename std::list<DynInstPtr>::iterator ListIt;
 114
 115     friend class O3ThreadContext<Impl>;
 116
 117   public:
 118     enum Status {
 119         Running,
 120         Idle,
 121         Halted,
 122         Blocked,
 123         SwitchedOut
 124     };
 125
 126     TheISA::TLB * itb;
 127     TheISA::TLB * dtb;
 128
 129     /** Overall CPU status. */
 130     Status _status;
 131
 132   private:
 133
 134     /**
 135      * IcachePort class for instruction fetch.
 136      */
 137     class IcachePort : public MasterPort
 138     {
 139       protected:
 140         /** Pointer to fetch. */
 141         DefaultFetch<Impl> *fetch;
 142
 143       public:
 144         /** Default constructor. */
 145         IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
 146             : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
 147         { }
 148
 149       protected:
 150
 151         /** Timing version of receive.  Handles setting fetch to the
 152          * proper status to start fetching. */
 153         virtual bool recvTimingResp(PacketPtr pkt);
 154
 155         /** Handles doing a retry of a failed fetch. */
 156         virtual void recvReqRetry();
 157     };
 158
 159     /**
 160      * DcachePort class for the load/store queue.
 161      */
 162     class DcachePort : public MasterPort
 163     {
 164       protected:
 165
 166         /** Pointer to LSQ. */
 167         LSQ<Impl> *lsq;
 168         FullO3CPU<Impl> *cpu;
 169
 170       public:
 171         /** Default constructor. */
 172         DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
 173             : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq),
 174               cpu(_cpu)
 175         { }
 176
 177       protected:
 178
 179         /** Timing version of receive.  Handles writing back and
 180          * completing the load or store that has returned from
 181          * memory. */
 182         virtual bool recvTimingResp(PacketPtr pkt);
 183         virtual void recvTimingSnoopReq(PacketPtr pkt);
 184
 185         virtual void recvFunctionalSnoop(PacketPtr pkt)
 186         {
 187             // @todo: Is there a need for potential invalidation here?
 188         }
 189
 190         /** Handles doing a retry of the previous send. */
 191         virtual void recvReqRetry();
 192
 193         /**
 194          * As this CPU requires snooping to maintain the load store queue
 195          * change the behaviour from the base CPU port.
 196          *
 197          * @return true since we have to snoop
 198          */
 199         virtual bool isSnooping() const { return true; }
 200     };
 201
 202     /** The tick event used for scheduling CPU ticks. */
 203     EventFunctionWrapper tickEvent;
 204
 205     /** Schedule tick event, regardless of its current state. */
 206     void scheduleTickEvent(Cycles delay)
 207     {
 208         if (tickEvent.squashed())
 209             reschedule(tickEvent, clockEdge(delay));
 210         else if (!tickEvent.scheduled())
 211             schedule(tickEvent, clockEdge(delay));
 212     }
 213
 214     /** Unschedule tick event, regardless of its current state. */
 215     void unscheduleTickEvent()
 216     {
 217         if (tickEvent.scheduled())
 218             tickEvent.squash();
 219     }
 220
 221     /**
 222      * Check if the pipeline has drained and signal drain done.
 223      *
 224      * This method checks if a drain has been requested and if the CPU
 225      * has drained successfully (i.e., there are no instructions in
 226      * the pipeline). If the CPU has drained, it deschedules the tick
 227      * event and signals the drain manager.
 228      *
 229      * @return False if a drain hasn't been requested or the CPU
 230      * hasn't drained, true otherwise.
 231      */
 232     bool tryDrain();
 233
 234     /**
 235      * Perform sanity checks after a drain.
 236      *
 237      * This method is called from drain() when it has determined that
 238      * the CPU is fully drained when gem5 is compiled with the NDEBUG
 239      * macro undefined. The intention of this method is to do more
 240      * extensive tests than the isDrained() method to weed out any
 241      * draining bugs.
 242      */
 243     void drainSanityCheck() const;
 244
 245     /** Check if a system is in a drained state. */
 246     bool isDrained() const;
 247
 248   public:
 249     /** Constructs a CPU with the given parameters. */
 250     FullO3CPU(DerivO3CPUParams *params);
 251     /** Destructor. */
 252     ~FullO3CPU();
 253
 254     /** Registers statistics. */
 255     void regStats() override;
 256
 257     ProbePointArg<PacketPtr> *ppInstAccessComplete;
 258     ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
 259
 260     /** Register probe points. */
 261     void regProbePoints() override;
 262
 263     void demapPage(Addr vaddr, uint64_t asn)
 264     {
 265         this->itb->demapPage(vaddr, asn);
 266         this->dtb->demapPage(vaddr, asn);
 267     }
 268
 269     void demapInstPage(Addr vaddr, uint64_t asn)
 270     {
 271         this->itb->demapPage(vaddr, asn);
 272     }
 273
 274     void demapDataPage(Addr vaddr, uint64_t asn)
 275     {
 276         this->dtb->demapPage(vaddr, asn);
 277     }
 278
 279     /** Ticks CPU, calling tick() on each stage, and checking the overall
 280      *  activity to see if the CPU should deschedule itself.
 281      */
 282     void tick();
 283
 284     /** Initialize the CPU */
 285     void init() override;
 286
 287     void startup() override;
 288
 289     /** Returns the Number of Active Threads in the CPU */
 290     int numActiveThreads()
 291     { return activeThreads.size(); }
 292
 293     /** Add Thread to Active Threads List */
 294     void activateThread(ThreadID tid);
 295
 296     /** Remove Thread from Active Threads List */
 297     void deactivateThread(ThreadID tid);
 298
 299     /** Setup CPU to insert a thread's context */
 300     void insertThread(ThreadID tid);
 301
 302     /** Remove all of a thread's context from CPU */
 303     void removeThread(ThreadID tid);
 304
 305     /** Count the Total Instructions Committed in the CPU. */
 306     Counter totalInsts() const override;
 307
 308     /** Count the Total Ops (including micro ops) committed in the CPU. */
 309     Counter totalOps() const override;
 310
 311     /** Add Thread to Active Threads List. */
 312     void activateContext(ThreadID tid) override;
 313
 314     /** Remove Thread from Active Threads List */
 315     void suspendContext(ThreadID tid) override;
 316
 317     /** Remove Thread from Active Threads List &&
 318      *  Remove Thread Context from CPU.
 319      */
 320     void haltContext(ThreadID tid) override;
 321
 322     /** Update The Order In Which We Process Threads. */
 323     void updateThreadPriority();
 324
 325     /** Is the CPU draining? */
 326     bool isDraining() const { return drainState() == DrainState::Draining; }
 327
 328     void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
 329     void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
 330
 331   public:
 332     /** Executes a syscall.
 333      * @todo: Determine if this needs to be virtual.
 334      */
 335     void syscall(int64_t callnum, ThreadID tid, Fault *fault);
 336
 337     /** Starts draining the CPU's pipeline of all instructions in
 338      * order to stop all memory accesses. */
 339     DrainState drain() override;
 340
 341     /** Resumes execution after a drain. */
 342     void drainResume() override;
 343
 344     /**
 345      * Commit has reached a safe point to drain a thread.
 346      *
 347      * Commit calls this method to inform the pipeline that it has
 348      * reached a point where it is not executed microcode and is about
 349      * to squash uncommitted instructions to fully drain the pipeline.
 350      */
 351     void commitDrained(ThreadID tid);
 352
 353     /** Switches out this CPU. */
 354     void switchOut() override;
 355
 356     /** Takes over from another CPU. */
 357     void takeOverFrom(BaseCPU *oldCPU) override;
 358
 359     void verifyMemoryMode() const override;
 360
 361     /** Get the current instruction sequence number, and increment it. */
 362     InstSeqNum getAndIncrementInstSeq()
 363     { return globalSeqNum++; }
 364
 365     /** Traps to handle given fault. */
 366     void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
 367
 368     /** HW return from error interrupt. */
 369     Fault hwrei(ThreadID tid);
 370
 371     bool simPalCheck(int palFunc, ThreadID tid);
 372
 373     /** Returns the Fault for any valid interrupt. */
 374     Fault getInterrupts();
 375
 376     /** Processes any an interrupt fault. */
 377     void processInterrupts(const Fault &interrupt);
 378
 379     /** Halts the CPU. */
 380     void halt() { panic("Halt not implemented!\n"); }
 381
 382     /** Register accessors.  Index refers to the physical register index. */
 383
 384     /** Reads a miscellaneous register. */
 385     TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
 386
 387     /** Reads a misc. register, including any side effects the read
 388      * might have as defined by the architecture.
 389      */
 390     TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
 391
 392     /** Sets a miscellaneous register. */
 393     void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
 394             ThreadID tid);
 395
 396     /** Sets a misc. register, including any side effects the write
 397      * might have as defined by the architecture.
 398      */
 399     void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
 400             ThreadID tid);
 401
 402     uint64_t readIntReg(PhysRegIdPtr phys_reg);
 403
 404     TheISA::FloatReg readFloatReg(PhysRegIdPtr phys_reg);
 405
 406     TheISA::FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg);
 407
 408     const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
 409
 410     /**
 411      * Read physical vector register for modification.
 412      */
 413     VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
 414
 415     /**
 416      * Read physical vector register lane
 417      */
 418     template<typename VecElem, int LaneIdx>
 419     VecLaneT<VecElem, true>
 420     readVecLane(PhysRegIdPtr phys_reg) const
 421     {
 422         vecRegfileReads++;
 423         return regFile.readVecLane<VecElem, LaneIdx>(phys_reg);
 424     }
 425
 426     /**
 427      * Read physical vector register lane
 428      */
 429     template<typename VecElem>
 430     VecLaneT<VecElem, true>
 431     readVecLane(PhysRegIdPtr phys_reg) const
 432     {
 433         vecRegfileReads++;
 434         return regFile.readVecLane<VecElem>(phys_reg);
 435     }
 436
 437     /** Write a lane of the destination vector register. */
 438     template<typename LD>
 439     void
 440     setVecLane(PhysRegIdPtr phys_reg, const LD& val)
 441     {
 442         vecRegfileWrites++;
 443         return regFile.setVecLane(phys_reg, val);
 444     }
 445
 446     const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
 447
 448     TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);
 449
 450     void setIntReg(PhysRegIdPtr phys_reg, uint64_t val);
 451
 452     void setFloatReg(PhysRegIdPtr phys_reg, TheISA::FloatReg val);
 453
 454     void setFloatRegBits(PhysRegIdPtr phys_reg, TheISA::FloatRegBits val);
 455
 456     void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
 457
 458     void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);
 459
 460     void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);
 461
 462     uint64_t readArchIntReg(int reg_idx, ThreadID tid);
 463
 464     float readArchFloatReg(int reg_idx, ThreadID tid);
 465
 466     uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
 467
 468     const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
 469     /** Read architectural vector register for modification. */
 470     VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
 471
 472     /** Read architectural vector register lane. */
 473     template<typename VecElem>
 474     VecLaneT<VecElem, true>
 475     readArchVecLane(int reg_idx, int lId, ThreadID tid) const
 476     {
 477         PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
 478                     RegId(VecRegClass, reg_idx));
 479         return readVecLane<VecElem>(phys_reg);
 480     }
 481
 482
 483     /** Write a lane of the destination vector register. */
 484     template<typename LD>
 485     void
 486     setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val)
 487     {
 488         PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
 489                     RegId(VecRegClass, reg_idx));
 490         setVecLane(phys_reg, val);
 491     }
 492
 493     const VecElem& readArchVecElem(const RegIndex& reg_idx,
 494                                    const ElemIndex& ldx, ThreadID tid) const;
 495
 496     TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
 497
 498     /** Architectural register accessors.  Looks up in the commit
 499      * rename table to obtain the true physical index of the
 500      * architected register first, then accesses that physical
 501      * register.
 502      */
 503     void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
 504
 505     void setArchFloatReg(int reg_idx, float val, ThreadID tid);
 506
 507     void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
 508
 509     void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
 510
 511     void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
 512                         const VecElem& val, ThreadID tid);
 513
 514     void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
 515
 516     /** Sets the commit PC state of a specific thread. */
 517     void pcState(const TheISA::PCState &newPCState, ThreadID tid);
 518
 519     /** Reads the commit PC state of a specific thread. */
 520     TheISA::PCState pcState(ThreadID tid);
 521
 522     /** Reads the commit PC of a specific thread. */
 523     Addr instAddr(ThreadID tid);
 524
 525     /** Reads the commit micro PC of a specific thread. */
 526     MicroPC microPC(ThreadID tid);
 527
 528     /** Reads the next PC of a specific thread. */
 529     Addr nextInstAddr(ThreadID tid);
 530
 531     /** Initiates a squash of all in-flight instructions for a given
 532      * thread.  The source of the squash is an external update of
 533      * state through the TC.
 534      */
 535     void squashFromTC(ThreadID tid);
 536
 537     /** Function to add instruction onto the head of the list of the
 538      *  instructions.  Used when new instructions are fetched.
 539      */
 540     ListIt addInst(DynInstPtr &inst);
 541
 542     /** Function to tell the CPU that an instruction has completed. */
 543     void instDone(ThreadID tid, DynInstPtr &inst);
 544
 545     /** Remove an instruction from the front end of the list.  There's
 546      *  no restriction on location of the instruction.
 547      */
 548     void removeFrontInst(DynInstPtr &inst);
 549
 550     /** Remove all instructions that are not currently in the ROB.
 551      *  There's also an option to not squash delay slot instructions.*/
 552     void removeInstsNotInROB(ThreadID tid);
 553
 554     /** Remove all instructions younger than the given sequence number. */
 555     void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
 556
 557     /** Removes the instruction pointed to by the iterator. */
 558     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 559
 560     /** Cleans up all instructions on the remove list. */
 561     void cleanUpRemovedInsts();
 562
 563     /** Debug function to print all instructions on the list. */
 564     void dumpInsts();
 565
 566   public:
 567 #ifndef NDEBUG
 568     /** Count of total number of dynamic instructions in flight. */
 569     int instcount;
 570 #endif
 571
 572     /** List of all the instructions in flight. */
 573     std::list<DynInstPtr> instList;
 574
 575     /** List of all the instructions that will be removed at the end of this
 576      *  cycle.
 577      */
 578     std::queue<ListIt> removeList;
 579
 580 #ifdef DEBUG
 581     /** Debug structure to keep track of the sequence numbers still in
 582      * flight.
 583      */
 584     std::set<InstSeqNum> snList;
 585 #endif
 586
 587     /** Records if instructions need to be removed this cycle due to
 588      *  being retired or squashed.
 589      */
 590     bool removeInstsThisCycle;
 591
 592   protected:
 593     /** The fetch stage. */
 594     typename CPUPolicy::Fetch fetch;
 595
 596     /** The decode stage. */
 597     typename CPUPolicy::Decode decode;
 598
 599     /** The dispatch stage. */
 600     typename CPUPolicy::Rename rename;
 601
 602     /** The issue/execute/writeback stages. */
 603     typename CPUPolicy::IEW iew;
 604
 605     /** The commit stage. */
 606     typename CPUPolicy::Commit commit;
 607
 608     /** The rename mode of the vector registers */
 609     Enums::VecRegRenameMode vecMode;
 610
 611     /** The register file. */
 612     PhysRegFile regFile;
 613
 614     /** The free list. */
 615     typename CPUPolicy::FreeList freeList;
 616
 617     /** The rename map. */
 618     typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
 619
 620     /** The commit rename map. */
 621     typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
 622
 623     /** The re-order buffer. */
 624     typename CPUPolicy::ROB rob;
 625
 626     /** Active Threads List */
 627     std::list<ThreadID> activeThreads;
 628
 629     /** Integer Register Scoreboard */
 630     Scoreboard scoreboard;
 631
 632     std::vector<TheISA::ISA *> isa;
 633
 634     /** Instruction port. Note that it has to appear after the fetch stage. */
 635     IcachePort icachePort;
 636
 637     /** Data port. Note that it has to appear after the iew stages */
 638     DcachePort dcachePort;
 639
 640   public:
 641     /** Enum to give each stage a specific index, so when calling
 642      *  activateStage() or deactivateStage(), they can specify which stage
 643      *  is being activated/deactivated.
 644      */
 645     enum StageIdx {
 646         FetchIdx,
 647         DecodeIdx,
 648         RenameIdx,
 649         IEWIdx,
 650         CommitIdx,
 651         NumStages };
 652
 653     /** Typedefs from the Impl to get the structs that each of the
 654      *  time buffers should use.
 655      */
 656     typedef typename CPUPolicy::TimeStruct TimeStruct;
 657
 658     typedef typename CPUPolicy::FetchStruct FetchStruct;
 659
 660     typedef typename CPUPolicy::DecodeStruct DecodeStruct;
 661
 662     typedef typename CPUPolicy::RenameStruct RenameStruct;
 663
 664     typedef typename CPUPolicy::IEWStruct IEWStruct;
 665
 666     /** The main time buffer to do backwards communication. */
 667     TimeBuffer<TimeStruct> timeBuffer;
 668
 669     /** The fetch stage's instruction queue. */
 670     TimeBuffer<FetchStruct> fetchQueue;
 671
 672     /** The decode stage's instruction queue. */
 673     TimeBuffer<DecodeStruct> decodeQueue;
 674
 675     /** The rename stage's instruction queue. */
 676     TimeBuffer<RenameStruct> renameQueue;
 677
 678     /** The IEW stage's instruction queue. */
 679     TimeBuffer<IEWStruct> iewQueue;
 680
 681   private:
 682     /** The activity recorder; used to tell if the CPU has any
 683      * activity remaining or if it can go to idle and deschedule
 684      * itself.
 685      */
 686     ActivityRecorder activityRec;
 687
 688   public:
 689     /** Records that there was time buffer activity this cycle. */
 690     void activityThisCycle() { activityRec.activity(); }
 691
 692     /** Changes a stage's status to active within the activity recorder. */
 693     void activateStage(const StageIdx idx)
 694     { activityRec.activateStage(idx); }
 695
 696     /** Changes a stage's status to inactive within the activity recorder. */
 697     void deactivateStage(const StageIdx idx)
 698     { activityRec.deactivateStage(idx); }
 699
 700     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 701     void wakeCPU();
 702
 703     virtual void wakeup(ThreadID tid) override;
 704
 705     /** Gets a free thread id. Use if thread ids change across system. */
 706     ThreadID getFreeTid();
 707
 708   public:
 709     /** Returns a pointer to a thread context. */
 710     ThreadContext *
 711     tcBase(ThreadID tid)
 712     {
 713         return thread[tid]->getTC();
 714     }
 715
 716     /** The global sequence number counter. */
 717     InstSeqNum globalSeqNum;//[Impl::MaxThreads];
 718
 719     /** Pointer to the checker, which can dynamically verify
 720      * instruction results at run time.  This can be set to NULL if it
 721      * is not being used.
 722      */
 723     Checker<Impl> *checker;
 724
 725     /** Pointer to the system. */
 726     System *system;
 727
 728     /** Pointers to all of the threads in the CPU. */
 729     std::vector<Thread *> thread;
 730
 731     /** Threads Scheduled to Enter CPU */
 732     std::list<int> cpuWaitList;
 733
 734     /** The cycle that the CPU was last running, used for statistics. */
 735     Cycles lastRunningCycle;
 736
 737     /** The cycle that the CPU was last activated by a new thread*/
 738     Tick lastActivatedCycle;
 739
 740     /** Mapping for system thread id to cpu id */
 741     std::map<ThreadID, unsigned> threadMap;
 742
 743     /** Available thread ids in the cpu*/
 744     std::vector<ThreadID> tids;
 745
 746     /** CPU read function, forwards read to LSQ. */
 747     Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
 748                int load_idx)
 749     {
 750         return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, load_idx);
 751     }
 752
 753     /** CPU write function, forwards write to LSQ. */
 754     Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
 755                 uint8_t *data, int store_idx)
 756     {
 757         return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
 758                                          data, store_idx);
 759     }
 760
 761     /** Used by the fetch unit to get a hold of the instruction port. */
 762     MasterPort &getInstPort() override { return icachePort; }
 763
 764     /** Get the dcache port (used to find block size for translations). */
 765     MasterPort &getDataPort() override { return dcachePort; }
 766
 767     /** Stat for total number of times the CPU is descheduled. */
 768     Stats::Scalar timesIdled;
 769     /** Stat for total number of cycles the CPU spends descheduled. */
 770     Stats::Scalar idleCycles;
 771     /** Stat for total number of cycles the CPU spends descheduled due to a
 772      * quiesce operation or waiting for an interrupt. */
 773     Stats::Scalar quiesceCycles;
 774     /** Stat for the number of committed instructions per thread. */
 775     Stats::Vector committedInsts;
 776     /** Stat for the number of committed ops (including micro ops) per thread. */
 777     Stats::Vector committedOps;
 778     /** Stat for the CPI per thread. */
 779     Stats::Formula cpi;
 780     /** Stat for the total CPI. */
 781     Stats::Formula totalCpi;
 782     /** Stat for the IPC per thread. */
 783     Stats::Formula ipc;
 784     /** Stat for the total IPC. */
 785     Stats::Formula totalIpc;
 786
 787     //number of integer register file accesses
 788     Stats::Scalar intRegfileReads;
 789     Stats::Scalar intRegfileWrites;
 790     //number of float register file accesses
 791     Stats::Scalar fpRegfileReads;
 792     Stats::Scalar fpRegfileWrites;
 793     //number of vector register file accesses
 794     mutable Stats::Scalar vecRegfileReads;
 795     Stats::Scalar vecRegfileWrites;
 796     //number of CC register file accesses
 797     Stats::Scalar ccRegfileReads;
 798     Stats::Scalar ccRegfileWrites;
 799     //number of misc
 800     Stats::Scalar miscRegfileReads;
 801     Stats::Scalar miscRegfileWrites;
 802 };
 803
 804 #endif // __CPU_O3_CPU_HH__