src/cpu/o3/cpu.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2011 Regents of the University of California
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Kevin Lim
  42  *          Korey Sewell
  43  *          Rick Strong
  44  */
  45
  46 #ifndef __CPU_O3_CPU_HH__
  47 #define __CPU_O3_CPU_HH__
  48
  49 #include <iostream>
  50 #include <list>
  51 #include <queue>
  52 #include <set>
  53 #include <vector>
  54
  55 #include "arch/types.hh"
  56 #include "base/statistics.hh"
  57 #include "config/the_isa.hh"
  58 #include "cpu/o3/comm.hh"
  59 #include "cpu/o3/cpu_policy.hh"
  60 #include "cpu/o3/scoreboard.hh"
  61 #include "cpu/o3/thread_state.hh"
  62 #include "cpu/activity.hh"
  63 #include "cpu/base.hh"
  64 #include "cpu/simple_thread.hh"
  65 #include "cpu/timebuf.hh"
  66 //#include "cpu/o3/thread_context.hh"
  67 #include "params/DerivO3CPU.hh"
  68 #include "sim/process.hh"
  69
  70 template <class>
  71 class Checker;
  72 class ThreadContext;
  73 template <class>
  74 class O3ThreadContext;
  75
  76 class Checkpoint;
  77 class MemObject;
  78 class Process;
  79
  80 struct BaseCPUParams;
  81
  82 class BaseO3CPU : public BaseCPU
  83 {
  84     //Stuff that's pretty ISA independent will go here.
  85   public:
  86     BaseO3CPU(BaseCPUParams *params);
  87
  88     void regStats();
  89 };
  90
  91 /**
  92  * FullO3CPU class, has each of the stages (fetch through commit)
  93  * within it, as well as all of the time buffers between stages.  The
  94  * tick() function for the CPU is defined here.
  95  */
  96 template <class Impl>
  97 class FullO3CPU : public BaseO3CPU
  98 {
  99   public:
 100     // Typedefs from the Impl here.
 101     typedef typename Impl::CPUPol CPUPolicy;
 102     typedef typename Impl::DynInstPtr DynInstPtr;
 103     typedef typename Impl::O3CPU O3CPU;
 104
 105     typedef O3ThreadState<Impl> ImplState;
 106     typedef O3ThreadState<Impl> Thread;
 107
 108     typedef typename std::list<DynInstPtr>::iterator ListIt;
 109
 110     friend class O3ThreadContext<Impl>;
 111
 112   public:
 113     enum Status {
 114         Running,
 115         Idle,
 116         Halted,
 117         Blocked,
 118         SwitchedOut
 119     };
 120
 121     TheISA::TLB * itb;
 122     TheISA::TLB * dtb;
 123
 124     /** Overall CPU status. */
 125     Status _status;
 126
 127     /** Per-thread status in CPU, used for SMT.  */
 128     Status _threadStatus[Impl::MaxThreads];
 129
 130   private:
 131
 132     /**
 133      * IcachePort class for instruction fetch.
 134      */
 135     class IcachePort : public CpuPort
 136     {
 137       protected:
 138         /** Pointer to fetch. */
 139         DefaultFetch<Impl> *fetch;
 140
 141       public:
 142         /** Default constructor. */
 143         IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
 144             : CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
 145         { }
 146
 147       protected:
 148
 149         /** Timing version of receive.  Handles setting fetch to the
 150          * proper status to start fetching. */
 151         virtual bool recvTimingResp(PacketPtr pkt);
 152         virtual void recvTimingSnoopReq(PacketPtr pkt) { }
 153
 154         /** Handles doing a retry of a failed fetch. */
 155         virtual void recvRetry();
 156     };
 157
 158     /**
 159      * DcachePort class for the load/store queue.
 160      */
 161     class DcachePort : public CpuPort
 162     {
 163       protected:
 164
 165         /** Pointer to LSQ. */
 166         LSQ<Impl> *lsq;
 167
 168       public:
 169         /** Default constructor. */
 170         DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
 171             : CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
 172         { }
 173
 174       protected:
 175
 176         /** Timing version of receive.  Handles writing back and
 177          * completing the load or store that has returned from
 178          * memory. */
 179         virtual bool recvTimingResp(PacketPtr pkt);
 180         virtual void recvTimingSnoopReq(PacketPtr pkt);
 181
 182         /** Handles doing a retry of the previous send. */
 183         virtual void recvRetry();
 184
 185         /**
 186          * As this CPU requires snooping to maintain the load store queue
 187          * change the behaviour from the base CPU port.
 188          *
 189          * @return true since we have to snoop
 190          */
 191         virtual bool isSnooping() const { return true; }
 192     };
 193
 194     class TickEvent : public Event
 195     {
 196       private:
 197         /** Pointer to the CPU. */
 198         FullO3CPU<Impl> *cpu;
 199
 200       public:
 201         /** Constructs a tick event. */
 202         TickEvent(FullO3CPU<Impl> *c);
 203
 204         /** Processes a tick event, calling tick() on the CPU. */
 205         void process();
 206         /** Returns the description of the tick event. */
 207         const char *description() const;
 208     };
 209
 210     /** The tick event used for scheduling CPU ticks. */
 211     TickEvent tickEvent;
 212
 213     /** Schedule tick event, regardless of its current state. */
 214     void scheduleTickEvent(int delay)
 215     {
 216         if (tickEvent.squashed())
 217             reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
 218         else if (!tickEvent.scheduled())
 219             schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
 220     }
 221
 222     /** Unschedule tick event, regardless of its current state. */
 223     void unscheduleTickEvent()
 224     {
 225         if (tickEvent.scheduled())
 226             tickEvent.squash();
 227     }
 228
 229     class ActivateThreadEvent : public Event
 230     {
 231       private:
 232         /** Number of Thread to Activate */
 233         ThreadID tid;
 234
 235         /** Pointer to the CPU. */
 236         FullO3CPU<Impl> *cpu;
 237
 238       public:
 239         /** Constructs the event. */
 240         ActivateThreadEvent();
 241
 242         /** Initialize Event */
 243         void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
 244
 245         /** Processes the event, calling activateThread() on the CPU. */
 246         void process();
 247
 248         /** Returns the description of the event. */
 249         const char *description() const;
 250     };
 251
 252     /** Schedule thread to activate , regardless of its current state. */
 253     void
 254     scheduleActivateThreadEvent(ThreadID tid, int delay)
 255     {
 256         // Schedule thread to activate, regardless of its current state.
 257         if (activateThreadEvent[tid].squashed())
 258             reschedule(activateThreadEvent[tid],
 259                 nextCycle(curTick() + ticks(delay)));
 260         else if (!activateThreadEvent[tid].scheduled()) {
 261             Tick when = nextCycle(curTick() + ticks(delay));
 262
 263             // Check if the deallocateEvent is also scheduled, and make
 264             // sure they do not happen at same time causing a sleep that
 265             // is never woken from.
 266             if (deallocateContextEvent[tid].scheduled() &&
 267                 deallocateContextEvent[tid].when() == when) {
 268                 when++;
 269             }
 270
 271             schedule(activateThreadEvent[tid], when);
 272         }
 273     }
 274
 275     /** Unschedule actiavte thread event, regardless of its current state. */
 276     void
 277     unscheduleActivateThreadEvent(ThreadID tid)
 278     {
 279         if (activateThreadEvent[tid].scheduled())
 280             activateThreadEvent[tid].squash();
 281     }
 282
 283     /** The tick event used for scheduling CPU ticks. */
 284     ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
 285
 286     class DeallocateContextEvent : public Event
 287     {
 288       private:
 289         /** Number of Thread to deactivate */
 290         ThreadID tid;
 291
 292         /** Should the thread be removed from the CPU? */
 293         bool remove;
 294
 295         /** Pointer to the CPU. */
 296         FullO3CPU<Impl> *cpu;
 297
 298       public:
 299         /** Constructs the event. */
 300         DeallocateContextEvent();
 301
 302         /** Initialize Event */
 303         void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
 304
 305         /** Processes the event, calling activateThread() on the CPU. */
 306         void process();
 307
 308         /** Sets whether the thread should also be removed from the CPU. */
 309         void setRemove(bool _remove) { remove = _remove; }
 310
 311         /** Returns the description of the event. */
 312         const char *description() const;
 313     };
 314
 315     /** Schedule cpu to deallocate thread context.*/
 316     void
 317     scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay)
 318     {
 319         // Schedule thread to activate, regardless of its current state.
 320         if (deallocateContextEvent[tid].squashed())
 321             reschedule(deallocateContextEvent[tid],
 322                 nextCycle(curTick() + ticks(delay)));
 323         else if (!deallocateContextEvent[tid].scheduled())
 324             schedule(deallocateContextEvent[tid],
 325                 nextCycle(curTick() + ticks(delay)));
 326     }
 327
 328     /** Unschedule thread deallocation in CPU */
 329     void
 330     unscheduleDeallocateContextEvent(ThreadID tid)
 331     {
 332         if (deallocateContextEvent[tid].scheduled())
 333             deallocateContextEvent[tid].squash();
 334     }
 335
 336     /** The tick event used for scheduling CPU ticks. */
 337     DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
 338
 339   public:
 340     /** Constructs a CPU with the given parameters. */
 341     FullO3CPU(DerivO3CPUParams *params);
 342     /** Destructor. */
 343     ~FullO3CPU();
 344
 345     /** Registers statistics. */
 346     void regStats();
 347
 348     void demapPage(Addr vaddr, uint64_t asn)
 349     {
 350         this->itb->demapPage(vaddr, asn);
 351         this->dtb->demapPage(vaddr, asn);
 352     }
 353
 354     void demapInstPage(Addr vaddr, uint64_t asn)
 355     {
 356         this->itb->demapPage(vaddr, asn);
 357     }
 358
 359     void demapDataPage(Addr vaddr, uint64_t asn)
 360     {
 361         this->dtb->demapPage(vaddr, asn);
 362     }
 363
 364     /** Ticks CPU, calling tick() on each stage, and checking the overall
 365      *  activity to see if the CPU should deschedule itself.
 366      */
 367     void tick();
 368
 369     /** Initialize the CPU */
 370     void init();
 371
 372     /** Returns the Number of Active Threads in the CPU */
 373     int numActiveThreads()
 374     { return activeThreads.size(); }
 375
 376     /** Add Thread to Active Threads List */
 377     void activateThread(ThreadID tid);
 378
 379     /** Remove Thread from Active Threads List */
 380     void deactivateThread(ThreadID tid);
 381
 382     /** Setup CPU to insert a thread's context */
 383     void insertThread(ThreadID tid);
 384
 385     /** Remove all of a thread's context from CPU */
 386     void removeThread(ThreadID tid);
 387
 388     /** Count the Total Instructions Committed in the CPU. */
 389     virtual Counter totalInsts() const;
 390
 391     /** Count the Total Ops (including micro ops) committed in the CPU. */
 392     virtual Counter totalOps() const;
 393
 394     /** Add Thread to Active Threads List. */
 395     void activateContext(ThreadID tid, int delay);
 396
 397     /** Remove Thread from Active Threads List */
 398     void suspendContext(ThreadID tid);
 399
 400     /** Remove Thread from Active Threads List &&
 401      *  Possibly Remove Thread Context from CPU.
 402      */
 403     bool scheduleDeallocateContext(ThreadID tid, bool remove, int delay = 1);
 404
 405     /** Remove Thread from Active Threads List &&
 406      *  Remove Thread Context from CPU.
 407      */
 408     void haltContext(ThreadID tid);
 409
 410     /** Activate a Thread When CPU Resources are Available. */
 411     void activateWhenReady(ThreadID tid);
 412
 413     /** Add or Remove a Thread Context in the CPU. */
 414     void doContextSwitch();
 415
 416     /** Update The Order In Which We Process Threads. */
 417     void updateThreadPriority();
 418
 419     /** Serialize state. */
 420     virtual void serialize(std::ostream &os);
 421
 422     /** Unserialize from a checkpoint. */
 423     virtual void unserialize(Checkpoint *cp, const std::string &section);
 424
 425   public:
 426     /** Executes a syscall.
 427      * @todo: Determine if this needs to be virtual.
 428      */
 429     void syscall(int64_t callnum, ThreadID tid);
 430
 431     /** Starts draining the CPU's pipeline of all instructions in
 432      * order to stop all memory accesses. */
 433     virtual unsigned int drain(Event *drain_event);
 434
 435     /** Resumes execution after a drain. */
 436     virtual void resume();
 437
 438     /** Signals to this CPU that a stage has completed switching out. */
 439     void signalDrained();
 440
 441     /** Switches out this CPU. */
 442     virtual void switchOut();
 443
 444     /** Takes over from another CPU. */
 445     virtual void takeOverFrom(BaseCPU *oldCPU);
 446
 447     /** Get the current instruction sequence number, and increment it. */
 448     InstSeqNum getAndIncrementInstSeq()
 449     { return globalSeqNum++; }
 450
 451     /** Traps to handle given fault. */
 452     void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
 453
 454     /** HW return from error interrupt. */
 455     Fault hwrei(ThreadID tid);
 456
 457     bool simPalCheck(int palFunc, ThreadID tid);
 458
 459     /** Returns the Fault for any valid interrupt. */
 460     Fault getInterrupts();
 461
 462     /** Processes any an interrupt fault. */
 463     void processInterrupts(Fault interrupt);
 464
 465     /** Halts the CPU. */
 466     void halt() { panic("Halt not implemented!\n"); }
 467
 468     /** Check if this address is a valid instruction address. */
 469     bool validInstAddr(Addr addr) { return true; }
 470
 471     /** Check if this address is a valid data address. */
 472     bool validDataAddr(Addr addr) { return true; }
 473
 474     /** Register accessors.  Index refers to the physical register index. */
 475
 476     /** Reads a miscellaneous register. */
 477     TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
 478
 479     /** Reads a misc. register, including any side effects the read
 480      * might have as defined by the architecture.
 481      */
 482     TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
 483
 484     /** Sets a miscellaneous register. */
 485     void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
 486             ThreadID tid);
 487
 488     /** Sets a misc. register, including any side effects the write
 489      * might have as defined by the architecture.
 490      */
 491     void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
 492             ThreadID tid);
 493
 494     uint64_t readIntReg(int reg_idx);
 495
 496     TheISA::FloatReg readFloatReg(int reg_idx);
 497
 498     TheISA::FloatRegBits readFloatRegBits(int reg_idx);
 499
 500     void setIntReg(int reg_idx, uint64_t val);
 501
 502     void setFloatReg(int reg_idx, TheISA::FloatReg val);
 503
 504     void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
 505
 506     uint64_t readArchIntReg(int reg_idx, ThreadID tid);
 507
 508     float readArchFloatReg(int reg_idx, ThreadID tid);
 509
 510     uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
 511
 512     /** Architectural register accessors.  Looks up in the commit
 513      * rename table to obtain the true physical index of the
 514      * architected register first, then accesses that physical
 515      * register.
 516      */
 517     void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
 518
 519     void setArchFloatReg(int reg_idx, float val, ThreadID tid);
 520
 521     void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
 522
 523     /** Sets the commit PC state of a specific thread. */
 524     void pcState(const TheISA::PCState &newPCState, ThreadID tid);
 525
 526     /** Reads the commit PC state of a specific thread. */
 527     TheISA::PCState pcState(ThreadID tid);
 528
 529     /** Reads the commit PC of a specific thread. */
 530     Addr instAddr(ThreadID tid);
 531
 532     /** Reads the commit micro PC of a specific thread. */
 533     MicroPC microPC(ThreadID tid);
 534
 535     /** Reads the next PC of a specific thread. */
 536     Addr nextInstAddr(ThreadID tid);
 537
 538     /** Initiates a squash of all in-flight instructions for a given
 539      * thread.  The source of the squash is an external update of
 540      * state through the TC.
 541      */
 542     void squashFromTC(ThreadID tid);
 543
 544     /** Function to add instruction onto the head of the list of the
 545      *  instructions.  Used when new instructions are fetched.
 546      */
 547     ListIt addInst(DynInstPtr &inst);
 548
 549     /** Function to tell the CPU that an instruction has completed. */
 550     void instDone(ThreadID tid, DynInstPtr &inst);
 551
 552     /** Remove an instruction from the front end of the list.  There's
 553      *  no restriction on location of the instruction.
 554      */
 555     void removeFrontInst(DynInstPtr &inst);
 556
 557     /** Remove all instructions that are not currently in the ROB.
 558      *  There's also an option to not squash delay slot instructions.*/
 559     void removeInstsNotInROB(ThreadID tid);
 560
 561     /** Remove all instructions younger than the given sequence number. */
 562     void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
 563
 564     /** Removes the instruction pointed to by the iterator. */
 565     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 566
 567     /** Cleans up all instructions on the remove list. */
 568     void cleanUpRemovedInsts();
 569
 570     /** Debug function to print all instructions on the list. */
 571     void dumpInsts();
 572
 573   public:
 574 #ifndef NDEBUG
 575     /** Count of total number of dynamic instructions in flight. */
 576     int instcount;
 577 #endif
 578
 579     /** List of all the instructions in flight. */
 580     std::list<DynInstPtr> instList;
 581
 582     /** List of all the instructions that will be removed at the end of this
 583      *  cycle.
 584      */
 585     std::queue<ListIt> removeList;
 586
 587 #ifdef DEBUG
 588     /** Debug structure to keep track of the sequence numbers still in
 589      * flight.
 590      */
 591     std::set<InstSeqNum> snList;
 592 #endif
 593
 594     /** Records if instructions need to be removed this cycle due to
 595      *  being retired or squashed.
 596      */
 597     bool removeInstsThisCycle;
 598
 599   protected:
 600     /** The fetch stage. */
 601     typename CPUPolicy::Fetch fetch;
 602
 603     /** The decode stage. */
 604     typename CPUPolicy::Decode decode;
 605
 606     /** The dispatch stage. */
 607     typename CPUPolicy::Rename rename;
 608
 609     /** The issue/execute/writeback stages. */
 610     typename CPUPolicy::IEW iew;
 611
 612     /** The commit stage. */
 613     typename CPUPolicy::Commit commit;
 614
 615     /** The register file. */
 616     typename CPUPolicy::RegFile regFile;
 617
 618     /** The free list. */
 619     typename CPUPolicy::FreeList freeList;
 620
 621     /** The rename map. */
 622     typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
 623
 624     /** The commit rename map. */
 625     typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
 626
 627     /** The re-order buffer. */
 628     typename CPUPolicy::ROB rob;
 629
 630     /** Active Threads List */
 631     std::list<ThreadID> activeThreads;
 632
 633     /** Integer Register Scoreboard */
 634     Scoreboard scoreboard;
 635
 636     TheISA::ISA isa[Impl::MaxThreads];
 637
 638     /** Instruction port. Note that it has to appear after the fetch stage. */
 639     IcachePort icachePort;
 640
 641     /** Data port. Note that it has to appear after the iew stages */
 642     DcachePort dcachePort;
 643
 644   public:
 645     /** Enum to give each stage a specific index, so when calling
 646      *  activateStage() or deactivateStage(), they can specify which stage
 647      *  is being activated/deactivated.
 648      */
 649     enum StageIdx {
 650         FetchIdx,
 651         DecodeIdx,
 652         RenameIdx,
 653         IEWIdx,
 654         CommitIdx,
 655         NumStages };
 656
 657     /** Typedefs from the Impl to get the structs that each of the
 658      *  time buffers should use.
 659      */
 660     typedef typename CPUPolicy::TimeStruct TimeStruct;
 661
 662     typedef typename CPUPolicy::FetchStruct FetchStruct;
 663
 664     typedef typename CPUPolicy::DecodeStruct DecodeStruct;
 665
 666     typedef typename CPUPolicy::RenameStruct RenameStruct;
 667
 668     typedef typename CPUPolicy::IEWStruct IEWStruct;
 669
 670     /** The main time buffer to do backwards communication. */
 671     TimeBuffer<TimeStruct> timeBuffer;
 672
 673     /** The fetch stage's instruction queue. */
 674     TimeBuffer<FetchStruct> fetchQueue;
 675
 676     /** The decode stage's instruction queue. */
 677     TimeBuffer<DecodeStruct> decodeQueue;
 678
 679     /** The rename stage's instruction queue. */
 680     TimeBuffer<RenameStruct> renameQueue;
 681
 682     /** The IEW stage's instruction queue. */
 683     TimeBuffer<IEWStruct> iewQueue;
 684
 685   private:
 686     /** The activity recorder; used to tell if the CPU has any
 687      * activity remaining or if it can go to idle and deschedule
 688      * itself.
 689      */
 690     ActivityRecorder activityRec;
 691
 692   public:
 693     /** Records that there was time buffer activity this cycle. */
 694     void activityThisCycle() { activityRec.activity(); }
 695
 696     /** Changes a stage's status to active within the activity recorder. */
 697     void activateStage(const StageIdx idx)
 698     { activityRec.activateStage(idx); }
 699
 700     /** Changes a stage's status to inactive within the activity recorder. */
 701     void deactivateStage(const StageIdx idx)
 702     { activityRec.deactivateStage(idx); }
 703
 704     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 705     void wakeCPU();
 706
 707     virtual void wakeup();
 708
 709     /** Gets a free thread id. Use if thread ids change across system. */
 710     ThreadID getFreeTid();
 711
 712   public:
 713     /** Returns a pointer to a thread context. */
 714     ThreadContext *
 715     tcBase(ThreadID tid)
 716     {
 717         return thread[tid]->getTC();
 718     }
 719
 720     /** The global sequence number counter. */
 721     InstSeqNum globalSeqNum;//[Impl::MaxThreads];
 722
 723     /** Pointer to the checker, which can dynamically verify
 724      * instruction results at run time.  This can be set to NULL if it
 725      * is not being used.
 726      */
 727     Checker<Impl> *checker;
 728
 729     /** Pointer to the system. */
 730     System *system;
 731
 732     /** Event to call process() on once draining has completed. */
 733     Event *drainEvent;
 734
 735     /** Counter of how many stages have completed draining. */
 736     int drainCount;
 737
 738     /** Pointers to all of the threads in the CPU. */
 739     std::vector<Thread *> thread;
 740
 741     /** Whether or not the CPU should defer its registration. */
 742     bool deferRegistration;
 743
 744     /** Is there a context switch pending? */
 745     bool contextSwitch;
 746
 747     /** Threads Scheduled to Enter CPU */
 748     std::list<int> cpuWaitList;
 749
 750     /** The cycle that the CPU was last running, used for statistics. */
 751     Tick lastRunningCycle;
 752
 753     /** The cycle that the CPU was last activated by a new thread*/
 754     Tick lastActivatedCycle;
 755
 756     /** Mapping for system thread id to cpu id */
 757     std::map<ThreadID, unsigned> threadMap;
 758
 759     /** Available thread ids in the cpu*/
 760     std::vector<ThreadID> tids;
 761
 762     /** CPU read function, forwards read to LSQ. */
 763     Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
 764                uint8_t *data, int load_idx)
 765     {
 766         return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
 767                                         data, load_idx);
 768     }
 769
 770     /** CPU write function, forwards write to LSQ. */
 771     Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
 772                 uint8_t *data, int store_idx)
 773     {
 774         return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
 775                                          data, store_idx);
 776     }
 777
 778     /** Used by the fetch unit to get a hold of the instruction port. */
 779     virtual CpuPort &getInstPort() { return icachePort; }
 780
 781     /** Get the dcache port (used to find block size for translations). */
 782     virtual CpuPort &getDataPort() { return dcachePort; }
 783
 784     Addr lockAddr;
 785
 786     /** Temporary fix for the lock flag, works in the UP case. */
 787     bool lockFlag;
 788
 789     /** Stat for total number of times the CPU is descheduled. */
 790     Stats::Scalar timesIdled;
 791     /** Stat for total number of cycles the CPU spends descheduled. */
 792     Stats::Scalar idleCycles;
 793     /** Stat for total number of cycles the CPU spends descheduled due to a
 794      * quiesce operation or waiting for an interrupt. */
 795     Stats::Scalar quiesceCycles;
 796     /** Stat for the number of committed instructions per thread. */
 797     Stats::Vector committedInsts;
 798     /** Stat for the number of committed ops (including micro ops) per thread. */
 799     Stats::Vector committedOps;
 800     /** Stat for the total number of committed instructions. */
 801     Stats::Scalar totalCommittedInsts;
 802     /** Stat for the CPI per thread. */
 803     Stats::Formula cpi;
 804     /** Stat for the total CPI. */
 805     Stats::Formula totalCpi;
 806     /** Stat for the IPC per thread. */
 807     Stats::Formula ipc;
 808     /** Stat for the total IPC. */
 809     Stats::Formula totalIpc;
 810
 811     //number of integer register file accesses
 812     Stats::Scalar intRegfileReads;
 813     Stats::Scalar intRegfileWrites;
 814     //number of float register file accesses
 815     Stats::Scalar fpRegfileReads;
 816     Stats::Scalar fpRegfileWrites;
 817     //number of misc
 818     Stats::Scalar miscRegfileReads;
 819     Stats::Scalar miscRegfileWrites;
 820 };
 821
 822 #endif // __CPU_O3_CPU_HH__