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46 #ifndef __CPU_O3_CPU_HH__
47 #define __CPU_O3_CPU_HH__
55 #include "arch/types.hh"
56 #include "base/statistics.hh"
57 #include "config/the_isa.hh"
58 #include "cpu/o3/comm.hh"
59 #include "cpu/o3/cpu_policy.hh"
60 #include "cpu/o3/scoreboard.hh"
61 #include "cpu/o3/thread_state.hh"
62 #include "cpu/activity.hh"
63 #include "cpu/base.hh"
64 #include "cpu/simple_thread.hh"
65 #include "cpu/timebuf.hh"
66 //#include "cpu/o3/thread_context.hh"
67 #include "params/DerivO3CPU.hh"
68 #include "sim/process.hh"
74 class O3ThreadContext;
82 class BaseO3CPU : public BaseCPU
84 //Stuff that's pretty ISA independent will go here.
86 BaseO3CPU(BaseCPUParams *params);
92 * FullO3CPU class, has each of the stages (fetch through commit)
93 * within it, as well as all of the time buffers between stages. The
94 * tick() function for the CPU is defined here.
97 class FullO3CPU : public BaseO3CPU
100 // Typedefs from the Impl here.
101 typedef typename Impl::CPUPol CPUPolicy;
102 typedef typename Impl::DynInstPtr DynInstPtr;
103 typedef typename Impl::O3CPU O3CPU;
105 typedef O3ThreadState<Impl> ImplState;
106 typedef O3ThreadState<Impl> Thread;
108 typedef typename std::list<DynInstPtr>::iterator ListIt;
110 friend class O3ThreadContext<Impl>;
124 /** Overall CPU status. */
127 /** Per-thread status in CPU, used for SMT. */
128 Status _threadStatus[Impl::MaxThreads];
133 * IcachePort class for instruction fetch.
135 class IcachePort : public CpuPort
138 /** Pointer to fetch. */
139 DefaultFetch<Impl> *fetch;
142 /** Default constructor. */
143 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
144 : CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
149 /** Timing version of receive. Handles setting fetch to the
150 * proper status to start fetching. */
151 virtual bool recvTimingResp(PacketPtr pkt);
152 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
154 /** Handles doing a retry of a failed fetch. */
155 virtual void recvRetry();
159 * DcachePort class for the load/store queue.
161 class DcachePort : public CpuPort
165 /** Pointer to LSQ. */
169 /** Default constructor. */
170 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
171 : CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
176 /** Timing version of receive. Handles writing back and
177 * completing the load or store that has returned from
179 virtual bool recvTimingResp(PacketPtr pkt);
180 virtual void recvTimingSnoopReq(PacketPtr pkt);
182 /** Handles doing a retry of the previous send. */
183 virtual void recvRetry();
186 * As this CPU requires snooping to maintain the load store queue
187 * change the behaviour from the base CPU port.
189 * @return true since we have to snoop
191 virtual bool isSnooping() const { return true; }
194 class TickEvent : public Event
197 /** Pointer to the CPU. */
198 FullO3CPU<Impl> *cpu;
201 /** Constructs a tick event. */
202 TickEvent(FullO3CPU<Impl> *c);
204 /** Processes a tick event, calling tick() on the CPU. */
206 /** Returns the description of the tick event. */
207 const char *description() const;
210 /** The tick event used for scheduling CPU ticks. */
213 /** Schedule tick event, regardless of its current state. */
214 void scheduleTickEvent(Cycles delay)
216 if (tickEvent.squashed())
217 reschedule(tickEvent, clockEdge(delay));
218 else if (!tickEvent.scheduled())
219 schedule(tickEvent, clockEdge(delay));
222 /** Unschedule tick event, regardless of its current state. */
223 void unscheduleTickEvent()
225 if (tickEvent.scheduled())
229 class ActivateThreadEvent : public Event
232 /** Number of Thread to Activate */
235 /** Pointer to the CPU. */
236 FullO3CPU<Impl> *cpu;
239 /** Constructs the event. */
240 ActivateThreadEvent();
242 /** Initialize Event */
243 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
245 /** Processes the event, calling activateThread() on the CPU. */
248 /** Returns the description of the event. */
249 const char *description() const;
252 /** Schedule thread to activate , regardless of its current state. */
254 scheduleActivateThreadEvent(ThreadID tid, Cycles delay)
256 // Schedule thread to activate, regardless of its current state.
257 if (activateThreadEvent[tid].squashed())
258 reschedule(activateThreadEvent[tid],
260 else if (!activateThreadEvent[tid].scheduled()) {
261 Tick when = clockEdge(delay);
263 // Check if the deallocateEvent is also scheduled, and make
264 // sure they do not happen at same time causing a sleep that
265 // is never woken from.
266 if (deallocateContextEvent[tid].scheduled() &&
267 deallocateContextEvent[tid].when() == when) {
271 schedule(activateThreadEvent[tid], when);
275 /** Unschedule actiavte thread event, regardless of its current state. */
277 unscheduleActivateThreadEvent(ThreadID tid)
279 if (activateThreadEvent[tid].scheduled())
280 activateThreadEvent[tid].squash();
283 /** The tick event used for scheduling CPU ticks. */
284 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
286 class DeallocateContextEvent : public Event
289 /** Number of Thread to deactivate */
292 /** Should the thread be removed from the CPU? */
295 /** Pointer to the CPU. */
296 FullO3CPU<Impl> *cpu;
299 /** Constructs the event. */
300 DeallocateContextEvent();
302 /** Initialize Event */
303 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
305 /** Processes the event, calling activateThread() on the CPU. */
308 /** Sets whether the thread should also be removed from the CPU. */
309 void setRemove(bool _remove) { remove = _remove; }
311 /** Returns the description of the event. */
312 const char *description() const;
315 /** Schedule cpu to deallocate thread context.*/
317 scheduleDeallocateContextEvent(ThreadID tid, bool remove, Cycles delay)
319 // Schedule thread to activate, regardless of its current state.
320 if (deallocateContextEvent[tid].squashed())
321 reschedule(deallocateContextEvent[tid],
323 else if (!deallocateContextEvent[tid].scheduled())
324 schedule(deallocateContextEvent[tid],
328 /** Unschedule thread deallocation in CPU */
330 unscheduleDeallocateContextEvent(ThreadID tid)
332 if (deallocateContextEvent[tid].scheduled())
333 deallocateContextEvent[tid].squash();
336 /** The tick event used for scheduling CPU ticks. */
337 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
340 /** Constructs a CPU with the given parameters. */
341 FullO3CPU(DerivO3CPUParams *params);
345 /** Registers statistics. */
348 void demapPage(Addr vaddr, uint64_t asn)
350 this->itb->demapPage(vaddr, asn);
351 this->dtb->demapPage(vaddr, asn);
354 void demapInstPage(Addr vaddr, uint64_t asn)
356 this->itb->demapPage(vaddr, asn);
359 void demapDataPage(Addr vaddr, uint64_t asn)
361 this->dtb->demapPage(vaddr, asn);
364 /** Ticks CPU, calling tick() on each stage, and checking the overall
365 * activity to see if the CPU should deschedule itself.
369 /** Initialize the CPU */
372 /** Returns the Number of Active Threads in the CPU */
373 int numActiveThreads()
374 { return activeThreads.size(); }
376 /** Add Thread to Active Threads List */
377 void activateThread(ThreadID tid);
379 /** Remove Thread from Active Threads List */
380 void deactivateThread(ThreadID tid);
382 /** Setup CPU to insert a thread's context */
383 void insertThread(ThreadID tid);
385 /** Remove all of a thread's context from CPU */
386 void removeThread(ThreadID tid);
388 /** Count the Total Instructions Committed in the CPU. */
389 virtual Counter totalInsts() const;
391 /** Count the Total Ops (including micro ops) committed in the CPU. */
392 virtual Counter totalOps() const;
394 /** Add Thread to Active Threads List. */
395 void activateContext(ThreadID tid, Cycles delay);
397 /** Remove Thread from Active Threads List */
398 void suspendContext(ThreadID tid);
400 /** Remove Thread from Active Threads List &&
401 * Possibly Remove Thread Context from CPU.
403 bool scheduleDeallocateContext(ThreadID tid, bool remove,
404 Cycles delay = Cycles(1));
406 /** Remove Thread from Active Threads List &&
407 * Remove Thread Context from CPU.
409 void haltContext(ThreadID tid);
411 /** Activate a Thread When CPU Resources are Available. */
412 void activateWhenReady(ThreadID tid);
414 /** Add or Remove a Thread Context in the CPU. */
415 void doContextSwitch();
417 /** Update The Order In Which We Process Threads. */
418 void updateThreadPriority();
420 /** Serialize state. */
421 virtual void serialize(std::ostream &os);
423 /** Unserialize from a checkpoint. */
424 virtual void unserialize(Checkpoint *cp, const std::string §ion);
427 /** Executes a syscall.
428 * @todo: Determine if this needs to be virtual.
430 void syscall(int64_t callnum, ThreadID tid);
432 /** Starts draining the CPU's pipeline of all instructions in
433 * order to stop all memory accesses. */
434 unsigned int drain(DrainManager *drain_manager);
436 /** Resumes execution after a drain. */
439 /** Signals to this CPU that a stage has completed switching out. */
440 void signalDrained();
442 /** Switches out this CPU. */
443 virtual void switchOut();
445 /** Takes over from another CPU. */
446 virtual void takeOverFrom(BaseCPU *oldCPU);
448 /** Get the current instruction sequence number, and increment it. */
449 InstSeqNum getAndIncrementInstSeq()
450 { return globalSeqNum++; }
452 /** Traps to handle given fault. */
453 void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
455 /** HW return from error interrupt. */
456 Fault hwrei(ThreadID tid);
458 bool simPalCheck(int palFunc, ThreadID tid);
460 /** Returns the Fault for any valid interrupt. */
461 Fault getInterrupts();
463 /** Processes any an interrupt fault. */
464 void processInterrupts(Fault interrupt);
466 /** Halts the CPU. */
467 void halt() { panic("Halt not implemented!\n"); }
469 /** Check if this address is a valid instruction address. */
470 bool validInstAddr(Addr addr) { return true; }
472 /** Check if this address is a valid data address. */
473 bool validDataAddr(Addr addr) { return true; }
475 /** Register accessors. Index refers to the physical register index. */
477 /** Reads a miscellaneous register. */
478 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
480 /** Reads a misc. register, including any side effects the read
481 * might have as defined by the architecture.
483 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
485 /** Sets a miscellaneous register. */
486 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
489 /** Sets a misc. register, including any side effects the write
490 * might have as defined by the architecture.
492 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
495 uint64_t readIntReg(int reg_idx);
497 TheISA::FloatReg readFloatReg(int reg_idx);
499 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
501 void setIntReg(int reg_idx, uint64_t val);
503 void setFloatReg(int reg_idx, TheISA::FloatReg val);
505 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
507 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
509 float readArchFloatReg(int reg_idx, ThreadID tid);
511 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
513 /** Architectural register accessors. Looks up in the commit
514 * rename table to obtain the true physical index of the
515 * architected register first, then accesses that physical
518 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
520 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
522 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
524 /** Sets the commit PC state of a specific thread. */
525 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
527 /** Reads the commit PC state of a specific thread. */
528 TheISA::PCState pcState(ThreadID tid);
530 /** Reads the commit PC of a specific thread. */
531 Addr instAddr(ThreadID tid);
533 /** Reads the commit micro PC of a specific thread. */
534 MicroPC microPC(ThreadID tid);
536 /** Reads the next PC of a specific thread. */
537 Addr nextInstAddr(ThreadID tid);
539 /** Initiates a squash of all in-flight instructions for a given
540 * thread. The source of the squash is an external update of
541 * state through the TC.
543 void squashFromTC(ThreadID tid);
545 /** Function to add instruction onto the head of the list of the
546 * instructions. Used when new instructions are fetched.
548 ListIt addInst(DynInstPtr &inst);
550 /** Function to tell the CPU that an instruction has completed. */
551 void instDone(ThreadID tid, DynInstPtr &inst);
553 /** Remove an instruction from the front end of the list. There's
554 * no restriction on location of the instruction.
556 void removeFrontInst(DynInstPtr &inst);
558 /** Remove all instructions that are not currently in the ROB.
559 * There's also an option to not squash delay slot instructions.*/
560 void removeInstsNotInROB(ThreadID tid);
562 /** Remove all instructions younger than the given sequence number. */
563 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
565 /** Removes the instruction pointed to by the iterator. */
566 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
568 /** Cleans up all instructions on the remove list. */
569 void cleanUpRemovedInsts();
571 /** Debug function to print all instructions on the list. */
576 /** Count of total number of dynamic instructions in flight. */
580 /** List of all the instructions in flight. */
581 std::list<DynInstPtr> instList;
583 /** List of all the instructions that will be removed at the end of this
586 std::queue<ListIt> removeList;
589 /** Debug structure to keep track of the sequence numbers still in
592 std::set<InstSeqNum> snList;
595 /** Records if instructions need to be removed this cycle due to
596 * being retired or squashed.
598 bool removeInstsThisCycle;
601 /** The fetch stage. */
602 typename CPUPolicy::Fetch fetch;
604 /** The decode stage. */
605 typename CPUPolicy::Decode decode;
607 /** The dispatch stage. */
608 typename CPUPolicy::Rename rename;
610 /** The issue/execute/writeback stages. */
611 typename CPUPolicy::IEW iew;
613 /** The commit stage. */
614 typename CPUPolicy::Commit commit;
616 /** The register file. */
617 typename CPUPolicy::RegFile regFile;
619 /** The free list. */
620 typename CPUPolicy::FreeList freeList;
622 /** The rename map. */
623 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
625 /** The commit rename map. */
626 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
628 /** The re-order buffer. */
629 typename CPUPolicy::ROB rob;
631 /** Active Threads List */
632 std::list<ThreadID> activeThreads;
634 /** Integer Register Scoreboard */
635 Scoreboard scoreboard;
637 TheISA::ISA isa[Impl::MaxThreads];
639 /** Instruction port. Note that it has to appear after the fetch stage. */
640 IcachePort icachePort;
642 /** Data port. Note that it has to appear after the iew stages */
643 DcachePort dcachePort;
646 /** Enum to give each stage a specific index, so when calling
647 * activateStage() or deactivateStage(), they can specify which stage
648 * is being activated/deactivated.
658 /** Typedefs from the Impl to get the structs that each of the
659 * time buffers should use.
661 typedef typename CPUPolicy::TimeStruct TimeStruct;
663 typedef typename CPUPolicy::FetchStruct FetchStruct;
665 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
667 typedef typename CPUPolicy::RenameStruct RenameStruct;
669 typedef typename CPUPolicy::IEWStruct IEWStruct;
671 /** The main time buffer to do backwards communication. */
672 TimeBuffer<TimeStruct> timeBuffer;
674 /** The fetch stage's instruction queue. */
675 TimeBuffer<FetchStruct> fetchQueue;
677 /** The decode stage's instruction queue. */
678 TimeBuffer<DecodeStruct> decodeQueue;
680 /** The rename stage's instruction queue. */
681 TimeBuffer<RenameStruct> renameQueue;
683 /** The IEW stage's instruction queue. */
684 TimeBuffer<IEWStruct> iewQueue;
687 /** The activity recorder; used to tell if the CPU has any
688 * activity remaining or if it can go to idle and deschedule
691 ActivityRecorder activityRec;
694 /** Records that there was time buffer activity this cycle. */
695 void activityThisCycle() { activityRec.activity(); }
697 /** Changes a stage's status to active within the activity recorder. */
698 void activateStage(const StageIdx idx)
699 { activityRec.activateStage(idx); }
701 /** Changes a stage's status to inactive within the activity recorder. */
702 void deactivateStage(const StageIdx idx)
703 { activityRec.deactivateStage(idx); }
705 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
708 virtual void wakeup();
710 /** Gets a free thread id. Use if thread ids change across system. */
711 ThreadID getFreeTid();
714 /** Returns a pointer to a thread context. */
718 return thread[tid]->getTC();
721 /** The global sequence number counter. */
722 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
724 /** Pointer to the checker, which can dynamically verify
725 * instruction results at run time. This can be set to NULL if it
728 Checker<Impl> *checker;
730 /** Pointer to the system. */
733 /** DrainManager to notify when draining has completed. */
734 DrainManager *drainManager;
736 /** Counter of how many stages have completed draining. */
739 /** Pointers to all of the threads in the CPU. */
740 std::vector<Thread *> thread;
742 /** Whether or not the CPU should defer its registration. */
743 bool deferRegistration;
745 /** Is there a context switch pending? */
748 /** Threads Scheduled to Enter CPU */
749 std::list<int> cpuWaitList;
751 /** The cycle that the CPU was last running, used for statistics. */
752 Cycles lastRunningCycle;
754 /** The cycle that the CPU was last activated by a new thread*/
755 Tick lastActivatedCycle;
757 /** Mapping for system thread id to cpu id */
758 std::map<ThreadID, unsigned> threadMap;
760 /** Available thread ids in the cpu*/
761 std::vector<ThreadID> tids;
763 /** CPU read function, forwards read to LSQ. */
764 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
765 uint8_t *data, int load_idx)
767 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
771 /** CPU write function, forwards write to LSQ. */
772 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
773 uint8_t *data, int store_idx)
775 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
779 /** Used by the fetch unit to get a hold of the instruction port. */
780 virtual CpuPort &getInstPort() { return icachePort; }
782 /** Get the dcache port (used to find block size for translations). */
783 virtual CpuPort &getDataPort() { return dcachePort; }
787 /** Temporary fix for the lock flag, works in the UP case. */
790 /** Stat for total number of times the CPU is descheduled. */
791 Stats::Scalar timesIdled;
792 /** Stat for total number of cycles the CPU spends descheduled. */
793 Stats::Scalar idleCycles;
794 /** Stat for total number of cycles the CPU spends descheduled due to a
795 * quiesce operation or waiting for an interrupt. */
796 Stats::Scalar quiesceCycles;
797 /** Stat for the number of committed instructions per thread. */
798 Stats::Vector committedInsts;
799 /** Stat for the number of committed ops (including micro ops) per thread. */
800 Stats::Vector committedOps;
801 /** Stat for the total number of committed instructions. */
802 Stats::Scalar totalCommittedInsts;
803 /** Stat for the CPI per thread. */
805 /** Stat for the total CPI. */
806 Stats::Formula totalCpi;
807 /** Stat for the IPC per thread. */
809 /** Stat for the total IPC. */
810 Stats::Formula totalIpc;
812 //number of integer register file accesses
813 Stats::Scalar intRegfileReads;
814 Stats::Scalar intRegfileWrites;
815 //number of float register file accesses
816 Stats::Scalar fpRegfileReads;
817 Stats::Scalar fpRegfileWrites;
819 Stats::Scalar miscRegfileReads;
820 Stats::Scalar miscRegfileWrites;
823 #endif // __CPU_O3_CPU_HH__