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47 #ifndef __CPU_O3_CPU_HH__
48 #define __CPU_O3_CPU_HH__
56 #include "arch/types.hh"
57 #include "base/statistics.hh"
58 #include "config/the_isa.hh"
59 #include "cpu/o3/comm.hh"
60 #include "cpu/o3/cpu_policy.hh"
61 #include "cpu/o3/scoreboard.hh"
62 #include "cpu/o3/thread_state.hh"
63 #include "cpu/activity.hh"
64 #include "cpu/base.hh"
65 #include "cpu/simple_thread.hh"
66 #include "cpu/timebuf.hh"
67 //#include "cpu/o3/thread_context.hh"
68 #include "params/DerivO3CPU.hh"
69 #include "sim/process.hh"
75 class O3ThreadContext;
83 class BaseO3CPU : public BaseCPU
85 //Stuff that's pretty ISA independent will go here.
87 BaseO3CPU(BaseCPUParams *params);
93 * FullO3CPU class, has each of the stages (fetch through commit)
94 * within it, as well as all of the time buffers between stages. The
95 * tick() function for the CPU is defined here.
98 class FullO3CPU : public BaseO3CPU
101 // Typedefs from the Impl here.
102 typedef typename Impl::CPUPol CPUPolicy;
103 typedef typename Impl::DynInstPtr DynInstPtr;
104 typedef typename Impl::O3CPU O3CPU;
106 typedef O3ThreadState<Impl> ImplState;
107 typedef O3ThreadState<Impl> Thread;
109 typedef typename std::list<DynInstPtr>::iterator ListIt;
111 friend class O3ThreadContext<Impl>;
125 /** Overall CPU status. */
131 * IcachePort class for instruction fetch.
133 class IcachePort : public MasterPort
136 /** Pointer to fetch. */
137 DefaultFetch<Impl> *fetch;
140 /** Default constructor. */
141 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
142 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
147 /** Timing version of receive. Handles setting fetch to the
148 * proper status to start fetching. */
149 virtual bool recvTimingResp(PacketPtr pkt);
150 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
152 /** Handles doing a retry of a failed fetch. */
153 virtual void recvRetry();
157 * DcachePort class for the load/store queue.
159 class DcachePort : public MasterPort
163 /** Pointer to LSQ. */
165 FullO3CPU<Impl> *cpu;
168 /** Default constructor. */
169 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
170 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq),
176 /** Timing version of receive. Handles writing back and
177 * completing the load or store that has returned from
179 virtual bool recvTimingResp(PacketPtr pkt);
180 virtual void recvTimingSnoopReq(PacketPtr pkt);
182 virtual void recvFunctionalSnoop(PacketPtr pkt)
184 // @todo: Is there a need for potential invalidation here?
187 /** Handles doing a retry of the previous send. */
188 virtual void recvRetry();
191 * As this CPU requires snooping to maintain the load store queue
192 * change the behaviour from the base CPU port.
194 * @return true since we have to snoop
196 virtual bool isSnooping() const { return true; }
199 class TickEvent : public Event
202 /** Pointer to the CPU. */
203 FullO3CPU<Impl> *cpu;
206 /** Constructs a tick event. */
207 TickEvent(FullO3CPU<Impl> *c);
209 /** Processes a tick event, calling tick() on the CPU. */
211 /** Returns the description of the tick event. */
212 const char *description() const;
215 /** The tick event used for scheduling CPU ticks. */
218 /** Schedule tick event, regardless of its current state. */
219 void scheduleTickEvent(Cycles delay)
221 if (tickEvent.squashed())
222 reschedule(tickEvent, clockEdge(delay));
223 else if (!tickEvent.scheduled())
224 schedule(tickEvent, clockEdge(delay));
227 /** Unschedule tick event, regardless of its current state. */
228 void unscheduleTickEvent()
230 if (tickEvent.scheduled())
235 * Check if the pipeline has drained and signal the DrainManager.
237 * This method checks if a drain has been requested and if the CPU
238 * has drained successfully (i.e., there are no instructions in
239 * the pipeline). If the CPU has drained, it deschedules the tick
240 * event and signals the drain manager.
242 * @return False if a drain hasn't been requested or the CPU
243 * hasn't drained, true otherwise.
248 * Perform sanity checks after a drain.
250 * This method is called from drain() when it has determined that
251 * the CPU is fully drained when gem5 is compiled with the NDEBUG
252 * macro undefined. The intention of this method is to do more
253 * extensive tests than the isDrained() method to weed out any
256 void drainSanityCheck() const;
258 /** Check if a system is in a drained state. */
259 bool isDrained() const;
262 /** Constructs a CPU with the given parameters. */
263 FullO3CPU(DerivO3CPUParams *params);
267 /** Registers statistics. */
270 ProbePointArg<PacketPtr> *ppInstAccessComplete;
271 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
273 /** Register probe points. */
274 void regProbePoints();
276 void demapPage(Addr vaddr, uint64_t asn)
278 this->itb->demapPage(vaddr, asn);
279 this->dtb->demapPage(vaddr, asn);
282 void demapInstPage(Addr vaddr, uint64_t asn)
284 this->itb->demapPage(vaddr, asn);
287 void demapDataPage(Addr vaddr, uint64_t asn)
289 this->dtb->demapPage(vaddr, asn);
292 /** Ticks CPU, calling tick() on each stage, and checking the overall
293 * activity to see if the CPU should deschedule itself.
297 /** Initialize the CPU */
302 /** Returns the Number of Active Threads in the CPU */
303 int numActiveThreads()
304 { return activeThreads.size(); }
306 /** Add Thread to Active Threads List */
307 void activateThread(ThreadID tid);
309 /** Remove Thread from Active Threads List */
310 void deactivateThread(ThreadID tid);
312 /** Setup CPU to insert a thread's context */
313 void insertThread(ThreadID tid);
315 /** Remove all of a thread's context from CPU */
316 void removeThread(ThreadID tid);
318 /** Count the Total Instructions Committed in the CPU. */
319 virtual Counter totalInsts() const;
321 /** Count the Total Ops (including micro ops) committed in the CPU. */
322 virtual Counter totalOps() const;
324 /** Add Thread to Active Threads List. */
325 void activateContext(ThreadID tid);
327 /** Remove Thread from Active Threads List */
328 void suspendContext(ThreadID tid);
330 /** Remove Thread from Active Threads List &&
331 * Remove Thread Context from CPU.
333 void haltContext(ThreadID tid);
335 /** Update The Order In Which We Process Threads. */
336 void updateThreadPriority();
338 /** Is the CPU draining? */
339 bool isDraining() const { return getDrainState() == Drainable::Draining; }
341 void serializeThread(std::ostream &os, ThreadID tid);
343 void unserializeThread(Checkpoint *cp, const std::string §ion,
347 /** Executes a syscall.
348 * @todo: Determine if this needs to be virtual.
350 void syscall(int64_t callnum, ThreadID tid);
352 /** Starts draining the CPU's pipeline of all instructions in
353 * order to stop all memory accesses. */
354 unsigned int drain(DrainManager *drain_manager);
356 /** Resumes execution after a drain. */
360 * Commit has reached a safe point to drain a thread.
362 * Commit calls this method to inform the pipeline that it has
363 * reached a point where it is not executed microcode and is about
364 * to squash uncommitted instructions to fully drain the pipeline.
366 void commitDrained(ThreadID tid);
368 /** Switches out this CPU. */
369 virtual void switchOut();
371 /** Takes over from another CPU. */
372 virtual void takeOverFrom(BaseCPU *oldCPU);
374 void verifyMemoryMode() const;
376 /** Get the current instruction sequence number, and increment it. */
377 InstSeqNum getAndIncrementInstSeq()
378 { return globalSeqNum++; }
380 /** Traps to handle given fault. */
381 void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
383 /** HW return from error interrupt. */
384 Fault hwrei(ThreadID tid);
386 bool simPalCheck(int palFunc, ThreadID tid);
388 /** Returns the Fault for any valid interrupt. */
389 Fault getInterrupts();
391 /** Processes any an interrupt fault. */
392 void processInterrupts(const Fault &interrupt);
394 /** Halts the CPU. */
395 void halt() { panic("Halt not implemented!\n"); }
397 /** Check if this address is a valid instruction address. */
398 bool validInstAddr(Addr addr) { return true; }
400 /** Check if this address is a valid data address. */
401 bool validDataAddr(Addr addr) { return true; }
403 /** Register accessors. Index refers to the physical register index. */
405 /** Reads a miscellaneous register. */
406 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
408 /** Reads a misc. register, including any side effects the read
409 * might have as defined by the architecture.
411 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
413 /** Sets a miscellaneous register. */
414 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
417 /** Sets a misc. register, including any side effects the write
418 * might have as defined by the architecture.
420 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
423 uint64_t readIntReg(int reg_idx);
425 TheISA::FloatReg readFloatReg(int reg_idx);
427 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
429 TheISA::CCReg readCCReg(int reg_idx);
431 void setIntReg(int reg_idx, uint64_t val);
433 void setFloatReg(int reg_idx, TheISA::FloatReg val);
435 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
437 void setCCReg(int reg_idx, TheISA::CCReg val);
439 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
441 float readArchFloatReg(int reg_idx, ThreadID tid);
443 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
445 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
447 /** Architectural register accessors. Looks up in the commit
448 * rename table to obtain the true physical index of the
449 * architected register first, then accesses that physical
452 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
454 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
456 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
458 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
460 /** Sets the commit PC state of a specific thread. */
461 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
463 /** Reads the commit PC state of a specific thread. */
464 TheISA::PCState pcState(ThreadID tid);
466 /** Reads the commit PC of a specific thread. */
467 Addr instAddr(ThreadID tid);
469 /** Reads the commit micro PC of a specific thread. */
470 MicroPC microPC(ThreadID tid);
472 /** Reads the next PC of a specific thread. */
473 Addr nextInstAddr(ThreadID tid);
475 /** Initiates a squash of all in-flight instructions for a given
476 * thread. The source of the squash is an external update of
477 * state through the TC.
479 void squashFromTC(ThreadID tid);
481 /** Function to add instruction onto the head of the list of the
482 * instructions. Used when new instructions are fetched.
484 ListIt addInst(DynInstPtr &inst);
486 /** Function to tell the CPU that an instruction has completed. */
487 void instDone(ThreadID tid, DynInstPtr &inst);
489 /** Remove an instruction from the front end of the list. There's
490 * no restriction on location of the instruction.
492 void removeFrontInst(DynInstPtr &inst);
494 /** Remove all instructions that are not currently in the ROB.
495 * There's also an option to not squash delay slot instructions.*/
496 void removeInstsNotInROB(ThreadID tid);
498 /** Remove all instructions younger than the given sequence number. */
499 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
501 /** Removes the instruction pointed to by the iterator. */
502 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
504 /** Cleans up all instructions on the remove list. */
505 void cleanUpRemovedInsts();
507 /** Debug function to print all instructions on the list. */
512 /** Count of total number of dynamic instructions in flight. */
516 /** List of all the instructions in flight. */
517 std::list<DynInstPtr> instList;
519 /** List of all the instructions that will be removed at the end of this
522 std::queue<ListIt> removeList;
525 /** Debug structure to keep track of the sequence numbers still in
528 std::set<InstSeqNum> snList;
531 /** Records if instructions need to be removed this cycle due to
532 * being retired or squashed.
534 bool removeInstsThisCycle;
537 /** The fetch stage. */
538 typename CPUPolicy::Fetch fetch;
540 /** The decode stage. */
541 typename CPUPolicy::Decode decode;
543 /** The dispatch stage. */
544 typename CPUPolicy::Rename rename;
546 /** The issue/execute/writeback stages. */
547 typename CPUPolicy::IEW iew;
549 /** The commit stage. */
550 typename CPUPolicy::Commit commit;
552 /** The register file. */
555 /** The free list. */
556 typename CPUPolicy::FreeList freeList;
558 /** The rename map. */
559 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
561 /** The commit rename map. */
562 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
564 /** The re-order buffer. */
565 typename CPUPolicy::ROB rob;
567 /** Active Threads List */
568 std::list<ThreadID> activeThreads;
570 /** Integer Register Scoreboard */
571 Scoreboard scoreboard;
573 std::vector<TheISA::ISA *> isa;
575 /** Instruction port. Note that it has to appear after the fetch stage. */
576 IcachePort icachePort;
578 /** Data port. Note that it has to appear after the iew stages */
579 DcachePort dcachePort;
582 /** Enum to give each stage a specific index, so when calling
583 * activateStage() or deactivateStage(), they can specify which stage
584 * is being activated/deactivated.
594 /** Typedefs from the Impl to get the structs that each of the
595 * time buffers should use.
597 typedef typename CPUPolicy::TimeStruct TimeStruct;
599 typedef typename CPUPolicy::FetchStruct FetchStruct;
601 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
603 typedef typename CPUPolicy::RenameStruct RenameStruct;
605 typedef typename CPUPolicy::IEWStruct IEWStruct;
607 /** The main time buffer to do backwards communication. */
608 TimeBuffer<TimeStruct> timeBuffer;
610 /** The fetch stage's instruction queue. */
611 TimeBuffer<FetchStruct> fetchQueue;
613 /** The decode stage's instruction queue. */
614 TimeBuffer<DecodeStruct> decodeQueue;
616 /** The rename stage's instruction queue. */
617 TimeBuffer<RenameStruct> renameQueue;
619 /** The IEW stage's instruction queue. */
620 TimeBuffer<IEWStruct> iewQueue;
623 /** The activity recorder; used to tell if the CPU has any
624 * activity remaining or if it can go to idle and deschedule
627 ActivityRecorder activityRec;
630 /** Records that there was time buffer activity this cycle. */
631 void activityThisCycle() { activityRec.activity(); }
633 /** Changes a stage's status to active within the activity recorder. */
634 void activateStage(const StageIdx idx)
635 { activityRec.activateStage(idx); }
637 /** Changes a stage's status to inactive within the activity recorder. */
638 void deactivateStage(const StageIdx idx)
639 { activityRec.deactivateStage(idx); }
641 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
644 virtual void wakeup();
646 /** Gets a free thread id. Use if thread ids change across system. */
647 ThreadID getFreeTid();
650 /** Returns a pointer to a thread context. */
654 return thread[tid]->getTC();
657 /** The global sequence number counter. */
658 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
660 /** Pointer to the checker, which can dynamically verify
661 * instruction results at run time. This can be set to NULL if it
664 Checker<Impl> *checker;
666 /** Pointer to the system. */
669 /** DrainManager to notify when draining has completed. */
670 DrainManager *drainManager;
672 /** Pointers to all of the threads in the CPU. */
673 std::vector<Thread *> thread;
675 /** Threads Scheduled to Enter CPU */
676 std::list<int> cpuWaitList;
678 /** The cycle that the CPU was last running, used for statistics. */
679 Cycles lastRunningCycle;
681 /** The cycle that the CPU was last activated by a new thread*/
682 Tick lastActivatedCycle;
684 /** Mapping for system thread id to cpu id */
685 std::map<ThreadID, unsigned> threadMap;
687 /** Available thread ids in the cpu*/
688 std::vector<ThreadID> tids;
690 /** CPU read function, forwards read to LSQ. */
691 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
692 uint8_t *data, int load_idx)
694 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
698 /** CPU write function, forwards write to LSQ. */
699 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
700 uint8_t *data, int store_idx)
702 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
706 /** Used by the fetch unit to get a hold of the instruction port. */
707 virtual MasterPort &getInstPort() { return icachePort; }
709 /** Get the dcache port (used to find block size for translations). */
710 virtual MasterPort &getDataPort() { return dcachePort; }
712 /** Stat for total number of times the CPU is descheduled. */
713 Stats::Scalar timesIdled;
714 /** Stat for total number of cycles the CPU spends descheduled. */
715 Stats::Scalar idleCycles;
716 /** Stat for total number of cycles the CPU spends descheduled due to a
717 * quiesce operation or waiting for an interrupt. */
718 Stats::Scalar quiesceCycles;
719 /** Stat for the number of committed instructions per thread. */
720 Stats::Vector committedInsts;
721 /** Stat for the number of committed ops (including micro ops) per thread. */
722 Stats::Vector committedOps;
723 /** Stat for the CPI per thread. */
725 /** Stat for the total CPI. */
726 Stats::Formula totalCpi;
727 /** Stat for the IPC per thread. */
729 /** Stat for the total IPC. */
730 Stats::Formula totalIpc;
732 //number of integer register file accesses
733 Stats::Scalar intRegfileReads;
734 Stats::Scalar intRegfileWrites;
735 //number of float register file accesses
736 Stats::Scalar fpRegfileReads;
737 Stats::Scalar fpRegfileWrites;
738 //number of CC register file accesses
739 Stats::Scalar ccRegfileReads;
740 Stats::Scalar ccRegfileWrites;
742 Stats::Scalar miscRegfileReads;
743 Stats::Scalar miscRegfileWrites;
746 #endif // __CPU_O3_CPU_HH__