2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
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32 #ifndef __CPU_O3_CPU_HH__
33 #define __CPU_O3_CPU_HH__
41 #include "arch/types.hh"
42 #include "base/statistics.hh"
43 #include "base/timebuf.hh"
44 #include "config/full_system.hh"
45 #include "config/use_checker.hh"
46 #include "cpu/activity.hh"
47 #include "cpu/base.hh"
48 #include "cpu/simple_thread.hh"
49 #include "cpu/o3/comm.hh"
50 #include "cpu/o3/cpu_policy.hh"
51 #include "cpu/o3/scoreboard.hh"
52 #include "cpu/o3/thread_state.hh"
53 //#include "cpu/o3/thread_context.hh"
54 #include "sim/process.hh"
56 #include "params/DerivO3CPU.hh"
62 class O3ThreadContext;
70 class BaseO3CPU : public BaseCPU
72 //Stuff that's pretty ISA independent will go here.
74 BaseO3CPU(BaseCPUParams *params);
80 * FullO3CPU class, has each of the stages (fetch through commit)
81 * within it, as well as all of the time buffers between stages. The
82 * tick() function for the CPU is defined here.
85 class FullO3CPU : public BaseO3CPU
88 // Typedefs from the Impl here.
89 typedef typename Impl::CPUPol CPUPolicy;
90 typedef typename Impl::DynInstPtr DynInstPtr;
91 typedef typename Impl::O3CPU O3CPU;
93 typedef O3ThreadState<Impl> ImplState;
94 typedef O3ThreadState<Impl> Thread;
96 typedef typename std::list<DynInstPtr>::iterator ListIt;
98 friend class O3ThreadContext<Impl>;
112 /** Overall CPU status. */
115 /** Per-thread status in CPU, used for SMT. */
116 Status _threadStatus[Impl::MaxThreads];
119 class TickEvent : public Event
122 /** Pointer to the CPU. */
123 FullO3CPU<Impl> *cpu;
126 /** Constructs a tick event. */
127 TickEvent(FullO3CPU<Impl> *c);
129 /** Processes a tick event, calling tick() on the CPU. */
131 /** Returns the description of the tick event. */
132 const char *description() const;
135 /** The tick event used for scheduling CPU ticks. */
138 /** Schedule tick event, regardless of its current state. */
139 void scheduleTickEvent(int delay)
141 if (tickEvent.squashed())
142 reschedule(tickEvent, nextCycle(curTick + ticks(delay)));
143 else if (!tickEvent.scheduled())
144 schedule(tickEvent, nextCycle(curTick + ticks(delay)));
147 /** Unschedule tick event, regardless of its current state. */
148 void unscheduleTickEvent()
150 if (tickEvent.scheduled())
154 class ActivateThreadEvent : public Event
157 /** Number of Thread to Activate */
160 /** Pointer to the CPU. */
161 FullO3CPU<Impl> *cpu;
164 /** Constructs the event. */
165 ActivateThreadEvent();
167 /** Initialize Event */
168 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
170 /** Processes the event, calling activateThread() on the CPU. */
173 /** Returns the description of the event. */
174 const char *description() const;
177 /** Schedule thread to activate , regardless of its current state. */
178 void scheduleActivateThreadEvent(int tid, int delay)
180 // Schedule thread to activate, regardless of its current state.
181 if (activateThreadEvent[tid].squashed())
182 reschedule(activateThreadEvent[tid],
183 nextCycle(curTick + ticks(delay)));
184 else if (!activateThreadEvent[tid].scheduled())
185 schedule(activateThreadEvent[tid],
186 nextCycle(curTick + ticks(delay)));
189 /** Unschedule actiavte thread event, regardless of its current state. */
190 void unscheduleActivateThreadEvent(int tid)
192 if (activateThreadEvent[tid].scheduled())
193 activateThreadEvent[tid].squash();
196 /** The tick event used for scheduling CPU ticks. */
197 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
199 class DeallocateContextEvent : public Event
202 /** Number of Thread to deactivate */
205 /** Should the thread be removed from the CPU? */
208 /** Pointer to the CPU. */
209 FullO3CPU<Impl> *cpu;
212 /** Constructs the event. */
213 DeallocateContextEvent();
215 /** Initialize Event */
216 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
218 /** Processes the event, calling activateThread() on the CPU. */
221 /** Sets whether the thread should also be removed from the CPU. */
222 void setRemove(bool _remove) { remove = _remove; }
224 /** Returns the description of the event. */
225 const char *description() const;
228 /** Schedule cpu to deallocate thread context.*/
229 void scheduleDeallocateContextEvent(int tid, bool remove, int delay)
231 // Schedule thread to activate, regardless of its current state.
232 if (deallocateContextEvent[tid].squashed())
233 reschedule(deallocateContextEvent[tid],
234 nextCycle(curTick + ticks(delay)));
235 else if (!deallocateContextEvent[tid].scheduled())
236 schedule(deallocateContextEvent[tid],
237 nextCycle(curTick + ticks(delay)));
240 /** Unschedule thread deallocation in CPU */
241 void unscheduleDeallocateContextEvent(int tid)
243 if (deallocateContextEvent[tid].scheduled())
244 deallocateContextEvent[tid].squash();
247 /** The tick event used for scheduling CPU ticks. */
248 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
251 /** Constructs a CPU with the given parameters. */
252 FullO3CPU(DerivO3CPUParams *params);
256 /** Registers statistics. */
259 void demapPage(Addr vaddr, uint64_t asn)
261 this->itb->demapPage(vaddr, asn);
262 this->dtb->demapPage(vaddr, asn);
265 void demapInstPage(Addr vaddr, uint64_t asn)
267 this->itb->demapPage(vaddr, asn);
270 void demapDataPage(Addr vaddr, uint64_t asn)
272 this->dtb->demapPage(vaddr, asn);
275 /** Returns a specific port. */
276 Port *getPort(const std::string &if_name, int idx);
278 /** Ticks CPU, calling tick() on each stage, and checking the overall
279 * activity to see if the CPU should deschedule itself.
283 /** Initialize the CPU */
286 /** Returns the Number of Active Threads in the CPU */
287 int numActiveThreads()
288 { return activeThreads.size(); }
290 /** Add Thread to Active Threads List */
291 void activateThread(unsigned tid);
293 /** Remove Thread from Active Threads List */
294 void deactivateThread(unsigned tid);
296 /** Setup CPU to insert a thread's context */
297 void insertThread(unsigned tid);
299 /** Remove all of a thread's context from CPU */
300 void removeThread(unsigned tid);
302 /** Count the Total Instructions Committed in the CPU. */
303 virtual Counter totalInstructions() const
307 for (int i=0; i < thread.size(); i++)
308 total += thread[i]->numInst;
313 /** Add Thread to Active Threads List. */
314 void activateContext(int tid, int delay);
316 /** Remove Thread from Active Threads List */
317 void suspendContext(int tid);
319 /** Remove Thread from Active Threads List &&
320 * Possibly Remove Thread Context from CPU.
322 bool deallocateContext(int tid, bool remove, int delay = 1);
324 /** Remove Thread from Active Threads List &&
325 * Remove Thread Context from CPU.
327 void haltContext(int tid);
329 /** Activate a Thread When CPU Resources are Available. */
330 void activateWhenReady(int tid);
332 /** Add or Remove a Thread Context in the CPU. */
333 void doContextSwitch();
335 /** Update The Order In Which We Process Threads. */
336 void updateThreadPriority();
338 /** Serialize state. */
339 virtual void serialize(std::ostream &os);
341 /** Unserialize from a checkpoint. */
342 virtual void unserialize(Checkpoint *cp, const std::string §ion);
346 /** Executes a syscall.
347 * @todo: Determine if this needs to be virtual.
349 void syscall(int64_t callnum, int tid);
352 /** Starts draining the CPU's pipeline of all instructions in
353 * order to stop all memory accesses. */
354 virtual unsigned int drain(Event *drain_event);
356 /** Resumes execution after a drain. */
357 virtual void resume();
359 /** Signals to this CPU that a stage has completed switching out. */
360 void signalDrained();
362 /** Switches out this CPU. */
363 virtual void switchOut();
365 /** Takes over from another CPU. */
366 virtual void takeOverFrom(BaseCPU *oldCPU);
368 /** Get the current instruction sequence number, and increment it. */
369 InstSeqNum getAndIncrementInstSeq()
370 { return globalSeqNum++; }
372 /** Traps to handle given fault. */
373 void trap(Fault fault, unsigned tid);
376 /** HW return from error interrupt. */
377 Fault hwrei(unsigned tid);
379 bool simPalCheck(int palFunc, unsigned tid);
381 /** Returns the Fault for any valid interrupt. */
382 Fault getInterrupts();
384 /** Processes any an interrupt fault. */
385 void processInterrupts(Fault interrupt);
387 /** Halts the CPU. */
388 void halt() { panic("Halt not implemented!\n"); }
390 /** Update the Virt and Phys ports of all ThreadContexts to
391 * reflect change in memory connections. */
392 void updateMemPorts();
394 /** Check if this address is a valid instruction address. */
395 bool validInstAddr(Addr addr) { return true; }
397 /** Check if this address is a valid data address. */
398 bool validDataAddr(Addr addr) { return true; }
400 /** Get instruction asid. */
401 int getInstAsid(unsigned tid)
402 { return regFile.miscRegs[tid].getInstAsid(); }
404 /** Get data asid. */
405 int getDataAsid(unsigned tid)
406 { return regFile.miscRegs[tid].getDataAsid(); }
408 /** Get instruction asid. */
409 int getInstAsid(unsigned tid)
410 { return thread[tid]->getInstAsid(); }
412 /** Get data asid. */
413 int getDataAsid(unsigned tid)
414 { return thread[tid]->getDataAsid(); }
418 /** Register accessors. Index refers to the physical register index. */
420 /** Reads a miscellaneous register. */
421 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
423 /** Reads a misc. register, including any side effects the read
424 * might have as defined by the architecture.
426 TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
428 /** Sets a miscellaneous register. */
429 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
431 /** Sets a misc. register, including any side effects the write
432 * might have as defined by the architecture.
434 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
437 uint64_t readIntReg(int reg_idx);
439 TheISA::FloatReg readFloatReg(int reg_idx);
441 TheISA::FloatReg readFloatReg(int reg_idx, int width);
443 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
445 TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
447 void setIntReg(int reg_idx, uint64_t val);
449 void setFloatReg(int reg_idx, TheISA::FloatReg val);
451 void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
453 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
455 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
457 uint64_t readArchIntReg(int reg_idx, unsigned tid);
459 float readArchFloatRegSingle(int reg_idx, unsigned tid);
461 double readArchFloatRegDouble(int reg_idx, unsigned tid);
463 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
465 /** Architectural register accessors. Looks up in the commit
466 * rename table to obtain the true physical index of the
467 * architected register first, then accesses that physical
470 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
472 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
474 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
476 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
478 /** Reads the commit PC of a specific thread. */
479 Addr readPC(unsigned tid);
481 /** Sets the commit PC of a specific thread. */
482 void setPC(Addr new_PC, unsigned tid);
484 /** Reads the commit micro PC of a specific thread. */
485 Addr readMicroPC(unsigned tid);
487 /** Sets the commmit micro PC of a specific thread. */
488 void setMicroPC(Addr new_microPC, unsigned tid);
490 /** Reads the next PC of a specific thread. */
491 Addr readNextPC(unsigned tid);
493 /** Sets the next PC of a specific thread. */
494 void setNextPC(Addr val, unsigned tid);
496 /** Reads the next NPC of a specific thread. */
497 Addr readNextNPC(unsigned tid);
499 /** Sets the next NPC of a specific thread. */
500 void setNextNPC(Addr val, unsigned tid);
502 /** Reads the commit next micro PC of a specific thread. */
503 Addr readNextMicroPC(unsigned tid);
505 /** Sets the commit next micro PC of a specific thread. */
506 void setNextMicroPC(Addr val, unsigned tid);
508 /** Initiates a squash of all in-flight instructions for a given
509 * thread. The source of the squash is an external update of
510 * state through the TC.
512 void squashFromTC(unsigned tid);
514 /** Function to add instruction onto the head of the list of the
515 * instructions. Used when new instructions are fetched.
517 ListIt addInst(DynInstPtr &inst);
519 /** Function to tell the CPU that an instruction has completed. */
520 void instDone(unsigned tid);
522 /** Add Instructions to the CPU Remove List*/
523 void addToRemoveList(DynInstPtr &inst);
525 /** Remove an instruction from the front end of the list. There's
526 * no restriction on location of the instruction.
528 void removeFrontInst(DynInstPtr &inst);
530 /** Remove all instructions that are not currently in the ROB.
531 * There's also an option to not squash delay slot instructions.*/
532 void removeInstsNotInROB(unsigned tid);
534 /** Remove all instructions younger than the given sequence number. */
535 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
537 /** Removes the instruction pointed to by the iterator. */
538 inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
540 /** Cleans up all instructions on the remove list. */
541 void cleanUpRemovedInsts();
543 /** Debug function to print all instructions on the list. */
548 /** Count of total number of dynamic instructions in flight. */
552 /** List of all the instructions in flight. */
553 std::list<DynInstPtr> instList;
555 /** List of all the instructions that will be removed at the end of this
558 std::queue<ListIt> removeList;
561 /** Debug structure to keep track of the sequence numbers still in
564 std::set<InstSeqNum> snList;
567 /** Records if instructions need to be removed this cycle due to
568 * being retired or squashed.
570 bool removeInstsThisCycle;
573 /** The fetch stage. */
574 typename CPUPolicy::Fetch fetch;
576 /** The decode stage. */
577 typename CPUPolicy::Decode decode;
579 /** The dispatch stage. */
580 typename CPUPolicy::Rename rename;
582 /** The issue/execute/writeback stages. */
583 typename CPUPolicy::IEW iew;
585 /** The commit stage. */
586 typename CPUPolicy::Commit commit;
588 /** The register file. */
589 typename CPUPolicy::RegFile regFile;
591 /** The free list. */
592 typename CPUPolicy::FreeList freeList;
594 /** The rename map. */
595 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
597 /** The commit rename map. */
598 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
600 /** The re-order buffer. */
601 typename CPUPolicy::ROB rob;
603 /** Active Threads List */
604 std::list<unsigned> activeThreads;
606 /** Integer Register Scoreboard */
607 Scoreboard scoreboard;
610 /** Enum to give each stage a specific index, so when calling
611 * activateStage() or deactivateStage(), they can specify which stage
612 * is being activated/deactivated.
622 /** Typedefs from the Impl to get the structs that each of the
623 * time buffers should use.
625 typedef typename CPUPolicy::TimeStruct TimeStruct;
627 typedef typename CPUPolicy::FetchStruct FetchStruct;
629 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
631 typedef typename CPUPolicy::RenameStruct RenameStruct;
633 typedef typename CPUPolicy::IEWStruct IEWStruct;
635 /** The main time buffer to do backwards communication. */
636 TimeBuffer<TimeStruct> timeBuffer;
638 /** The fetch stage's instruction queue. */
639 TimeBuffer<FetchStruct> fetchQueue;
641 /** The decode stage's instruction queue. */
642 TimeBuffer<DecodeStruct> decodeQueue;
644 /** The rename stage's instruction queue. */
645 TimeBuffer<RenameStruct> renameQueue;
647 /** The IEW stage's instruction queue. */
648 TimeBuffer<IEWStruct> iewQueue;
651 /** The activity recorder; used to tell if the CPU has any
652 * activity remaining or if it can go to idle and deschedule
655 ActivityRecorder activityRec;
658 /** Records that there was time buffer activity this cycle. */
659 void activityThisCycle() { activityRec.activity(); }
661 /** Changes a stage's status to active within the activity recorder. */
662 void activateStage(const StageIdx idx)
663 { activityRec.activateStage(idx); }
665 /** Changes a stage's status to inactive within the activity recorder. */
666 void deactivateStage(const StageIdx idx)
667 { activityRec.deactivateStage(idx); }
669 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
673 virtual void wakeup();
676 /** Gets a free thread id. Use if thread ids change across system. */
680 /** Returns a pointer to a thread context. */
681 ThreadContext *tcBase(unsigned tid)
683 return thread[tid]->getTC();
686 /** The global sequence number counter. */
687 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
690 /** Pointer to the checker, which can dynamically verify
691 * instruction results at run time. This can be set to NULL if it
694 Checker<DynInstPtr> *checker;
698 /** Pointer to the system. */
701 /** Pointer to physical memory. */
702 PhysicalMemory *physmem;
705 /** Event to call process() on once draining has completed. */
708 /** Counter of how many stages have completed draining. */
711 /** Pointers to all of the threads in the CPU. */
712 std::vector<Thread *> thread;
714 /** Whether or not the CPU should defer its registration. */
715 bool deferRegistration;
717 /** Is there a context switch pending? */
720 /** Threads Scheduled to Enter CPU */
721 std::list<int> cpuWaitList;
723 /** The cycle that the CPU was last running, used for statistics. */
724 Tick lastRunningCycle;
726 /** The cycle that the CPU was last activated by a new thread*/
727 Tick lastActivatedCycle;
729 /** Number of Threads CPU can process */
732 /** Mapping for system thread id to cpu id */
733 std::map<unsigned,unsigned> threadMap;
735 /** Available thread ids in the cpu*/
736 std::vector<unsigned> tids;
738 /** CPU read function, forwards read to LSQ. */
740 Fault read(RequestPtr &req, T &data, int load_idx)
742 return this->iew.ldstQueue.read(req, data, load_idx);
745 /** CPU write function, forwards write to LSQ. */
747 Fault write(RequestPtr &req, T &data, int store_idx)
749 return this->iew.ldstQueue.write(req, data, store_idx);
754 /** Temporary fix for the lock flag, works in the UP case. */
757 /** Stat for total number of times the CPU is descheduled. */
758 Stats::Scalar timesIdled;
759 /** Stat for total number of cycles the CPU spends descheduled. */
760 Stats::Scalar idleCycles;
761 /** Stat for the number of committed instructions per thread. */
762 Stats::Vector committedInsts;
763 /** Stat for the total number of committed instructions. */
764 Stats::Scalar totalCommittedInsts;
765 /** Stat for the CPI per thread. */
767 /** Stat for the total CPI. */
768 Stats::Formula totalCpi;
769 /** Stat for the IPC per thread. */
771 /** Stat for the total IPC. */
772 Stats::Formula totalIpc;
775 #endif // __CPU_O3_CPU_HH__