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47 #ifndef __CPU_O3_CPU_HH__
48 #define __CPU_O3_CPU_HH__
56 #include "arch/types.hh"
57 #include "base/statistics.hh"
58 #include "config/the_isa.hh"
59 #include "cpu/o3/comm.hh"
60 #include "cpu/o3/cpu_policy.hh"
61 #include "cpu/o3/scoreboard.hh"
62 #include "cpu/o3/thread_state.hh"
63 #include "cpu/activity.hh"
64 #include "cpu/base.hh"
65 #include "cpu/simple_thread.hh"
66 #include "cpu/timebuf.hh"
67 //#include "cpu/o3/thread_context.hh"
68 #include "params/DerivO3CPU.hh"
69 #include "sim/process.hh"
75 class O3ThreadContext;
83 class BaseO3CPU : public BaseCPU
85 //Stuff that's pretty ISA independent will go here.
87 BaseO3CPU(BaseCPUParams *params);
93 * FullO3CPU class, has each of the stages (fetch through commit)
94 * within it, as well as all of the time buffers between stages. The
95 * tick() function for the CPU is defined here.
98 class FullO3CPU : public BaseO3CPU
101 // Typedefs from the Impl here.
102 typedef typename Impl::CPUPol CPUPolicy;
103 typedef typename Impl::DynInstPtr DynInstPtr;
104 typedef typename Impl::O3CPU O3CPU;
106 typedef O3ThreadState<Impl> ImplState;
107 typedef O3ThreadState<Impl> Thread;
109 typedef typename std::list<DynInstPtr>::iterator ListIt;
111 friend class O3ThreadContext<Impl>;
125 /** Overall CPU status. */
131 * IcachePort class for instruction fetch.
133 class IcachePort : public MasterPort
136 /** Pointer to fetch. */
137 DefaultFetch<Impl> *fetch;
140 /** Default constructor. */
141 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
142 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
147 /** Timing version of receive. Handles setting fetch to the
148 * proper status to start fetching. */
149 virtual bool recvTimingResp(PacketPtr pkt);
150 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
152 /** Handles doing a retry of a failed fetch. */
153 virtual void recvRetry();
157 * DcachePort class for the load/store queue.
159 class DcachePort : public MasterPort
163 /** Pointer to LSQ. */
167 /** Default constructor. */
168 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
169 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
174 /** Timing version of receive. Handles writing back and
175 * completing the load or store that has returned from
177 virtual bool recvTimingResp(PacketPtr pkt);
178 virtual void recvTimingSnoopReq(PacketPtr pkt);
180 virtual void recvFunctionalSnoop(PacketPtr pkt)
182 // @todo: Is there a need for potential invalidation here?
185 /** Handles doing a retry of the previous send. */
186 virtual void recvRetry();
189 * As this CPU requires snooping to maintain the load store queue
190 * change the behaviour from the base CPU port.
192 * @return true since we have to snoop
194 virtual bool isSnooping() const { return true; }
197 class TickEvent : public Event
200 /** Pointer to the CPU. */
201 FullO3CPU<Impl> *cpu;
204 /** Constructs a tick event. */
205 TickEvent(FullO3CPU<Impl> *c);
207 /** Processes a tick event, calling tick() on the CPU. */
209 /** Returns the description of the tick event. */
210 const char *description() const;
213 /** The tick event used for scheduling CPU ticks. */
216 /** Schedule tick event, regardless of its current state. */
217 void scheduleTickEvent(Cycles delay)
219 if (tickEvent.squashed())
220 reschedule(tickEvent, clockEdge(delay));
221 else if (!tickEvent.scheduled())
222 schedule(tickEvent, clockEdge(delay));
225 /** Unschedule tick event, regardless of its current state. */
226 void unscheduleTickEvent()
228 if (tickEvent.scheduled())
233 * Check if the pipeline has drained and signal the DrainManager.
235 * This method checks if a drain has been requested and if the CPU
236 * has drained successfully (i.e., there are no instructions in
237 * the pipeline). If the CPU has drained, it deschedules the tick
238 * event and signals the drain manager.
240 * @return False if a drain hasn't been requested or the CPU
241 * hasn't drained, true otherwise.
246 * Perform sanity checks after a drain.
248 * This method is called from drain() when it has determined that
249 * the CPU is fully drained when gem5 is compiled with the NDEBUG
250 * macro undefined. The intention of this method is to do more
251 * extensive tests than the isDrained() method to weed out any
254 void drainSanityCheck() const;
256 /** Check if a system is in a drained state. */
257 bool isDrained() const;
260 /** Constructs a CPU with the given parameters. */
261 FullO3CPU(DerivO3CPUParams *params);
265 /** Registers statistics. */
268 ProbePointArg<PacketPtr> *ppInstAccessComplete;
269 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
271 /** Register probe points. */
272 void regProbePoints();
274 void demapPage(Addr vaddr, uint64_t asn)
276 this->itb->demapPage(vaddr, asn);
277 this->dtb->demapPage(vaddr, asn);
280 void demapInstPage(Addr vaddr, uint64_t asn)
282 this->itb->demapPage(vaddr, asn);
285 void demapDataPage(Addr vaddr, uint64_t asn)
287 this->dtb->demapPage(vaddr, asn);
290 /** Ticks CPU, calling tick() on each stage, and checking the overall
291 * activity to see if the CPU should deschedule itself.
295 /** Initialize the CPU */
300 /** Returns the Number of Active Threads in the CPU */
301 int numActiveThreads()
302 { return activeThreads.size(); }
304 /** Add Thread to Active Threads List */
305 void activateThread(ThreadID tid);
307 /** Remove Thread from Active Threads List */
308 void deactivateThread(ThreadID tid);
310 /** Setup CPU to insert a thread's context */
311 void insertThread(ThreadID tid);
313 /** Remove all of a thread's context from CPU */
314 void removeThread(ThreadID tid);
316 /** Count the Total Instructions Committed in the CPU. */
317 virtual Counter totalInsts() const;
319 /** Count the Total Ops (including micro ops) committed in the CPU. */
320 virtual Counter totalOps() const;
322 /** Add Thread to Active Threads List. */
323 void activateContext(ThreadID tid);
325 /** Remove Thread from Active Threads List */
326 void suspendContext(ThreadID tid);
328 /** Remove Thread from Active Threads List &&
329 * Possibly Remove Thread Context from CPU.
331 void deallocateContext(ThreadID tid, bool remove);
333 /** Remove Thread from Active Threads List &&
334 * Remove Thread Context from CPU.
336 void haltContext(ThreadID tid);
338 /** Update The Order In Which We Process Threads. */
339 void updateThreadPriority();
341 /** Is the CPU draining? */
342 bool isDraining() const { return getDrainState() == Drainable::Draining; }
344 void serializeThread(std::ostream &os, ThreadID tid);
346 void unserializeThread(Checkpoint *cp, const std::string §ion,
350 /** Executes a syscall.
351 * @todo: Determine if this needs to be virtual.
353 void syscall(int64_t callnum, ThreadID tid);
355 /** Starts draining the CPU's pipeline of all instructions in
356 * order to stop all memory accesses. */
357 unsigned int drain(DrainManager *drain_manager);
359 /** Resumes execution after a drain. */
363 * Commit has reached a safe point to drain a thread.
365 * Commit calls this method to inform the pipeline that it has
366 * reached a point where it is not executed microcode and is about
367 * to squash uncommitted instructions to fully drain the pipeline.
369 void commitDrained(ThreadID tid);
371 /** Switches out this CPU. */
372 virtual void switchOut();
374 /** Takes over from another CPU. */
375 virtual void takeOverFrom(BaseCPU *oldCPU);
377 void verifyMemoryMode() const;
379 /** Get the current instruction sequence number, and increment it. */
380 InstSeqNum getAndIncrementInstSeq()
381 { return globalSeqNum++; }
383 /** Traps to handle given fault. */
384 void trap(const Fault &fault, ThreadID tid, StaticInstPtr inst);
386 /** HW return from error interrupt. */
387 Fault hwrei(ThreadID tid);
389 bool simPalCheck(int palFunc, ThreadID tid);
391 /** Returns the Fault for any valid interrupt. */
392 Fault getInterrupts();
394 /** Processes any an interrupt fault. */
395 void processInterrupts(const Fault &interrupt);
397 /** Halts the CPU. */
398 void halt() { panic("Halt not implemented!\n"); }
400 /** Check if this address is a valid instruction address. */
401 bool validInstAddr(Addr addr) { return true; }
403 /** Check if this address is a valid data address. */
404 bool validDataAddr(Addr addr) { return true; }
406 /** Register accessors. Index refers to the physical register index. */
408 /** Reads a miscellaneous register. */
409 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
411 /** Reads a misc. register, including any side effects the read
412 * might have as defined by the architecture.
414 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
416 /** Sets a miscellaneous register. */
417 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
420 /** Sets a misc. register, including any side effects the write
421 * might have as defined by the architecture.
423 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
426 uint64_t readIntReg(int reg_idx);
428 TheISA::FloatReg readFloatReg(int reg_idx);
430 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
432 TheISA::CCReg readCCReg(int reg_idx);
434 void setIntReg(int reg_idx, uint64_t val);
436 void setFloatReg(int reg_idx, TheISA::FloatReg val);
438 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
440 void setCCReg(int reg_idx, TheISA::CCReg val);
442 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
444 float readArchFloatReg(int reg_idx, ThreadID tid);
446 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
448 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
450 /** Architectural register accessors. Looks up in the commit
451 * rename table to obtain the true physical index of the
452 * architected register first, then accesses that physical
455 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
457 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
459 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
461 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
463 /** Sets the commit PC state of a specific thread. */
464 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
466 /** Reads the commit PC state of a specific thread. */
467 TheISA::PCState pcState(ThreadID tid);
469 /** Reads the commit PC of a specific thread. */
470 Addr instAddr(ThreadID tid);
472 /** Reads the commit micro PC of a specific thread. */
473 MicroPC microPC(ThreadID tid);
475 /** Reads the next PC of a specific thread. */
476 Addr nextInstAddr(ThreadID tid);
478 /** Initiates a squash of all in-flight instructions for a given
479 * thread. The source of the squash is an external update of
480 * state through the TC.
482 void squashFromTC(ThreadID tid);
484 /** Function to add instruction onto the head of the list of the
485 * instructions. Used when new instructions are fetched.
487 ListIt addInst(DynInstPtr &inst);
489 /** Function to tell the CPU that an instruction has completed. */
490 void instDone(ThreadID tid, DynInstPtr &inst);
492 /** Remove an instruction from the front end of the list. There's
493 * no restriction on location of the instruction.
495 void removeFrontInst(DynInstPtr &inst);
497 /** Remove all instructions that are not currently in the ROB.
498 * There's also an option to not squash delay slot instructions.*/
499 void removeInstsNotInROB(ThreadID tid);
501 /** Remove all instructions younger than the given sequence number. */
502 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
504 /** Removes the instruction pointed to by the iterator. */
505 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
507 /** Cleans up all instructions on the remove list. */
508 void cleanUpRemovedInsts();
510 /** Debug function to print all instructions on the list. */
515 /** Count of total number of dynamic instructions in flight. */
519 /** List of all the instructions in flight. */
520 std::list<DynInstPtr> instList;
522 /** List of all the instructions that will be removed at the end of this
525 std::queue<ListIt> removeList;
528 /** Debug structure to keep track of the sequence numbers still in
531 std::set<InstSeqNum> snList;
534 /** Records if instructions need to be removed this cycle due to
535 * being retired or squashed.
537 bool removeInstsThisCycle;
540 /** The fetch stage. */
541 typename CPUPolicy::Fetch fetch;
543 /** The decode stage. */
544 typename CPUPolicy::Decode decode;
546 /** The dispatch stage. */
547 typename CPUPolicy::Rename rename;
549 /** The issue/execute/writeback stages. */
550 typename CPUPolicy::IEW iew;
552 /** The commit stage. */
553 typename CPUPolicy::Commit commit;
555 /** The register file. */
558 /** The free list. */
559 typename CPUPolicy::FreeList freeList;
561 /** The rename map. */
562 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
564 /** The commit rename map. */
565 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
567 /** The re-order buffer. */
568 typename CPUPolicy::ROB rob;
570 /** Active Threads List */
571 std::list<ThreadID> activeThreads;
573 /** Integer Register Scoreboard */
574 Scoreboard scoreboard;
576 std::vector<TheISA::ISA *> isa;
578 /** Instruction port. Note that it has to appear after the fetch stage. */
579 IcachePort icachePort;
581 /** Data port. Note that it has to appear after the iew stages */
582 DcachePort dcachePort;
585 /** Enum to give each stage a specific index, so when calling
586 * activateStage() or deactivateStage(), they can specify which stage
587 * is being activated/deactivated.
597 /** Typedefs from the Impl to get the structs that each of the
598 * time buffers should use.
600 typedef typename CPUPolicy::TimeStruct TimeStruct;
602 typedef typename CPUPolicy::FetchStruct FetchStruct;
604 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
606 typedef typename CPUPolicy::RenameStruct RenameStruct;
608 typedef typename CPUPolicy::IEWStruct IEWStruct;
610 /** The main time buffer to do backwards communication. */
611 TimeBuffer<TimeStruct> timeBuffer;
613 /** The fetch stage's instruction queue. */
614 TimeBuffer<FetchStruct> fetchQueue;
616 /** The decode stage's instruction queue. */
617 TimeBuffer<DecodeStruct> decodeQueue;
619 /** The rename stage's instruction queue. */
620 TimeBuffer<RenameStruct> renameQueue;
622 /** The IEW stage's instruction queue. */
623 TimeBuffer<IEWStruct> iewQueue;
626 /** The activity recorder; used to tell if the CPU has any
627 * activity remaining or if it can go to idle and deschedule
630 ActivityRecorder activityRec;
633 /** Records that there was time buffer activity this cycle. */
634 void activityThisCycle() { activityRec.activity(); }
636 /** Changes a stage's status to active within the activity recorder. */
637 void activateStage(const StageIdx idx)
638 { activityRec.activateStage(idx); }
640 /** Changes a stage's status to inactive within the activity recorder. */
641 void deactivateStage(const StageIdx idx)
642 { activityRec.deactivateStage(idx); }
644 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
647 virtual void wakeup();
649 /** Gets a free thread id. Use if thread ids change across system. */
650 ThreadID getFreeTid();
653 /** Returns a pointer to a thread context. */
657 return thread[tid]->getTC();
660 /** The global sequence number counter. */
661 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
663 /** Pointer to the checker, which can dynamically verify
664 * instruction results at run time. This can be set to NULL if it
667 Checker<Impl> *checker;
669 /** Pointer to the system. */
672 /** DrainManager to notify when draining has completed. */
673 DrainManager *drainManager;
675 /** Pointers to all of the threads in the CPU. */
676 std::vector<Thread *> thread;
678 /** Threads Scheduled to Enter CPU */
679 std::list<int> cpuWaitList;
681 /** The cycle that the CPU was last running, used for statistics. */
682 Cycles lastRunningCycle;
684 /** The cycle that the CPU was last activated by a new thread*/
685 Tick lastActivatedCycle;
687 /** Mapping for system thread id to cpu id */
688 std::map<ThreadID, unsigned> threadMap;
690 /** Available thread ids in the cpu*/
691 std::vector<ThreadID> tids;
693 /** CPU read function, forwards read to LSQ. */
694 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
695 uint8_t *data, int load_idx)
697 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
701 /** CPU write function, forwards write to LSQ. */
702 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
703 uint8_t *data, int store_idx)
705 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
709 /** Used by the fetch unit to get a hold of the instruction port. */
710 virtual MasterPort &getInstPort() { return icachePort; }
712 /** Get the dcache port (used to find block size for translations). */
713 virtual MasterPort &getDataPort() { return dcachePort; }
715 /** Stat for total number of times the CPU is descheduled. */
716 Stats::Scalar timesIdled;
717 /** Stat for total number of cycles the CPU spends descheduled. */
718 Stats::Scalar idleCycles;
719 /** Stat for total number of cycles the CPU spends descheduled due to a
720 * quiesce operation or waiting for an interrupt. */
721 Stats::Scalar quiesceCycles;
722 /** Stat for the number of committed instructions per thread. */
723 Stats::Vector committedInsts;
724 /** Stat for the number of committed ops (including micro ops) per thread. */
725 Stats::Vector committedOps;
726 /** Stat for the CPI per thread. */
728 /** Stat for the total CPI. */
729 Stats::Formula totalCpi;
730 /** Stat for the IPC per thread. */
732 /** Stat for the total IPC. */
733 Stats::Formula totalIpc;
735 //number of integer register file accesses
736 Stats::Scalar intRegfileReads;
737 Stats::Scalar intRegfileWrites;
738 //number of float register file accesses
739 Stats::Scalar fpRegfileReads;
740 Stats::Scalar fpRegfileWrites;
741 //number of CC register file accesses
742 Stats::Scalar ccRegfileReads;
743 Stats::Scalar ccRegfileWrites;
745 Stats::Scalar miscRegfileReads;
746 Stats::Scalar miscRegfileWrites;
749 #endif // __CPU_O3_CPU_HH__