src/cpu/o3/cpu_policy.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_O3_CPU_POLICY_HH__
  32 #define __CPU_O3_CPU_POLICY_HH__
  33
  34 #include "cpu/o3/bpred_unit.hh"
  35 #include "cpu/o3/free_list.hh"
  36 #include "cpu/o3/inst_queue.hh"
  37 #include "cpu/o3/lsq.hh"
  38 #include "cpu/o3/lsq_unit.hh"
  39 #include "cpu/o3/mem_dep_unit.hh"
  40 #include "cpu/o3/regfile.hh"
  41 #include "cpu/o3/rename_map.hh"
  42 #include "cpu/o3/rob.hh"
  43 #include "cpu/o3/store_set.hh"
  44
  45 #include "cpu/o3/commit.hh"
  46 #include "cpu/o3/decode.hh"
  47 #include "cpu/o3/fetch.hh"
  48 #include "cpu/o3/iew.hh"
  49 #include "cpu/o3/rename.hh"
  50
  51 #include "cpu/o3/comm.hh"
  52
  53 /**
  54  * Struct that defines the key classes to be used by the CPU.  All
  55  * classes use the typedefs defined here to determine what are the
  56  * classes of the other stages and communication buffers.  In order to
  57  * change a structure such as the IQ, simply change the typedef here
  58  * to use the desired class instead, and recompile.  In order to
  59  * create a different CPU to be used simultaneously with this one, see
  60  * the alpha_impl.hh file for instructions.
  61  */
  62 template<class Impl>
  63 struct SimpleCPUPolicy
  64 {
  65     /** Typedef for the branch prediction unit (which includes the BP,
  66      * RAS, and BTB).
  67      */
  68     typedef ::BPredUnit<Impl> BPredUnit;
  69     /** Typedef for the register file.  Most classes assume a unified
  70      * physical register file.
  71      */
  72     typedef PhysRegFile<Impl> RegFile;
  73     /** Typedef for the freelist of registers. */
  74     typedef SimpleFreeList FreeList;
  75     /** Typedef for the rename map. */
  76     typedef SimpleRenameMap RenameMap;
  77     /** Typedef for the ROB. */
  78     typedef ::ROB<Impl> ROB;
  79     /** Typedef for the instruction queue/scheduler. */
  80     typedef InstructionQueue<Impl> IQ;
  81     /** Typedef for the memory dependence unit. */
  82     typedef ::MemDepUnit<StoreSet, Impl> MemDepUnit;
  83     /** Typedef for the LSQ. */
  84     typedef ::LSQ<Impl> LSQ;
  85     /** Typedef for the thread-specific LSQ units. */
  86     typedef ::LSQUnit<Impl> LSQUnit;
  87
  88     /** Typedef for fetch. */
  89     typedef DefaultFetch<Impl> Fetch;
  90     /** Typedef for decode. */
  91     typedef DefaultDecode<Impl> Decode;
  92     /** Typedef for rename. */
  93     typedef DefaultRename<Impl> Rename;
  94     /** Typedef for Issue/Execute/Writeback. */
  95     typedef DefaultIEW<Impl> IEW;
  96     /** Typedef for commit. */
  97     typedef DefaultCommit<Impl> Commit;
  98
  99     /** The struct for communication between fetch and decode. */
 100     typedef DefaultFetchDefaultDecode<Impl> FetchStruct;
 101
 102     /** The struct for communication between decode and rename. */
 103     typedef DefaultDecodeDefaultRename<Impl> DecodeStruct;
 104
 105     /** The struct for communication between rename and IEW. */
 106     typedef DefaultRenameDefaultIEW<Impl> RenameStruct;
 107
 108     /** The struct for communication between IEW and commit. */
 109     typedef DefaultIEWDefaultCommit<Impl> IEWStruct;
 110
 111     /** The struct for communication within the IEW stage. */
 112     typedef ::IssueStruct<Impl> IssueStruct;
 113
 114     /** The struct for all backwards communication. */
 115     typedef TimeBufStruct<Impl> TimeStruct;
 116
 117 };
 118
 119 #endif //__CPU_O3_CPU_POLICY_HH__