src/cpu/o3/decode.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_O3_DECODE_HH__
  32 #define __CPU_O3_DECODE_HH__
  33
  34 #include <queue>
  35
  36 #include "base/statistics.hh"
  37 #include "base/timebuf.hh"
  38
  39 /**
  40  * DefaultDecode class handles both single threaded and SMT
  41  * decode. Its width is specified by the parameters; each cycles it
  42  * tries to decode that many instructions. Because instructions are
  43  * actually decoded when the StaticInst is created, this stage does
  44  * not do much other than check any PC-relative branches.
  45  */
  46 template<class Impl>
  47 class DefaultDecode
  48 {
  49   private:
  50     // Typedefs from the Impl.
  51     typedef typename Impl::O3CPU O3CPU;
  52     typedef typename Impl::DynInstPtr DynInstPtr;
  53     typedef typename Impl::Params Params;
  54     typedef typename Impl::CPUPol CPUPol;
  55
  56     // Typedefs from the CPU policy.
  57     typedef typename CPUPol::FetchStruct FetchStruct;
  58     typedef typename CPUPol::DecodeStruct DecodeStruct;
  59     typedef typename CPUPol::TimeStruct TimeStruct;
  60
  61   public:
  62     /** Overall decode stage status. Used to determine if the CPU can
  63      * deschedule itself due to a lack of activity.
  64      */
  65     enum DecodeStatus {
  66         Active,
  67         Inactive
  68     };
  69
  70     /** Individual thread status. */
  71     enum ThreadStatus {
  72         Running,
  73         Idle,
  74         StartSquash,
  75         Squashing,
  76         Blocked,
  77         Unblocking
  78     };
  79
  80   private:
  81     /** Decode status. */
  82     DecodeStatus _status;
  83
  84     /** Per-thread status. */
  85     ThreadStatus decodeStatus[Impl::MaxThreads];
  86
  87   public:
  88     /** DefaultDecode constructor. */
  89     DefaultDecode(O3CPU *_cpu, Params *params);
  90
  91     /** Returns the name of decode. */
  92     std::string name() const;
  93
  94     /** Registers statistics. */
  95     void regStats();
  96
  97     /** Sets the main backwards communication time buffer pointer. */
  98     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
  99
 100     /** Sets pointer to time buffer used to communicate to the next stage. */
 101     void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
 102
 103     /** Sets pointer to time buffer coming from fetch. */
 104     void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
 105
 106     /** Sets pointer to list of active threads. */
 107     void setActiveThreads(std::list<unsigned> *at_ptr);
 108
 109     /** Drains the decode stage. */
 110     bool drain();
 111
 112     /** Resumes execution after a drain. */
 113     void resume() { }
 114
 115     /** Switches out the decode stage. */
 116     void switchOut() { }
 117
 118     /** Takes over from another CPU's thread. */
 119     void takeOverFrom();
 120
 121     /** Ticks decode, processing all input signals and decoding as many
 122      * instructions as possible.
 123      */
 124     void tick();
 125
 126     /** Determines what to do based on decode's current status.
 127      * @param status_change decode() sets this variable if there was a status
 128      * change (ie switching from from blocking to unblocking).
 129      * @param tid Thread id to decode instructions from.
 130      */
 131     void decode(bool &status_change, unsigned tid);
 132
 133     /** Processes instructions from fetch and passes them on to rename.
 134      * Decoding of instructions actually happens when they are created in
 135      * fetch, so this function mostly checks if PC-relative branches are
 136      * correct.
 137      */
 138     void decodeInsts(unsigned tid);
 139
 140   private:
 141     /** Inserts a thread's instructions into the skid buffer, to be decoded
 142      * once decode unblocks.
 143      */
 144     void skidInsert(unsigned tid);
 145
 146     /** Returns if all of the skid buffers are empty. */
 147     bool skidsEmpty();
 148
 149     /** Updates overall decode status based on all of the threads' statuses. */
 150     void updateStatus();
 151
 152     /** Separates instructions from fetch into individual lists of instructions
 153      * sorted by thread.
 154      */
 155     void sortInsts();
 156
 157     /** Reads all stall signals from the backwards communication timebuffer. */
 158     void readStallSignals(unsigned tid);
 159
 160     /** Checks all input signals and updates decode's status appropriately. */
 161     bool checkSignalsAndUpdate(unsigned tid);
 162
 163     /** Checks all stall signals, and returns if any are true. */
 164     bool checkStall(unsigned tid) const;
 165
 166     /** Returns if there any instructions from fetch on this cycle. */
 167     inline bool fetchInstsValid();
 168
 169     /** Switches decode to blocking, and signals back that decode has
 170      * become blocked.
 171      * @return Returns true if there is a status change.
 172      */
 173     bool block(unsigned tid);
 174
 175     /** Switches decode to unblocking if the skid buffer is empty, and
 176      * signals back that decode has unblocked.
 177      * @return Returns true if there is a status change.
 178      */
 179     bool unblock(unsigned tid);
 180
 181     /** Squashes if there is a PC-relative branch that was predicted
 182      * incorrectly. Sends squash information back to fetch.
 183      */
 184     void squash(DynInstPtr &inst, unsigned tid);
 185
 186   public:
 187     /** Squashes due to commit signalling a squash. Changes status to
 188      * squashing and clears block/unblock signals as needed.
 189      */
 190     unsigned squash(unsigned tid);
 191
 192   private:
 193     // Interfaces to objects outside of decode.
 194     /** CPU interface. */
 195     O3CPU *cpu;
 196
 197     /** Time buffer interface. */
 198     TimeBuffer<TimeStruct> *timeBuffer;
 199
 200     /** Wire to get rename's output from backwards time buffer. */
 201     typename TimeBuffer<TimeStruct>::wire fromRename;
 202
 203     /** Wire to get iew's information from backwards time buffer. */
 204     typename TimeBuffer<TimeStruct>::wire fromIEW;
 205
 206     /** Wire to get commit's information from backwards time buffer. */
 207     typename TimeBuffer<TimeStruct>::wire fromCommit;
 208
 209     /** Wire to write information heading to previous stages. */
 210     // Might not be the best name as not only fetch will read it.
 211     typename TimeBuffer<TimeStruct>::wire toFetch;
 212
 213     /** Decode instruction queue. */
 214     TimeBuffer<DecodeStruct> *decodeQueue;
 215
 216     /** Wire used to write any information heading to rename. */
 217     typename TimeBuffer<DecodeStruct>::wire toRename;
 218
 219     /** Fetch instruction queue interface. */
 220     TimeBuffer<FetchStruct> *fetchQueue;
 221
 222     /** Wire to get fetch's output from fetch queue. */
 223     typename TimeBuffer<FetchStruct>::wire fromFetch;
 224
 225     /** Queue of all instructions coming from fetch this cycle. */
 226     std::queue<DynInstPtr> insts[Impl::MaxThreads];
 227
 228     /** Skid buffer between fetch and decode. */
 229     std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
 230
 231     /** Variable that tracks if decode has written to the time buffer this
 232      * cycle. Used to tell CPU if there is activity this cycle.
 233      */
 234     bool wroteToTimeBuffer;
 235
 236     /** Source of possible stalls. */
 237     struct Stalls {
 238         bool rename;
 239         bool iew;
 240         bool commit;
 241     };
 242
 243     /** Tracks which stages are telling decode to stall. */
 244     Stalls stalls[Impl::MaxThreads];
 245
 246     /** Rename to decode delay, in ticks. */
 247     unsigned renameToDecodeDelay;
 248
 249     /** IEW to decode delay, in ticks. */
 250     unsigned iewToDecodeDelay;
 251
 252     /** Commit to decode delay, in ticks. */
 253     unsigned commitToDecodeDelay;
 254
 255     /** Fetch to decode delay, in ticks. */
 256     unsigned fetchToDecodeDelay;
 257
 258     /** The width of decode, in instructions. */
 259     unsigned decodeWidth;
 260
 261     /** Index of instructions being sent to rename. */
 262     unsigned toRenameIndex;
 263
 264     /** number of Active Threads*/
 265     unsigned numThreads;
 266
 267     /** List of active thread ids */
 268     std::list<unsigned> *activeThreads;
 269
 270     /** Number of branches in flight. */
 271     unsigned branchCount[Impl::MaxThreads];
 272
 273     /** Maximum size of the skid buffer. */
 274     unsigned skidBufferMax;
 275
 276     /** SeqNum of Squashing Branch Delay Instruction (used for MIPS)*/
 277     Addr bdelayDoneSeqNum[Impl::MaxThreads];
 278
 279     /** Instruction used for squashing branch (used for MIPS)*/
 280     DynInstPtr squashInst[Impl::MaxThreads];
 281
 282     /** Tells when their is a pending delay slot inst. to send
 283      *  to rename. If there is, then wait squash after the next
 284      *  instruction (used for MIPS).
 285      */
 286     bool squashAfterDelaySlot[Impl::MaxThreads];
 287
 288
 289     /** Stat for total number of idle cycles. */
 290     Stats::Scalar<> decodeIdleCycles;
 291     /** Stat for total number of blocked cycles. */
 292     Stats::Scalar<> decodeBlockedCycles;
 293     /** Stat for total number of normal running cycles. */
 294     Stats::Scalar<> decodeRunCycles;
 295     /** Stat for total number of unblocking cycles. */
 296     Stats::Scalar<> decodeUnblockCycles;
 297     /** Stat for total number of squashing cycles. */
 298     Stats::Scalar<> decodeSquashCycles;
 299     /** Stat for number of times a branch is resolved at decode. */
 300     Stats::Scalar<> decodeBranchResolved;
 301     /** Stat for number of times a branch mispredict is detected. */
 302     Stats::Scalar<> decodeBranchMispred;
 303     /** Stat for number of times decode detected a non-control instruction
 304      * incorrectly predicted as a branch.
 305      */
 306     Stats::Scalar<> decodeControlMispred;
 307     /** Stat for total number of decoded instructions. */
 308     Stats::Scalar<> decodeDecodedInsts;
 309     /** Stat for total number of squashed instructions. */
 310     Stats::Scalar<> decodeSquashedInsts;
 311 };
 312
 313 #endif // __CPU_O3_DECODE_HH__