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43 #ifndef __CPU_O3_DECODE_HH__
44 #define __CPU_O3_DECODE_HH__
48 #include "base/statistics.hh"
49 #include "cpu/timebuf.hh"
51 struct DerivO3CPUParams;
54 * DefaultDecode class handles both single threaded and SMT
55 * decode. Its width is specified by the parameters; each cycles it
56 * tries to decode that many instructions. Because instructions are
57 * actually decoded when the StaticInst is created, this stage does
58 * not do much other than check any PC-relative branches.
64 // Typedefs from the Impl.
65 typedef typename Impl::O3CPU O3CPU;
66 typedef typename Impl::DynInstPtr DynInstPtr;
67 typedef typename Impl::CPUPol CPUPol;
69 // Typedefs from the CPU policy.
70 typedef typename CPUPol::FetchStruct FetchStruct;
71 typedef typename CPUPol::DecodeStruct DecodeStruct;
72 typedef typename CPUPol::TimeStruct TimeStruct;
75 /** Overall decode stage status. Used to determine if the CPU can
76 * deschedule itself due to a lack of activity.
83 /** Individual thread status. */
97 /** Per-thread status. */
98 ThreadStatus decodeStatus[Impl::MaxThreads];
101 /** DefaultDecode constructor. */
102 DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params);
106 /** Clear all thread-specific states */
107 void clearStates(ThreadID tid);
111 /** Returns the name of decode. */
112 std::string name() const;
114 /** Registers statistics. */
117 /** Sets the main backwards communication time buffer pointer. */
118 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
120 /** Sets pointer to time buffer used to communicate to the next stage. */
121 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
123 /** Sets pointer to time buffer coming from fetch. */
124 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
126 /** Sets pointer to list of active threads. */
127 void setActiveThreads(std::list<ThreadID> *at_ptr);
129 /** Perform sanity checks after a drain. */
130 void drainSanityCheck() const;
132 /** Has the stage drained? */
133 bool isDrained() const;
135 /** Takes over from another CPU's thread. */
136 void takeOverFrom() { resetStage(); }
138 /** Ticks decode, processing all input signals and decoding as many
139 * instructions as possible.
143 /** Determines what to do based on decode's current status.
144 * @param status_change decode() sets this variable if there was a status
145 * change (ie switching from from blocking to unblocking).
146 * @param tid Thread id to decode instructions from.
148 void decode(bool &status_change, ThreadID tid);
150 /** Processes instructions from fetch and passes them on to rename.
151 * Decoding of instructions actually happens when they are created in
152 * fetch, so this function mostly checks if PC-relative branches are
155 void decodeInsts(ThreadID tid);
158 /** Inserts a thread's instructions into the skid buffer, to be decoded
159 * once decode unblocks.
161 void skidInsert(ThreadID tid);
163 /** Returns if all of the skid buffers are empty. */
166 /** Updates overall decode status based on all of the threads' statuses. */
169 /** Separates instructions from fetch into individual lists of instructions
174 /** Reads all stall signals from the backwards communication timebuffer. */
175 void readStallSignals(ThreadID tid);
177 /** Checks all input signals and updates decode's status appropriately. */
178 bool checkSignalsAndUpdate(ThreadID tid);
180 /** Checks all stall signals, and returns if any are true. */
181 bool checkStall(ThreadID tid) const;
183 /** Returns if there any instructions from fetch on this cycle. */
184 inline bool fetchInstsValid();
186 /** Switches decode to blocking, and signals back that decode has
188 * @return Returns true if there is a status change.
190 bool block(ThreadID tid);
192 /** Switches decode to unblocking if the skid buffer is empty, and
193 * signals back that decode has unblocked.
194 * @return Returns true if there is a status change.
196 bool unblock(ThreadID tid);
198 /** Squashes if there is a PC-relative branch that was predicted
199 * incorrectly. Sends squash information back to fetch.
201 void squash(const DynInstPtr &inst, ThreadID tid);
204 /** Squashes due to commit signalling a squash. Changes status to
205 * squashing and clears block/unblock signals as needed.
207 unsigned squash(ThreadID tid);
210 // Interfaces to objects outside of decode.
211 /** CPU interface. */
214 /** Time buffer interface. */
215 TimeBuffer<TimeStruct> *timeBuffer;
217 /** Wire to get rename's output from backwards time buffer. */
218 typename TimeBuffer<TimeStruct>::wire fromRename;
220 /** Wire to get iew's information from backwards time buffer. */
221 typename TimeBuffer<TimeStruct>::wire fromIEW;
223 /** Wire to get commit's information from backwards time buffer. */
224 typename TimeBuffer<TimeStruct>::wire fromCommit;
226 /** Wire to write information heading to previous stages. */
227 // Might not be the best name as not only fetch will read it.
228 typename TimeBuffer<TimeStruct>::wire toFetch;
230 /** Decode instruction queue. */
231 TimeBuffer<DecodeStruct> *decodeQueue;
233 /** Wire used to write any information heading to rename. */
234 typename TimeBuffer<DecodeStruct>::wire toRename;
236 /** Fetch instruction queue interface. */
237 TimeBuffer<FetchStruct> *fetchQueue;
239 /** Wire to get fetch's output from fetch queue. */
240 typename TimeBuffer<FetchStruct>::wire fromFetch;
242 /** Queue of all instructions coming from fetch this cycle. */
243 std::queue<DynInstPtr> insts[Impl::MaxThreads];
245 /** Skid buffer between fetch and decode. */
246 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
248 /** Variable that tracks if decode has written to the time buffer this
249 * cycle. Used to tell CPU if there is activity this cycle.
251 bool wroteToTimeBuffer;
253 /** Source of possible stalls. */
258 /** Tracks which stages are telling decode to stall. */
259 Stalls stalls[Impl::MaxThreads];
261 /** Rename to decode delay. */
262 Cycles renameToDecodeDelay;
264 /** IEW to decode delay. */
265 Cycles iewToDecodeDelay;
267 /** Commit to decode delay. */
268 Cycles commitToDecodeDelay;
270 /** Fetch to decode delay. */
271 Cycles fetchToDecodeDelay;
273 /** The width of decode, in instructions. */
274 unsigned decodeWidth;
276 /** Index of instructions being sent to rename. */
277 unsigned toRenameIndex;
279 /** number of Active Threads*/
282 /** List of active thread ids */
283 std::list<ThreadID> *activeThreads;
285 /** Maximum size of the skid buffer. */
286 unsigned skidBufferMax;
288 /** SeqNum of Squashing Branch Delay Instruction (used for MIPS)*/
289 Addr bdelayDoneSeqNum[Impl::MaxThreads];
291 /** Instruction used for squashing branch (used for MIPS)*/
292 DynInstPtr squashInst[Impl::MaxThreads];
294 /** Tells when their is a pending delay slot inst. to send
295 * to rename. If there is, then wait squash after the next
296 * instruction (used for MIPS).
298 bool squashAfterDelaySlot[Impl::MaxThreads];
301 /** Stat for total number of idle cycles. */
302 Stats::Scalar decodeIdleCycles;
303 /** Stat for total number of blocked cycles. */
304 Stats::Scalar decodeBlockedCycles;
305 /** Stat for total number of normal running cycles. */
306 Stats::Scalar decodeRunCycles;
307 /** Stat for total number of unblocking cycles. */
308 Stats::Scalar decodeUnblockCycles;
309 /** Stat for total number of squashing cycles. */
310 Stats::Scalar decodeSquashCycles;
311 /** Stat for number of times a branch is resolved at decode. */
312 Stats::Scalar decodeBranchResolved;
313 /** Stat for number of times a branch mispredict is detected. */
314 Stats::Scalar decodeBranchMispred;
315 /** Stat for number of times decode detected a non-control instruction
316 * incorrectly predicted as a branch.
318 Stats::Scalar decodeControlMispred;
319 /** Stat for total number of decoded instructions. */
320 Stats::Scalar decodeDecodedInsts;
321 /** Stat for total number of squashed instructions. */
322 Stats::Scalar decodeSquashedInsts;
325 #endif // __CPU_O3_DECODE_HH__