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31 #ifndef __CPU_O3_DECODE_HH__
32 #define __CPU_O3_DECODE_HH__
36 #include "base/statistics.hh"
37 #include "cpu/timebuf.hh"
39 struct DerivO3CPUParams;
42 * DefaultDecode class handles both single threaded and SMT
43 * decode. Its width is specified by the parameters; each cycles it
44 * tries to decode that many instructions. Because instructions are
45 * actually decoded when the StaticInst is created, this stage does
46 * not do much other than check any PC-relative branches.
52 // Typedefs from the Impl.
53 typedef typename Impl::O3CPU O3CPU;
54 typedef typename Impl::DynInstPtr DynInstPtr;
55 typedef typename Impl::CPUPol CPUPol;
57 // Typedefs from the CPU policy.
58 typedef typename CPUPol::FetchStruct FetchStruct;
59 typedef typename CPUPol::DecodeStruct DecodeStruct;
60 typedef typename CPUPol::TimeStruct TimeStruct;
63 /** Overall decode stage status. Used to determine if the CPU can
64 * deschedule itself due to a lack of activity.
71 /** Individual thread status. */
85 /** Per-thread status. */
86 ThreadStatus decodeStatus[Impl::MaxThreads];
89 /** DefaultDecode constructor. */
90 DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params);
92 /** Returns the name of decode. */
93 std::string name() const;
95 /** Registers statistics. */
98 /** Sets the main backwards communication time buffer pointer. */
99 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
101 /** Sets pointer to time buffer used to communicate to the next stage. */
102 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
104 /** Sets pointer to time buffer coming from fetch. */
105 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
107 /** Sets pointer to list of active threads. */
108 void setActiveThreads(std::list<ThreadID> *at_ptr);
110 /** Drains the decode stage. */
113 /** Resumes execution after a drain. */
116 /** Switches out the decode stage. */
119 /** Takes over from another CPU's thread. */
122 /** Ticks decode, processing all input signals and decoding as many
123 * instructions as possible.
127 /** Determines what to do based on decode's current status.
128 * @param status_change decode() sets this variable if there was a status
129 * change (ie switching from from blocking to unblocking).
130 * @param tid Thread id to decode instructions from.
132 void decode(bool &status_change, ThreadID tid);
134 /** Processes instructions from fetch and passes them on to rename.
135 * Decoding of instructions actually happens when they are created in
136 * fetch, so this function mostly checks if PC-relative branches are
139 void decodeInsts(ThreadID tid);
142 /** Inserts a thread's instructions into the skid buffer, to be decoded
143 * once decode unblocks.
145 void skidInsert(ThreadID tid);
147 /** Returns if all of the skid buffers are empty. */
150 /** Updates overall decode status based on all of the threads' statuses. */
153 /** Separates instructions from fetch into individual lists of instructions
158 /** Reads all stall signals from the backwards communication timebuffer. */
159 void readStallSignals(ThreadID tid);
161 /** Checks all input signals and updates decode's status appropriately. */
162 bool checkSignalsAndUpdate(ThreadID tid);
164 /** Checks all stall signals, and returns if any are true. */
165 bool checkStall(ThreadID tid) const;
167 /** Returns if there any instructions from fetch on this cycle. */
168 inline bool fetchInstsValid();
170 /** Switches decode to blocking, and signals back that decode has
172 * @return Returns true if there is a status change.
174 bool block(ThreadID tid);
176 /** Switches decode to unblocking if the skid buffer is empty, and
177 * signals back that decode has unblocked.
178 * @return Returns true if there is a status change.
180 bool unblock(ThreadID tid);
182 /** Squashes if there is a PC-relative branch that was predicted
183 * incorrectly. Sends squash information back to fetch.
185 void squash(DynInstPtr &inst, ThreadID tid);
188 /** Squashes due to commit signalling a squash. Changes status to
189 * squashing and clears block/unblock signals as needed.
191 unsigned squash(ThreadID tid);
194 // Interfaces to objects outside of decode.
195 /** CPU interface. */
198 /** Time buffer interface. */
199 TimeBuffer<TimeStruct> *timeBuffer;
201 /** Wire to get rename's output from backwards time buffer. */
202 typename TimeBuffer<TimeStruct>::wire fromRename;
204 /** Wire to get iew's information from backwards time buffer. */
205 typename TimeBuffer<TimeStruct>::wire fromIEW;
207 /** Wire to get commit's information from backwards time buffer. */
208 typename TimeBuffer<TimeStruct>::wire fromCommit;
210 /** Wire to write information heading to previous stages. */
211 // Might not be the best name as not only fetch will read it.
212 typename TimeBuffer<TimeStruct>::wire toFetch;
214 /** Decode instruction queue. */
215 TimeBuffer<DecodeStruct> *decodeQueue;
217 /** Wire used to write any information heading to rename. */
218 typename TimeBuffer<DecodeStruct>::wire toRename;
220 /** Fetch instruction queue interface. */
221 TimeBuffer<FetchStruct> *fetchQueue;
223 /** Wire to get fetch's output from fetch queue. */
224 typename TimeBuffer<FetchStruct>::wire fromFetch;
226 /** Queue of all instructions coming from fetch this cycle. */
227 std::queue<DynInstPtr> insts[Impl::MaxThreads];
229 /** Skid buffer between fetch and decode. */
230 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
232 /** Variable that tracks if decode has written to the time buffer this
233 * cycle. Used to tell CPU if there is activity this cycle.
235 bool wroteToTimeBuffer;
237 /** Source of possible stalls. */
244 /** Tracks which stages are telling decode to stall. */
245 Stalls stalls[Impl::MaxThreads];
247 /** Rename to decode delay. */
248 Cycles renameToDecodeDelay;
250 /** IEW to decode delay. */
251 Cycles iewToDecodeDelay;
253 /** Commit to decode delay. */
254 Cycles commitToDecodeDelay;
256 /** Fetch to decode delay. */
257 Cycles fetchToDecodeDelay;
259 /** The width of decode, in instructions. */
260 unsigned decodeWidth;
262 /** Index of instructions being sent to rename. */
263 unsigned toRenameIndex;
265 /** number of Active Threads*/
268 /** List of active thread ids */
269 std::list<ThreadID> *activeThreads;
271 /** Number of branches in flight. */
272 unsigned branchCount[Impl::MaxThreads];
274 /** Maximum size of the skid buffer. */
275 unsigned skidBufferMax;
277 /** SeqNum of Squashing Branch Delay Instruction (used for MIPS)*/
278 Addr bdelayDoneSeqNum[Impl::MaxThreads];
280 /** Instruction used for squashing branch (used for MIPS)*/
281 DynInstPtr squashInst[Impl::MaxThreads];
283 /** Tells when their is a pending delay slot inst. to send
284 * to rename. If there is, then wait squash after the next
285 * instruction (used for MIPS).
287 bool squashAfterDelaySlot[Impl::MaxThreads];
290 /** Stat for total number of idle cycles. */
291 Stats::Scalar decodeIdleCycles;
292 /** Stat for total number of blocked cycles. */
293 Stats::Scalar decodeBlockedCycles;
294 /** Stat for total number of normal running cycles. */
295 Stats::Scalar decodeRunCycles;
296 /** Stat for total number of unblocking cycles. */
297 Stats::Scalar decodeUnblockCycles;
298 /** Stat for total number of squashing cycles. */
299 Stats::Scalar decodeSquashCycles;
300 /** Stat for number of times a branch is resolved at decode. */
301 Stats::Scalar decodeBranchResolved;
302 /** Stat for number of times a branch mispredict is detected. */
303 Stats::Scalar decodeBranchMispred;
304 /** Stat for number of times decode detected a non-control instruction
305 * incorrectly predicted as a branch.
307 Stats::Scalar decodeControlMispred;
308 /** Stat for total number of decoded instructions. */
309 Stats::Scalar decodeDecodedInsts;
310 /** Stat for total number of squashed instructions. */
311 Stats::Scalar decodeSquashedInsts;
314 #endif // __CPU_O3_DECODE_HH__