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31 #ifndef __CPU_O3_DECODE_HH__
32 #define __CPU_O3_DECODE_HH__
36 #include "base/statistics.hh"
37 #include "base/timebuf.hh"
40 * DefaultDecode class handles both single threaded and SMT
41 * decode. Its width is specified by the parameters; each cycles it
42 * tries to decode that many instructions. Because instructions are
43 * actually decoded when the StaticInst is created, this stage does
44 * not do much other than check any PC-relative branches.
50 // Typedefs from the Impl.
51 typedef typename Impl::O3CPU O3CPU;
52 typedef typename Impl::DynInstPtr DynInstPtr;
53 typedef typename Impl::Params Params;
54 typedef typename Impl::CPUPol CPUPol;
56 // Typedefs from the CPU policy.
57 typedef typename CPUPol::FetchStruct FetchStruct;
58 typedef typename CPUPol::DecodeStruct DecodeStruct;
59 typedef typename CPUPol::TimeStruct TimeStruct;
62 /** Overall decode stage status. Used to determine if the CPU can
63 * deschedule itself due to a lack of activity.
70 /** Individual thread status. */
84 /** Per-thread status. */
85 ThreadStatus decodeStatus[Impl::MaxThreads];
88 /** DefaultDecode constructor. */
89 DefaultDecode(Params *params);
91 /** Returns the name of decode. */
92 std::string name() const;
94 /** Registers statistics. */
97 /** Sets CPU pointer. */
98 void setCPU(O3CPU *cpu_ptr);
100 /** Sets the main backwards communication time buffer pointer. */
101 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
103 /** Sets pointer to time buffer used to communicate to the next stage. */
104 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
106 /** Sets pointer to time buffer coming from fetch. */
107 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
109 /** Sets pointer to list of active threads. */
110 void setActiveThreads(std::list<unsigned> *at_ptr);
112 /** Drains the decode stage. */
115 /** Resumes execution after a drain. */
118 /** Switches out the decode stage. */
121 /** Takes over from another CPU's thread. */
124 /** Ticks decode, processing all input signals and decoding as many
125 * instructions as possible.
129 /** Determines what to do based on decode's current status.
130 * @param status_change decode() sets this variable if there was a status
131 * change (ie switching from from blocking to unblocking).
132 * @param tid Thread id to decode instructions from.
134 void decode(bool &status_change, unsigned tid);
136 /** Processes instructions from fetch and passes them on to rename.
137 * Decoding of instructions actually happens when they are created in
138 * fetch, so this function mostly checks if PC-relative branches are
141 void decodeInsts(unsigned tid);
144 /** Inserts a thread's instructions into the skid buffer, to be decoded
145 * once decode unblocks.
147 void skidInsert(unsigned tid);
149 /** Returns if all of the skid buffers are empty. */
152 /** Updates overall decode status based on all of the threads' statuses. */
155 /** Separates instructions from fetch into individual lists of instructions
160 /** Reads all stall signals from the backwards communication timebuffer. */
161 void readStallSignals(unsigned tid);
163 /** Checks all input signals and updates decode's status appropriately. */
164 bool checkSignalsAndUpdate(unsigned tid);
166 /** Checks all stall signals, and returns if any are true. */
167 bool checkStall(unsigned tid) const;
169 /** Returns if there any instructions from fetch on this cycle. */
170 inline bool fetchInstsValid();
172 /** Switches decode to blocking, and signals back that decode has
174 * @return Returns true if there is a status change.
176 bool block(unsigned tid);
178 /** Switches decode to unblocking if the skid buffer is empty, and
179 * signals back that decode has unblocked.
180 * @return Returns true if there is a status change.
182 bool unblock(unsigned tid);
184 /** Squashes if there is a PC-relative branch that was predicted
185 * incorrectly. Sends squash information back to fetch.
187 void squash(DynInstPtr &inst, unsigned tid);
190 /** Squashes due to commit signalling a squash. Changes status to
191 * squashing and clears block/unblock signals as needed.
193 unsigned squash(unsigned tid);
196 // Interfaces to objects outside of decode.
197 /** CPU interface. */
200 /** Time buffer interface. */
201 TimeBuffer<TimeStruct> *timeBuffer;
203 /** Wire to get rename's output from backwards time buffer. */
204 typename TimeBuffer<TimeStruct>::wire fromRename;
206 /** Wire to get iew's information from backwards time buffer. */
207 typename TimeBuffer<TimeStruct>::wire fromIEW;
209 /** Wire to get commit's information from backwards time buffer. */
210 typename TimeBuffer<TimeStruct>::wire fromCommit;
212 /** Wire to write information heading to previous stages. */
213 // Might not be the best name as not only fetch will read it.
214 typename TimeBuffer<TimeStruct>::wire toFetch;
216 /** Decode instruction queue. */
217 TimeBuffer<DecodeStruct> *decodeQueue;
219 /** Wire used to write any information heading to rename. */
220 typename TimeBuffer<DecodeStruct>::wire toRename;
222 /** Fetch instruction queue interface. */
223 TimeBuffer<FetchStruct> *fetchQueue;
225 /** Wire to get fetch's output from fetch queue. */
226 typename TimeBuffer<FetchStruct>::wire fromFetch;
228 /** Queue of all instructions coming from fetch this cycle. */
229 std::queue<DynInstPtr> insts[Impl::MaxThreads];
231 /** Skid buffer between fetch and decode. */
232 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
234 /** Variable that tracks if decode has written to the time buffer this
235 * cycle. Used to tell CPU if there is activity this cycle.
237 bool wroteToTimeBuffer;
239 /** Source of possible stalls. */
246 /** Tracks which stages are telling decode to stall. */
247 Stalls stalls[Impl::MaxThreads];
249 /** Rename to decode delay, in ticks. */
250 unsigned renameToDecodeDelay;
252 /** IEW to decode delay, in ticks. */
253 unsigned iewToDecodeDelay;
255 /** Commit to decode delay, in ticks. */
256 unsigned commitToDecodeDelay;
258 /** Fetch to decode delay, in ticks. */
259 unsigned fetchToDecodeDelay;
261 /** The width of decode, in instructions. */
262 unsigned decodeWidth;
264 /** Index of instructions being sent to rename. */
265 unsigned toRenameIndex;
267 /** number of Active Threads*/
270 /** List of active thread ids */
271 std::list<unsigned> *activeThreads;
273 /** Number of branches in flight. */
274 unsigned branchCount[Impl::MaxThreads];
276 /** Maximum size of the skid buffer. */
277 unsigned skidBufferMax;
279 /** Stat for total number of idle cycles. */
280 Stats::Scalar<> decodeIdleCycles;
281 /** Stat for total number of blocked cycles. */
282 Stats::Scalar<> decodeBlockedCycles;
283 /** Stat for total number of normal running cycles. */
284 Stats::Scalar<> decodeRunCycles;
285 /** Stat for total number of unblocking cycles. */
286 Stats::Scalar<> decodeUnblockCycles;
287 /** Stat for total number of squashing cycles. */
288 Stats::Scalar<> decodeSquashCycles;
289 /** Stat for number of times a branch is resolved at decode. */
290 Stats::Scalar<> decodeBranchResolved;
291 /** Stat for number of times a branch mispredict is detected. */
292 Stats::Scalar<> decodeBranchMispred;
293 /** Stat for number of times decode detected a non-control instruction
294 * incorrectly predicted as a branch.
296 Stats::Scalar<> decodeControlMispred;
297 /** Stat for total number of decoded instructions. */
298 Stats::Scalar<> decodeDecodedInsts;
299 /** Stat for total number of squashed instructions. */
300 Stats::Scalar<> decodeSquashedInsts;
303 #endif // __CPU_O3_DECODE_HH__