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31 #include "arch/types.hh"
32 #include "base/trace.hh"
33 #include "config/the_isa.hh"
34 #include "cpu/o3/decode.hh"
35 #include "cpu/inst_seq.hh"
36 #include "debug/Activity.hh"
37 #include "debug/Decode.hh"
38 #include "params/DerivO3CPU.hh"
39 #include "sim/full_system.hh"
41 // clang complains about std::set being overloaded with Packet::set if
42 // we open up the entire namespace std
46 DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
48 renameToDecodeDelay(params->renameToDecodeDelay),
49 iewToDecodeDelay(params->iewToDecodeDelay),
50 commitToDecodeDelay(params->commitToDecodeDelay),
51 fetchToDecodeDelay(params->fetchToDecodeDelay),
52 decodeWidth(params->decodeWidth),
53 numThreads(params->numThreads)
57 // Setup status, make sure stall signals are clear.
58 for (ThreadID tid = 0; tid < numThreads; ++tid) {
59 decodeStatus[tid] = Idle;
61 stalls[tid].rename = false;
62 stalls[tid].iew = false;
63 stalls[tid].commit = false;
66 // @todo: Make into a parameter
67 skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth;
72 DefaultDecode<Impl>::name() const
74 return cpu->name() + ".decode";
79 DefaultDecode<Impl>::regStats()
82 .name(name() + ".IdleCycles")
83 .desc("Number of cycles decode is idle")
84 .prereq(decodeIdleCycles);
86 .name(name() + ".BlockedCycles")
87 .desc("Number of cycles decode is blocked")
88 .prereq(decodeBlockedCycles);
90 .name(name() + ".RunCycles")
91 .desc("Number of cycles decode is running")
92 .prereq(decodeRunCycles);
94 .name(name() + ".UnblockCycles")
95 .desc("Number of cycles decode is unblocking")
96 .prereq(decodeUnblockCycles);
98 .name(name() + ".SquashCycles")
99 .desc("Number of cycles decode is squashing")
100 .prereq(decodeSquashCycles);
102 .name(name() + ".BranchResolved")
103 .desc("Number of times decode resolved a branch")
104 .prereq(decodeBranchResolved);
106 .name(name() + ".BranchMispred")
107 .desc("Number of times decode detected a branch misprediction")
108 .prereq(decodeBranchMispred);
110 .name(name() + ".ControlMispred")
111 .desc("Number of times decode detected an instruction incorrectly"
112 " predicted as a control")
113 .prereq(decodeControlMispred);
115 .name(name() + ".DecodedInsts")
116 .desc("Number of instructions handled by decode")
117 .prereq(decodeDecodedInsts);
119 .name(name() + ".SquashedInsts")
120 .desc("Number of squashed instructions handled by decode")
121 .prereq(decodeSquashedInsts);
126 DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
130 // Setup wire to write information back to fetch.
131 toFetch = timeBuffer->getWire(0);
133 // Create wires to get information from proper places in time buffer.
134 fromRename = timeBuffer->getWire(-renameToDecodeDelay);
135 fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
136 fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
141 DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
143 decodeQueue = dq_ptr;
145 // Setup wire to write information to proper place in decode queue.
146 toRename = decodeQueue->getWire(0);
151 DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
155 // Setup wire to read information from fetch queue.
156 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
161 DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
163 activeThreads = at_ptr;
166 template <class Impl>
168 DefaultDecode<Impl>::drain()
170 // Decode is done draining at any time.
171 cpu->signalDrained();
175 template <class Impl>
177 DefaultDecode<Impl>::takeOverFrom()
181 // Be sure to reset state and clear out any old instructions.
182 for (ThreadID tid = 0; tid < numThreads; ++tid) {
183 decodeStatus[tid] = Idle;
185 stalls[tid].rename = false;
186 stalls[tid].iew = false;
187 stalls[tid].commit = false;
188 while (!insts[tid].empty())
190 while (!skidBuffer[tid].empty())
191 skidBuffer[tid].pop();
192 branchCount[tid] = 0;
194 wroteToTimeBuffer = false;
199 DefaultDecode<Impl>::checkStall(ThreadID tid) const
201 bool ret_val = false;
203 if (stalls[tid].rename) {
204 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
206 } else if (stalls[tid].iew) {
207 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
209 } else if (stalls[tid].commit) {
210 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
219 DefaultDecode<Impl>::fetchInstsValid()
221 return fromFetch->size > 0;
226 DefaultDecode<Impl>::block(ThreadID tid)
228 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
230 // Add the current inputs to the skid buffer so they can be
231 // reprocessed when this stage unblocks.
234 // If the decode status is blocked or unblocking then decode has not yet
235 // signalled fetch to unblock. In that case, there is no need to tell
237 if (decodeStatus[tid] != Blocked) {
238 // Set the status to Blocked.
239 decodeStatus[tid] = Blocked;
241 if (decodeStatus[tid] != Unblocking) {
242 toFetch->decodeBlock[tid] = true;
243 wroteToTimeBuffer = true;
254 DefaultDecode<Impl>::unblock(ThreadID tid)
256 // Decode is done unblocking only if the skid buffer is empty.
257 if (skidBuffer[tid].empty()) {
258 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
259 toFetch->decodeUnblock[tid] = true;
260 wroteToTimeBuffer = true;
262 decodeStatus[tid] = Running;
266 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
273 DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
275 DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch "
276 "prediction detected at decode.\n", tid, inst->seqNum);
278 // Send back mispredict information.
279 toFetch->decodeInfo[tid].branchMispredict = true;
280 toFetch->decodeInfo[tid].predIncorrect = true;
281 toFetch->decodeInfo[tid].mispredictInst = inst;
282 toFetch->decodeInfo[tid].squash = true;
283 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
284 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
285 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
286 toFetch->decodeInfo[tid].squashInst = inst;
287 if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) {
288 toFetch->decodeInfo[tid].branchTaken = true;
291 InstSeqNum squash_seq_num = inst->seqNum;
293 // Might have to tell fetch to unblock.
294 if (decodeStatus[tid] == Blocked ||
295 decodeStatus[tid] == Unblocking) {
296 toFetch->decodeUnblock[tid] = 1;
299 // Set status to squashing.
300 decodeStatus[tid] = Squashing;
302 for (int i=0; i<fromFetch->size; i++) {
303 if (fromFetch->insts[i]->threadNumber == tid &&
304 fromFetch->insts[i]->seqNum > squash_seq_num) {
305 fromFetch->insts[i]->setSquashed();
309 // Clear the instruction list and skid buffer in case they have any
311 while (!insts[tid].empty()) {
315 while (!skidBuffer[tid].empty()) {
316 skidBuffer[tid].pop();
319 // Squash instructions up until this one
320 cpu->removeInstsUntil(squash_seq_num, tid);
325 DefaultDecode<Impl>::squash(ThreadID tid)
327 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
329 if (decodeStatus[tid] == Blocked ||
330 decodeStatus[tid] == Unblocking) {
332 toFetch->decodeUnblock[tid] = 1;
334 // In syscall emulation, we can have both a block and a squash due
335 // to a syscall in the same cycle. This would cause both signals
336 // to be high. This shouldn't happen in full system.
337 // @todo: Determine if this still happens.
338 if (toFetch->decodeBlock[tid])
339 toFetch->decodeBlock[tid] = 0;
341 toFetch->decodeUnblock[tid] = 1;
345 // Set status to squashing.
346 decodeStatus[tid] = Squashing;
348 // Go through incoming instructions from fetch and squash them.
349 unsigned squash_count = 0;
351 for (int i=0; i<fromFetch->size; i++) {
352 if (fromFetch->insts[i]->threadNumber == tid) {
353 fromFetch->insts[i]->setSquashed();
358 // Clear the instruction list and skid buffer in case they have any
360 while (!insts[tid].empty()) {
364 while (!skidBuffer[tid].empty()) {
365 skidBuffer[tid].pop();
373 DefaultDecode<Impl>::skidInsert(ThreadID tid)
375 DynInstPtr inst = NULL;
377 while (!insts[tid].empty()) {
378 inst = insts[tid].front();
382 assert(tid == inst->threadNumber);
384 DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n",
385 inst->seqNum, inst->pcState(), inst->threadNumber);
387 skidBuffer[tid].push(inst);
390 // @todo: Eventually need to enforce this by not letting a thread
391 // fetch past its skidbuffer
392 assert(skidBuffer[tid].size() <= skidBufferMax);
397 DefaultDecode<Impl>::skidsEmpty()
399 list<ThreadID>::iterator threads = activeThreads->begin();
400 list<ThreadID>::iterator end = activeThreads->end();
402 while (threads != end) {
403 ThreadID tid = *threads++;
404 if (!skidBuffer[tid].empty())
413 DefaultDecode<Impl>::updateStatus()
415 bool any_unblocking = false;
417 list<ThreadID>::iterator threads = activeThreads->begin();
418 list<ThreadID>::iterator end = activeThreads->end();
420 while (threads != end) {
421 ThreadID tid = *threads++;
423 if (decodeStatus[tid] == Unblocking) {
424 any_unblocking = true;
429 // Decode will have activity if it's unblocking.
430 if (any_unblocking) {
431 if (_status == Inactive) {
434 DPRINTF(Activity, "Activating stage.\n");
436 cpu->activateStage(O3CPU::DecodeIdx);
439 // If it's not unblocking, then decode will not have any internal
440 // activity. Switch it to inactive.
441 if (_status == Active) {
443 DPRINTF(Activity, "Deactivating stage.\n");
445 cpu->deactivateStage(O3CPU::DecodeIdx);
450 template <class Impl>
452 DefaultDecode<Impl>::sortInsts()
454 int insts_from_fetch = fromFetch->size;
455 for (int i = 0; i < insts_from_fetch; ++i) {
456 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
462 DefaultDecode<Impl>::readStallSignals(ThreadID tid)
464 if (fromRename->renameBlock[tid]) {
465 stalls[tid].rename = true;
468 if (fromRename->renameUnblock[tid]) {
469 assert(stalls[tid].rename);
470 stalls[tid].rename = false;
473 if (fromIEW->iewBlock[tid]) {
474 stalls[tid].iew = true;
477 if (fromIEW->iewUnblock[tid]) {
478 assert(stalls[tid].iew);
479 stalls[tid].iew = false;
482 if (fromCommit->commitBlock[tid]) {
483 stalls[tid].commit = true;
486 if (fromCommit->commitUnblock[tid]) {
487 assert(stalls[tid].commit);
488 stalls[tid].commit = false;
492 template <class Impl>
494 DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid)
496 // Check if there's a squash signal, squash if there is.
497 // Check stall signals, block if necessary.
498 // If status was blocked
499 // Check if stall conditions have passed
500 // if so then go to unblocking
501 // If status was Squashing
502 // check if squashing is not high. Switch to running this cycle.
504 // Update the per thread stall statuses.
505 readStallSignals(tid);
507 // Check squash signals from commit.
508 if (fromCommit->commitInfo[tid].squash) {
510 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
511 "from commit.\n", tid);
518 // Check ROB squash signals from commit.
519 if (fromCommit->commitInfo[tid].robSquashing) {
520 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
522 // Continue to squash.
523 decodeStatus[tid] = Squashing;
528 if (checkStall(tid)) {
532 if (decodeStatus[tid] == Blocked) {
533 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
536 decodeStatus[tid] = Unblocking;
543 if (decodeStatus[tid] == Squashing) {
544 // Switch status to running if decode isn't being told to block or
545 // squash this cycle.
546 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
549 decodeStatus[tid] = Running;
554 // If we've reached this point, we have not gotten any signals that
555 // cause decode to change its status. Decode remains the same as before.
561 DefaultDecode<Impl>::tick()
563 wroteToTimeBuffer = false;
565 bool status_change = false;
569 list<ThreadID>::iterator threads = activeThreads->begin();
570 list<ThreadID>::iterator end = activeThreads->end();
574 //Check stall and squash signals.
575 while (threads != end) {
576 ThreadID tid = *threads++;
578 DPRINTF(Decode,"Processing [tid:%i]\n",tid);
579 status_change = checkSignalsAndUpdate(tid) || status_change;
581 decode(status_change, tid);
588 if (wroteToTimeBuffer) {
589 DPRINTF(Activity, "Activity this cycle.\n");
591 cpu->activityThisCycle();
597 DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid)
599 // If status is Running or idle,
600 // call decodeInsts()
601 // If status is Unblocking,
602 // buffer any instructions coming from fetch
603 // continue trying to empty skid buffer
604 // check if stall conditions have passed
606 if (decodeStatus[tid] == Blocked) {
607 ++decodeBlockedCycles;
608 } else if (decodeStatus[tid] == Squashing) {
609 ++decodeSquashCycles;
612 // Decode should try to decode as many instructions as its bandwidth
613 // will allow, as long as it is not currently blocked.
614 if (decodeStatus[tid] == Running ||
615 decodeStatus[tid] == Idle) {
616 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run "
620 } else if (decodeStatus[tid] == Unblocking) {
621 // Make sure that the skid buffer has something in it if the
622 // status is unblocking.
623 assert(!skidsEmpty());
625 // If the status was unblocking, then instructions from the skid
626 // buffer were used. Remove those instructions and handle
627 // the rest of unblocking.
630 if (fetchInstsValid()) {
631 // Add the current inputs to the skid buffer so they can be
632 // reprocessed when this stage unblocks.
636 status_change = unblock(tid) || status_change;
640 template <class Impl>
642 DefaultDecode<Impl>::decodeInsts(ThreadID tid)
644 // Instructions can come either from the skid buffer or the list of
645 // instructions coming from fetch, depending on decode's status.
646 int insts_available = decodeStatus[tid] == Unblocking ?
647 skidBuffer[tid].size() : insts[tid].size();
649 if (insts_available == 0) {
650 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
652 // Should I change the status to idle?
655 } else if (decodeStatus[tid] == Unblocking) {
656 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
658 ++decodeUnblockCycles;
659 } else if (decodeStatus[tid] == Running) {
665 std::queue<DynInstPtr>
666 &insts_to_decode = decodeStatus[tid] == Unblocking ?
667 skidBuffer[tid] : insts[tid];
669 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
671 while (insts_available > 0 && toRenameIndex < decodeWidth) {
672 assert(!insts_to_decode.empty());
674 inst = insts_to_decode.front();
676 insts_to_decode.pop();
678 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
679 "PC %s\n", tid, inst->seqNum, inst->pcState());
681 if (inst->isSquashed()) {
682 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is "
683 "squashed, skipping.\n",
684 tid, inst->seqNum, inst->pcState());
686 ++decodeSquashedInsts;
693 // Also check if instructions have no source registers. Mark
694 // them as ready to issue at any time. Not sure if this check
695 // should exist here or at a later stage; however it doesn't matter
696 // too much for function correctness.
697 if (inst->numSrcRegs() == 0) {
701 // This current instruction is valid, so add it into the decode
702 // queue. The next instruction may not be valid, so check to
703 // see if branches were predicted correctly.
704 toRename->insts[toRenameIndex] = inst;
708 ++decodeDecodedInsts;
712 inst->decodeTick = curTick() - inst->fetchTick;
715 // Ensure that if it was predicted as a branch, it really is a
717 if (inst->readPredTaken() && !inst->isControl()) {
718 panic("Instruction predicted as a branch!");
720 ++decodeControlMispred;
722 // Might want to set some sort of boolean and just do
723 // a check at the end
724 squash(inst, inst->threadNumber);
729 // Go ahead and compute any PC-relative branches.
730 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
731 ++decodeBranchResolved;
733 if (!(inst->branchTarget() == inst->readPredTarg())) {
734 ++decodeBranchMispred;
736 // Might want to set some sort of boolean and just do
737 // a check at the end
738 squash(inst, inst->threadNumber);
739 TheISA::PCState target = inst->branchTarget();
741 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n",
742 inst->seqNum, target);
743 //The micro pc after an instruction level branch should be 0
744 inst->setPredTarg(target);
750 // If we didn't process all instructions, then we will need to block
751 // and put all those instructions into the skid buffer.
752 if (!insts_to_decode.empty()) {
756 // Record that decode has written to the time buffer for activity
759 wroteToTimeBuffer = true;