src/cpu/o3/decode_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "cpu/o3/decode.hh"
  32
  33 template<class Impl>
  34 DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, Params *params)
  35     : cpu(_cpu),
  36       renameToDecodeDelay(params->renameToDecodeDelay),
  37       iewToDecodeDelay(params->iewToDecodeDelay),
  38       commitToDecodeDelay(params->commitToDecodeDelay),
  39       fetchToDecodeDelay(params->fetchToDecodeDelay),
  40       decodeWidth(params->decodeWidth),
  41       numThreads(params->numberOfThreads)
  42 {
  43     _status = Inactive;
  44
  45     // Setup status, make sure stall signals are clear.
  46     for (int i = 0; i < numThreads; ++i) {
  47         decodeStatus[i] = Idle;
  48
  49         stalls[i].rename = false;
  50         stalls[i].iew = false;
  51         stalls[i].commit = false;
  52     }
  53
  54     // @todo: Make into a parameter
  55     skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth;
  56 }
  57
  58 template <class Impl>
  59 std::string
  60 DefaultDecode<Impl>::name() const
  61 {
  62     return cpu->name() + ".decode";
  63 }
  64
  65 template <class Impl>
  66 void
  67 DefaultDecode<Impl>::regStats()
  68 {
  69     decodeIdleCycles
  70         .name(name() + ".DECODE:IdleCycles")
  71         .desc("Number of cycles decode is idle")
  72         .prereq(decodeIdleCycles);
  73     decodeBlockedCycles
  74         .name(name() + ".DECODE:BlockedCycles")
  75         .desc("Number of cycles decode is blocked")
  76         .prereq(decodeBlockedCycles);
  77     decodeRunCycles
  78         .name(name() + ".DECODE:RunCycles")
  79         .desc("Number of cycles decode is running")
  80         .prereq(decodeRunCycles);
  81     decodeUnblockCycles
  82         .name(name() + ".DECODE:UnblockCycles")
  83         .desc("Number of cycles decode is unblocking")
  84         .prereq(decodeUnblockCycles);
  85     decodeSquashCycles
  86         .name(name() + ".DECODE:SquashCycles")
  87         .desc("Number of cycles decode is squashing")
  88         .prereq(decodeSquashCycles);
  89     decodeBranchResolved
  90         .name(name() + ".DECODE:BranchResolved")
  91         .desc("Number of times decode resolved a branch")
  92         .prereq(decodeBranchResolved);
  93     decodeBranchMispred
  94         .name(name() + ".DECODE:BranchMispred")
  95         .desc("Number of times decode detected a branch misprediction")
  96         .prereq(decodeBranchMispred);
  97     decodeControlMispred
  98         .name(name() + ".DECODE:ControlMispred")
  99         .desc("Number of times decode detected an instruction incorrectly"
 100               " predicted as a control")
 101         .prereq(decodeControlMispred);
 102     decodeDecodedInsts
 103         .name(name() + ".DECODE:DecodedInsts")
 104         .desc("Number of instructions handled by decode")
 105         .prereq(decodeDecodedInsts);
 106     decodeSquashedInsts
 107         .name(name() + ".DECODE:SquashedInsts")
 108         .desc("Number of squashed instructions handled by decode")
 109         .prereq(decodeSquashedInsts);
 110 }
 111
 112 template<class Impl>
 113 void
 114 DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 115 {
 116     timeBuffer = tb_ptr;
 117
 118     // Setup wire to write information back to fetch.
 119     toFetch = timeBuffer->getWire(0);
 120
 121     // Create wires to get information from proper places in time buffer.
 122     fromRename = timeBuffer->getWire(-renameToDecodeDelay);
 123     fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
 124     fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
 125 }
 126
 127 template<class Impl>
 128 void
 129 DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
 130 {
 131     decodeQueue = dq_ptr;
 132
 133     // Setup wire to write information to proper place in decode queue.
 134     toRename = decodeQueue->getWire(0);
 135 }
 136
 137 template<class Impl>
 138 void
 139 DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
 140 {
 141     fetchQueue = fq_ptr;
 142
 143     // Setup wire to read information from fetch queue.
 144     fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
 145 }
 146
 147 template<class Impl>
 148 void
 149 DefaultDecode<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
 150 {
 151     activeThreads = at_ptr;
 152 }
 153
 154 template <class Impl>
 155 bool
 156 DefaultDecode<Impl>::drain()
 157 {
 158     // Decode is done draining at any time.
 159     cpu->signalDrained();
 160     return true;
 161 }
 162
 163 template <class Impl>
 164 void
 165 DefaultDecode<Impl>::takeOverFrom()
 166 {
 167     _status = Inactive;
 168
 169     // Be sure to reset state and clear out any old instructions.
 170     for (int i = 0; i < numThreads; ++i) {
 171         decodeStatus[i] = Idle;
 172
 173         stalls[i].rename = false;
 174         stalls[i].iew = false;
 175         stalls[i].commit = false;
 176         while (!insts[i].empty())
 177             insts[i].pop();
 178         while (!skidBuffer[i].empty())
 179             skidBuffer[i].pop();
 180         branchCount[i] = 0;
 181     }
 182     wroteToTimeBuffer = false;
 183 }
 184
 185 template<class Impl>
 186 bool
 187 DefaultDecode<Impl>::checkStall(unsigned tid) const
 188 {
 189     bool ret_val = false;
 190
 191     if (stalls[tid].rename) {
 192         DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
 193         ret_val = true;
 194     } else if (stalls[tid].iew) {
 195         DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
 196         ret_val = true;
 197     } else if (stalls[tid].commit) {
 198         DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
 199         ret_val = true;
 200     }
 201
 202     return ret_val;
 203 }
 204
 205 template<class Impl>
 206 inline bool
 207 DefaultDecode<Impl>::fetchInstsValid()
 208 {
 209     return fromFetch->size > 0;
 210 }
 211
 212 template<class Impl>
 213 bool
 214 DefaultDecode<Impl>::block(unsigned tid)
 215 {
 216     DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
 217
 218     // Add the current inputs to the skid buffer so they can be
 219     // reprocessed when this stage unblocks.
 220     skidInsert(tid);
 221
 222     // If the decode status is blocked or unblocking then decode has not yet
 223     // signalled fetch to unblock. In that case, there is no need to tell
 224     // fetch to block.
 225     if (decodeStatus[tid] != Blocked) {
 226         // Set the status to Blocked.
 227         decodeStatus[tid] = Blocked;
 228
 229         if (decodeStatus[tid] != Unblocking) {
 230             toFetch->decodeBlock[tid] = true;
 231             wroteToTimeBuffer = true;
 232         }
 233
 234         return true;
 235     }
 236
 237     return false;
 238 }
 239
 240 template<class Impl>
 241 bool
 242 DefaultDecode<Impl>::unblock(unsigned tid)
 243 {
 244     // Decode is done unblocking only if the skid buffer is empty.
 245     if (skidBuffer[tid].empty()) {
 246         DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
 247         toFetch->decodeUnblock[tid] = true;
 248         wroteToTimeBuffer = true;
 249
 250         decodeStatus[tid] = Running;
 251         return true;
 252     }
 253
 254     DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
 255
 256     return false;
 257 }
 258
 259 template<class Impl>
 260 void
 261 DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
 262 {
 263     DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction "
 264             "detected at decode.\n", tid);
 265
 266     // Send back mispredict information.
 267     toFetch->decodeInfo[tid].branchMispredict = true;
 268     toFetch->decodeInfo[tid].predIncorrect = true;
 269     toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
 270     toFetch->decodeInfo[tid].squash = true;
 271     toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
 272     ///FIXME There needs to be a way to set the nextPC and nextNPC
 273     ///explicitly for ISAs with delay slots.
 274     toFetch->decodeInfo[tid].nextNPC =
 275         inst->branchTarget() + sizeof(TheISA::MachInst);
 276     toFetch->decodeInfo[tid].nextMicroPC = inst->readMicroPC();
 277 #if ISA_HAS_DELAY_SLOT
 278     toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() !=
 279         (inst->readNextPC() + sizeof(TheISA::MachInst));
 280 #else
 281     toFetch->decodeInfo[tid].branchTaken =
 282         inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
 283 #endif
 284
 285     InstSeqNum squash_seq_num = inst->seqNum;
 286
 287     // Might have to tell fetch to unblock.
 288     if (decodeStatus[tid] == Blocked ||
 289         decodeStatus[tid] == Unblocking) {
 290         toFetch->decodeUnblock[tid] = 1;
 291     }
 292
 293     // Set status to squashing.
 294     decodeStatus[tid] = Squashing;
 295
 296     for (int i=0; i<fromFetch->size; i++) {
 297         if (fromFetch->insts[i]->threadNumber == tid &&
 298             fromFetch->insts[i]->seqNum > squash_seq_num) {
 299             fromFetch->insts[i]->setSquashed();
 300         }
 301     }
 302
 303     // Clear the instruction list and skid buffer in case they have any
 304     // insts in them.
 305     while (!insts[tid].empty()) {
 306         insts[tid].pop();
 307     }
 308
 309     while (!skidBuffer[tid].empty()) {
 310         skidBuffer[tid].pop();
 311     }
 312
 313     // Squash instructions up until this one
 314     cpu->removeInstsUntil(squash_seq_num, tid);
 315 }
 316
 317 template<class Impl>
 318 unsigned
 319 DefaultDecode<Impl>::squash(unsigned tid)
 320 {
 321     DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
 322
 323     if (decodeStatus[tid] == Blocked ||
 324         decodeStatus[tid] == Unblocking) {
 325 #if !FULL_SYSTEM
 326         // In syscall emulation, we can have both a block and a squash due
 327         // to a syscall in the same cycle.  This would cause both signals to
 328         // be high.  This shouldn't happen in full system.
 329         // @todo: Determine if this still happens.
 330         if (toFetch->decodeBlock[tid]) {
 331             toFetch->decodeBlock[tid] = 0;
 332         } else {
 333             toFetch->decodeUnblock[tid] = 1;
 334         }
 335 #else
 336         toFetch->decodeUnblock[tid] = 1;
 337 #endif
 338     }
 339
 340     // Set status to squashing.
 341     decodeStatus[tid] = Squashing;
 342
 343     // Go through incoming instructions from fetch and squash them.
 344     unsigned squash_count = 0;
 345
 346     for (int i=0; i<fromFetch->size; i++) {
 347         if (fromFetch->insts[i]->threadNumber == tid) {
 348             fromFetch->insts[i]->setSquashed();
 349             squash_count++;
 350         }
 351     }
 352
 353     // Clear the instruction list and skid buffer in case they have any
 354     // insts in them.
 355     while (!insts[tid].empty()) {
 356         insts[tid].pop();
 357     }
 358
 359     while (!skidBuffer[tid].empty()) {
 360         skidBuffer[tid].pop();
 361     }
 362
 363     return squash_count;
 364 }
 365
 366 template<class Impl>
 367 void
 368 DefaultDecode<Impl>::skidInsert(unsigned tid)
 369 {
 370     DynInstPtr inst = NULL;
 371
 372     while (!insts[tid].empty()) {
 373         inst = insts[tid].front();
 374
 375         insts[tid].pop();
 376
 377         assert(tid == inst->threadNumber);
 378
 379         DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n",
 380                 inst->seqNum, inst->readPC(), inst->threadNumber);
 381
 382         skidBuffer[tid].push(inst);
 383     }
 384
 385     // @todo: Eventually need to enforce this by not letting a thread
 386     // fetch past its skidbuffer
 387     assert(skidBuffer[tid].size() <= skidBufferMax);
 388 }
 389
 390 template<class Impl>
 391 bool
 392 DefaultDecode<Impl>::skidsEmpty()
 393 {
 394     std::list<unsigned>::iterator threads = activeThreads->begin();
 395     std::list<unsigned>::iterator end = activeThreads->end();
 396
 397     while (threads != end) {
 398         unsigned tid = *threads++;
 399         if (!skidBuffer[tid].empty())
 400             return false;
 401     }
 402
 403     return true;
 404 }
 405
 406 template<class Impl>
 407 void
 408 DefaultDecode<Impl>::updateStatus()
 409 {
 410     bool any_unblocking = false;
 411
 412     std::list<unsigned>::iterator threads = activeThreads->begin();
 413     std::list<unsigned>::iterator end = activeThreads->end();
 414
 415     while (threads != end) {
 416         unsigned tid = *threads++;
 417
 418         if (decodeStatus[tid] == Unblocking) {
 419             any_unblocking = true;
 420             break;
 421         }
 422     }
 423
 424     // Decode will have activity if it's unblocking.
 425     if (any_unblocking) {
 426         if (_status == Inactive) {
 427             _status = Active;
 428
 429             DPRINTF(Activity, "Activating stage.\n");
 430
 431             cpu->activateStage(O3CPU::DecodeIdx);
 432         }
 433     } else {
 434         // If it's not unblocking, then decode will not have any internal
 435         // activity.  Switch it to inactive.
 436         if (_status == Active) {
 437             _status = Inactive;
 438             DPRINTF(Activity, "Deactivating stage.\n");
 439
 440             cpu->deactivateStage(O3CPU::DecodeIdx);
 441         }
 442     }
 443 }
 444
 445 template <class Impl>
 446 void
 447 DefaultDecode<Impl>::sortInsts()
 448 {
 449     int insts_from_fetch = fromFetch->size;
 450 #ifdef DEBUG
 451     for (int i=0; i < numThreads; i++)
 452         assert(insts[i].empty());
 453 #endif
 454     for (int i = 0; i < insts_from_fetch; ++i) {
 455         insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
 456     }
 457 }
 458
 459 template<class Impl>
 460 void
 461 DefaultDecode<Impl>::readStallSignals(unsigned tid)
 462 {
 463     if (fromRename->renameBlock[tid]) {
 464         stalls[tid].rename = true;
 465     }
 466
 467     if (fromRename->renameUnblock[tid]) {
 468         assert(stalls[tid].rename);
 469         stalls[tid].rename = false;
 470     }
 471
 472     if (fromIEW->iewBlock[tid]) {
 473         stalls[tid].iew = true;
 474     }
 475
 476     if (fromIEW->iewUnblock[tid]) {
 477         assert(stalls[tid].iew);
 478         stalls[tid].iew = false;
 479     }
 480
 481     if (fromCommit->commitBlock[tid]) {
 482         stalls[tid].commit = true;
 483     }
 484
 485     if (fromCommit->commitUnblock[tid]) {
 486         assert(stalls[tid].commit);
 487         stalls[tid].commit = false;
 488     }
 489 }
 490
 491 template <class Impl>
 492 bool
 493 DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid)
 494 {
 495     // Check if there's a squash signal, squash if there is.
 496     // Check stall signals, block if necessary.
 497     // If status was blocked
 498     //     Check if stall conditions have passed
 499     //         if so then go to unblocking
 500     // If status was Squashing
 501     //     check if squashing is not high.  Switch to running this cycle.
 502
 503     // Update the per thread stall statuses.
 504     readStallSignals(tid);
 505
 506     // Check squash signals from commit.
 507     if (fromCommit->commitInfo[tid].squash) {
 508
 509         DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
 510                 "from commit.\n", tid);
 511
 512         squash(tid);
 513
 514         return true;
 515     }
 516
 517     // Check ROB squash signals from commit.
 518     if (fromCommit->commitInfo[tid].robSquashing) {
 519         DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
 520
 521         // Continue to squash.
 522         decodeStatus[tid] = Squashing;
 523
 524         return true;
 525     }
 526
 527     if (checkStall(tid)) {
 528         return block(tid);
 529     }
 530
 531     if (decodeStatus[tid] == Blocked) {
 532         DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
 533                 tid);
 534
 535         decodeStatus[tid] = Unblocking;
 536
 537         unblock(tid);
 538
 539         return true;
 540     }
 541
 542     if (decodeStatus[tid] == Squashing) {
 543         // Switch status to running if decode isn't being told to block or
 544         // squash this cycle.
 545         DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
 546                 tid);
 547
 548         decodeStatus[tid] = Running;
 549
 550         return false;
 551     }
 552
 553     // If we've reached this point, we have not gotten any signals that
 554     // cause decode to change its status.  Decode remains the same as before.
 555     return false;
 556 }
 557
 558 template<class Impl>
 559 void
 560 DefaultDecode<Impl>::tick()
 561 {
 562     wroteToTimeBuffer = false;
 563
 564     bool status_change = false;
 565
 566     toRenameIndex = 0;
 567
 568     std::list<unsigned>::iterator threads = activeThreads->begin();
 569     std::list<unsigned>::iterator end = activeThreads->end();
 570
 571     sortInsts();
 572
 573     //Check stall and squash signals.
 574     while (threads != end) {
 575         unsigned tid = *threads++;
 576
 577         DPRINTF(Decode,"Processing [tid:%i]\n",tid);
 578         status_change =  checkSignalsAndUpdate(tid) || status_change;
 579
 580         decode(status_change, tid);
 581     }
 582
 583     if (status_change) {
 584         updateStatus();
 585     }
 586
 587     if (wroteToTimeBuffer) {
 588         DPRINTF(Activity, "Activity this cycle.\n");
 589
 590         cpu->activityThisCycle();
 591     }
 592 }
 593
 594 template<class Impl>
 595 void
 596 DefaultDecode<Impl>::decode(bool &status_change, unsigned tid)
 597 {
 598     // If status is Running or idle,
 599     //     call decodeInsts()
 600     // If status is Unblocking,
 601     //     buffer any instructions coming from fetch
 602     //     continue trying to empty skid buffer
 603     //     check if stall conditions have passed
 604
 605     if (decodeStatus[tid] == Blocked) {
 606         ++decodeBlockedCycles;
 607     } else if (decodeStatus[tid] == Squashing) {
 608         ++decodeSquashCycles;
 609     }
 610
 611     // Decode should try to decode as many instructions as its bandwidth
 612     // will allow, as long as it is not currently blocked.
 613     if (decodeStatus[tid] == Running ||
 614         decodeStatus[tid] == Idle) {
 615         DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run "
 616                 "stage.\n",tid);
 617
 618         decodeInsts(tid);
 619     } else if (decodeStatus[tid] == Unblocking) {
 620         // Make sure that the skid buffer has something in it if the
 621         // status is unblocking.
 622         assert(!skidsEmpty());
 623
 624         // If the status was unblocking, then instructions from the skid
 625         // buffer were used.  Remove those instructions and handle
 626         // the rest of unblocking.
 627         decodeInsts(tid);
 628
 629         if (fetchInstsValid()) {
 630             // Add the current inputs to the skid buffer so they can be
 631             // reprocessed when this stage unblocks.
 632             skidInsert(tid);
 633         }
 634
 635         status_change = unblock(tid) || status_change;
 636     }
 637 }
 638
 639 template <class Impl>
 640 void
 641 DefaultDecode<Impl>::decodeInsts(unsigned tid)
 642 {
 643     // Instructions can come either from the skid buffer or the list of
 644     // instructions coming from fetch, depending on decode's status.
 645     int insts_available = decodeStatus[tid] == Unblocking ?
 646         skidBuffer[tid].size() : insts[tid].size();
 647
 648     if (insts_available == 0) {
 649         DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
 650                 " early.\n",tid);
 651         // Should I change the status to idle?
 652         ++decodeIdleCycles;
 653         return;
 654     } else if (decodeStatus[tid] == Unblocking) {
 655         DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
 656                 "buffer.\n",tid);
 657         ++decodeUnblockCycles;
 658     } else if (decodeStatus[tid] == Running) {
 659         ++decodeRunCycles;
 660     }
 661
 662     DynInstPtr inst;
 663
 664     std::queue<DynInstPtr>
 665         &insts_to_decode = decodeStatus[tid] == Unblocking ?
 666         skidBuffer[tid] : insts[tid];
 667
 668     DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
 669
 670     while (insts_available > 0 && toRenameIndex < decodeWidth) {
 671         assert(!insts_to_decode.empty());
 672
 673         inst = insts_to_decode.front();
 674
 675         insts_to_decode.pop();
 676
 677         DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
 678                 "PC %#x\n",
 679                 tid, inst->seqNum, inst->readPC());
 680
 681         if (inst->isSquashed()) {
 682             DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is "
 683                     "squashed, skipping.\n",
 684                     tid, inst->seqNum, inst->readPC());
 685
 686             ++decodeSquashedInsts;
 687
 688             --insts_available;
 689
 690             continue;
 691         }
 692
 693         // Also check if instructions have no source registers.  Mark
 694         // them as ready to issue at any time.  Not sure if this check
 695         // should exist here or at a later stage; however it doesn't matter
 696         // too much for function correctness.
 697         if (inst->numSrcRegs() == 0) {
 698             inst->setCanIssue();
 699         }
 700
 701         // This current instruction is valid, so add it into the decode
 702         // queue.  The next instruction may not be valid, so check to
 703         // see if branches were predicted correctly.
 704         toRename->insts[toRenameIndex] = inst;
 705
 706         ++(toRename->size);
 707         ++toRenameIndex;
 708         ++decodeDecodedInsts;
 709         --insts_available;
 710
 711         // Ensure that if it was predicted as a branch, it really is a
 712         // branch.
 713         if (inst->readPredTaken() && !inst->isControl()) {
 714             DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n",
 715                     inst->readPredPC(), inst->readNextPC() + 4);
 716
 717             panic("Instruction predicted as a branch!");
 718
 719             ++decodeControlMispred;
 720
 721             // Might want to set some sort of boolean and just do
 722             // a check at the end
 723             squash(inst, inst->threadNumber);
 724
 725             break;
 726         }
 727
 728         // Go ahead and compute any PC-relative branches.
 729         if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
 730             ++decodeBranchResolved;
 731
 732             if (inst->branchTarget() != inst->readPredPC()) {
 733                 ++decodeBranchMispred;
 734
 735                 // Might want to set some sort of boolean and just do
 736                 // a check at the end
 737                 squash(inst, inst->threadNumber);
 738                 Addr target = inst->branchTarget();
 739                 //The micro pc after an instruction level branch should be 0
 740                 inst->setPredTarg(target, target + sizeof(TheISA::MachInst), 0);
 741                 break;
 742             }
 743         }
 744     }
 745
 746     // If we didn't process all instructions, then we will need to block
 747     // and put all those instructions into the skid buffer.
 748     if (!insts_to_decode.empty()) {
 749         block(tid);
 750     }
 751
 752     // Record that decode has written to the time buffer for activity
 753     // tracking.
 754     if (toRenameIndex) {
 755         wroteToTimeBuffer = true;
 756     }
 757 }