src/cpu/o3/decode_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "cpu/o3/decode.hh"
  32
  33 #include "params/DerivO3CPU.hh"
  34
  35 template<class Impl>
  36 DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
  37     : cpu(_cpu),
  38       renameToDecodeDelay(params->renameToDecodeDelay),
  39       iewToDecodeDelay(params->iewToDecodeDelay),
  40       commitToDecodeDelay(params->commitToDecodeDelay),
  41       fetchToDecodeDelay(params->fetchToDecodeDelay),
  42       decodeWidth(params->decodeWidth),
  43       numThreads(params->numThreads)
  44 {
  45     _status = Inactive;
  46
  47     // Setup status, make sure stall signals are clear.
  48     for (int i = 0; i < numThreads; ++i) {
  49         decodeStatus[i] = Idle;
  50
  51         stalls[i].rename = false;
  52         stalls[i].iew = false;
  53         stalls[i].commit = false;
  54     }
  55
  56     // @todo: Make into a parameter
  57     skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth;
  58 }
  59
  60 template <class Impl>
  61 std::string
  62 DefaultDecode<Impl>::name() const
  63 {
  64     return cpu->name() + ".decode";
  65 }
  66
  67 template <class Impl>
  68 void
  69 DefaultDecode<Impl>::regStats()
  70 {
  71     decodeIdleCycles
  72         .name(name() + ".DECODE:IdleCycles")
  73         .desc("Number of cycles decode is idle")
  74         .prereq(decodeIdleCycles);
  75     decodeBlockedCycles
  76         .name(name() + ".DECODE:BlockedCycles")
  77         .desc("Number of cycles decode is blocked")
  78         .prereq(decodeBlockedCycles);
  79     decodeRunCycles
  80         .name(name() + ".DECODE:RunCycles")
  81         .desc("Number of cycles decode is running")
  82         .prereq(decodeRunCycles);
  83     decodeUnblockCycles
  84         .name(name() + ".DECODE:UnblockCycles")
  85         .desc("Number of cycles decode is unblocking")
  86         .prereq(decodeUnblockCycles);
  87     decodeSquashCycles
  88         .name(name() + ".DECODE:SquashCycles")
  89         .desc("Number of cycles decode is squashing")
  90         .prereq(decodeSquashCycles);
  91     decodeBranchResolved
  92         .name(name() + ".DECODE:BranchResolved")
  93         .desc("Number of times decode resolved a branch")
  94         .prereq(decodeBranchResolved);
  95     decodeBranchMispred
  96         .name(name() + ".DECODE:BranchMispred")
  97         .desc("Number of times decode detected a branch misprediction")
  98         .prereq(decodeBranchMispred);
  99     decodeControlMispred
 100         .name(name() + ".DECODE:ControlMispred")
 101         .desc("Number of times decode detected an instruction incorrectly"
 102               " predicted as a control")
 103         .prereq(decodeControlMispred);
 104     decodeDecodedInsts
 105         .name(name() + ".DECODE:DecodedInsts")
 106         .desc("Number of instructions handled by decode")
 107         .prereq(decodeDecodedInsts);
 108     decodeSquashedInsts
 109         .name(name() + ".DECODE:SquashedInsts")
 110         .desc("Number of squashed instructions handled by decode")
 111         .prereq(decodeSquashedInsts);
 112 }
 113
 114 template<class Impl>
 115 void
 116 DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 117 {
 118     timeBuffer = tb_ptr;
 119
 120     // Setup wire to write information back to fetch.
 121     toFetch = timeBuffer->getWire(0);
 122
 123     // Create wires to get information from proper places in time buffer.
 124     fromRename = timeBuffer->getWire(-renameToDecodeDelay);
 125     fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
 126     fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
 127 }
 128
 129 template<class Impl>
 130 void
 131 DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
 132 {
 133     decodeQueue = dq_ptr;
 134
 135     // Setup wire to write information to proper place in decode queue.
 136     toRename = decodeQueue->getWire(0);
 137 }
 138
 139 template<class Impl>
 140 void
 141 DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
 142 {
 143     fetchQueue = fq_ptr;
 144
 145     // Setup wire to read information from fetch queue.
 146     fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
 147 }
 148
 149 template<class Impl>
 150 void
 151 DefaultDecode<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
 152 {
 153     activeThreads = at_ptr;
 154 }
 155
 156 template <class Impl>
 157 bool
 158 DefaultDecode<Impl>::drain()
 159 {
 160     // Decode is done draining at any time.
 161     cpu->signalDrained();
 162     return true;
 163 }
 164
 165 template <class Impl>
 166 void
 167 DefaultDecode<Impl>::takeOverFrom()
 168 {
 169     _status = Inactive;
 170
 171     // Be sure to reset state and clear out any old instructions.
 172     for (int i = 0; i < numThreads; ++i) {
 173         decodeStatus[i] = Idle;
 174
 175         stalls[i].rename = false;
 176         stalls[i].iew = false;
 177         stalls[i].commit = false;
 178         while (!insts[i].empty())
 179             insts[i].pop();
 180         while (!skidBuffer[i].empty())
 181             skidBuffer[i].pop();
 182         branchCount[i] = 0;
 183     }
 184     wroteToTimeBuffer = false;
 185 }
 186
 187 template<class Impl>
 188 bool
 189 DefaultDecode<Impl>::checkStall(unsigned tid) const
 190 {
 191     bool ret_val = false;
 192
 193     if (stalls[tid].rename) {
 194         DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
 195         ret_val = true;
 196     } else if (stalls[tid].iew) {
 197         DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
 198         ret_val = true;
 199     } else if (stalls[tid].commit) {
 200         DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
 201         ret_val = true;
 202     }
 203
 204     return ret_val;
 205 }
 206
 207 template<class Impl>
 208 inline bool
 209 DefaultDecode<Impl>::fetchInstsValid()
 210 {
 211     return fromFetch->size > 0;
 212 }
 213
 214 template<class Impl>
 215 bool
 216 DefaultDecode<Impl>::block(unsigned tid)
 217 {
 218     DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
 219
 220     // Add the current inputs to the skid buffer so they can be
 221     // reprocessed when this stage unblocks.
 222     skidInsert(tid);
 223
 224     // If the decode status is blocked or unblocking then decode has not yet
 225     // signalled fetch to unblock. In that case, there is no need to tell
 226     // fetch to block.
 227     if (decodeStatus[tid] != Blocked) {
 228         // Set the status to Blocked.
 229         decodeStatus[tid] = Blocked;
 230
 231         if (decodeStatus[tid] != Unblocking) {
 232             toFetch->decodeBlock[tid] = true;
 233             wroteToTimeBuffer = true;
 234         }
 235
 236         return true;
 237     }
 238
 239     return false;
 240 }
 241
 242 template<class Impl>
 243 bool
 244 DefaultDecode<Impl>::unblock(unsigned tid)
 245 {
 246     // Decode is done unblocking only if the skid buffer is empty.
 247     if (skidBuffer[tid].empty()) {
 248         DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
 249         toFetch->decodeUnblock[tid] = true;
 250         wroteToTimeBuffer = true;
 251
 252         decodeStatus[tid] = Running;
 253         return true;
 254     }
 255
 256     DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
 257
 258     return false;
 259 }
 260
 261 template<class Impl>
 262 void
 263 DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
 264 {
 265     DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch prediction "
 266             "detected at decode.\n", tid, inst->seqNum);
 267
 268     // Send back mispredict information.
 269     toFetch->decodeInfo[tid].branchMispredict = true;
 270     toFetch->decodeInfo[tid].predIncorrect = true;
 271     toFetch->decodeInfo[tid].squash = true;
 272     toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
 273     toFetch->decodeInfo[tid].nextMicroPC = inst->readMicroPC();
 274
 275 #if ISA_HAS_DELAY_SLOT
 276     toFetch->decodeInfo[tid].nextPC = inst->readPC() + sizeof(TheISA::MachInst);
 277     toFetch->decodeInfo[tid].nextNPC = inst->branchTarget();
 278     toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() !=
 279         (inst->readNextPC() + sizeof(TheISA::MachInst));
 280 #else
 281     toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
 282     toFetch->decodeInfo[tid].nextNPC =
 283         inst->branchTarget() + sizeof(TheISA::MachInst);
 284     toFetch->decodeInfo[tid].branchTaken =
 285         inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
 286 #endif
 287
 288
 289     InstSeqNum squash_seq_num = inst->seqNum;
 290
 291     // Might have to tell fetch to unblock.
 292     if (decodeStatus[tid] == Blocked ||
 293         decodeStatus[tid] == Unblocking) {
 294         toFetch->decodeUnblock[tid] = 1;
 295     }
 296
 297     // Set status to squashing.
 298     decodeStatus[tid] = Squashing;
 299
 300     for (int i=0; i<fromFetch->size; i++) {
 301         if (fromFetch->insts[i]->threadNumber == tid &&
 302             fromFetch->insts[i]->seqNum > squash_seq_num) {
 303             fromFetch->insts[i]->setSquashed();
 304         }
 305     }
 306
 307     // Clear the instruction list and skid buffer in case they have any
 308     // insts in them.
 309     while (!insts[tid].empty()) {
 310         insts[tid].pop();
 311     }
 312
 313     while (!skidBuffer[tid].empty()) {
 314         skidBuffer[tid].pop();
 315     }
 316
 317     // Squash instructions up until this one
 318     cpu->removeInstsUntil(squash_seq_num, tid);
 319 }
 320
 321 template<class Impl>
 322 unsigned
 323 DefaultDecode<Impl>::squash(unsigned tid)
 324 {
 325     DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
 326
 327     if (decodeStatus[tid] == Blocked ||
 328         decodeStatus[tid] == Unblocking) {
 329 #if !FULL_SYSTEM
 330         // In syscall emulation, we can have both a block and a squash due
 331         // to a syscall in the same cycle.  This would cause both signals to
 332         // be high.  This shouldn't happen in full system.
 333         // @todo: Determine if this still happens.
 334         if (toFetch->decodeBlock[tid]) {
 335             toFetch->decodeBlock[tid] = 0;
 336         } else {
 337             toFetch->decodeUnblock[tid] = 1;
 338         }
 339 #else
 340         toFetch->decodeUnblock[tid] = 1;
 341 #endif
 342     }
 343
 344     // Set status to squashing.
 345     decodeStatus[tid] = Squashing;
 346
 347     // Go through incoming instructions from fetch and squash them.
 348     unsigned squash_count = 0;
 349
 350     for (int i=0; i<fromFetch->size; i++) {
 351         if (fromFetch->insts[i]->threadNumber == tid) {
 352             fromFetch->insts[i]->setSquashed();
 353             squash_count++;
 354         }
 355     }
 356
 357     // Clear the instruction list and skid buffer in case they have any
 358     // insts in them.
 359     while (!insts[tid].empty()) {
 360         insts[tid].pop();
 361     }
 362
 363     while (!skidBuffer[tid].empty()) {
 364         skidBuffer[tid].pop();
 365     }
 366
 367     return squash_count;
 368 }
 369
 370 template<class Impl>
 371 void
 372 DefaultDecode<Impl>::skidInsert(unsigned tid)
 373 {
 374     DynInstPtr inst = NULL;
 375
 376     while (!insts[tid].empty()) {
 377         inst = insts[tid].front();
 378
 379         insts[tid].pop();
 380
 381         assert(tid == inst->threadNumber);
 382
 383         DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n",
 384                 inst->seqNum, inst->readPC(), inst->threadNumber);
 385
 386         skidBuffer[tid].push(inst);
 387     }
 388
 389     // @todo: Eventually need to enforce this by not letting a thread
 390     // fetch past its skidbuffer
 391     assert(skidBuffer[tid].size() <= skidBufferMax);
 392 }
 393
 394 template<class Impl>
 395 bool
 396 DefaultDecode<Impl>::skidsEmpty()
 397 {
 398     std::list<unsigned>::iterator threads = activeThreads->begin();
 399     std::list<unsigned>::iterator end = activeThreads->end();
 400
 401     while (threads != end) {
 402         unsigned tid = *threads++;
 403         if (!skidBuffer[tid].empty())
 404             return false;
 405     }
 406
 407     return true;
 408 }
 409
 410 template<class Impl>
 411 void
 412 DefaultDecode<Impl>::updateStatus()
 413 {
 414     bool any_unblocking = false;
 415
 416     std::list<unsigned>::iterator threads = activeThreads->begin();
 417     std::list<unsigned>::iterator end = activeThreads->end();
 418
 419     while (threads != end) {
 420         unsigned tid = *threads++;
 421
 422         if (decodeStatus[tid] == Unblocking) {
 423             any_unblocking = true;
 424             break;
 425         }
 426     }
 427
 428     // Decode will have activity if it's unblocking.
 429     if (any_unblocking) {
 430         if (_status == Inactive) {
 431             _status = Active;
 432
 433             DPRINTF(Activity, "Activating stage.\n");
 434
 435             cpu->activateStage(O3CPU::DecodeIdx);
 436         }
 437     } else {
 438         // If it's not unblocking, then decode will not have any internal
 439         // activity.  Switch it to inactive.
 440         if (_status == Active) {
 441             _status = Inactive;
 442             DPRINTF(Activity, "Deactivating stage.\n");
 443
 444             cpu->deactivateStage(O3CPU::DecodeIdx);
 445         }
 446     }
 447 }
 448
 449 template <class Impl>
 450 void
 451 DefaultDecode<Impl>::sortInsts()
 452 {
 453     int insts_from_fetch = fromFetch->size;
 454 #ifdef DEBUG
 455     for (int i=0; i < numThreads; i++)
 456         assert(insts[i].empty());
 457 #endif
 458     for (int i = 0; i < insts_from_fetch; ++i) {
 459         insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
 460     }
 461 }
 462
 463 template<class Impl>
 464 void
 465 DefaultDecode<Impl>::readStallSignals(unsigned tid)
 466 {
 467     if (fromRename->renameBlock[tid]) {
 468         stalls[tid].rename = true;
 469     }
 470
 471     if (fromRename->renameUnblock[tid]) {
 472         assert(stalls[tid].rename);
 473         stalls[tid].rename = false;
 474     }
 475
 476     if (fromIEW->iewBlock[tid]) {
 477         stalls[tid].iew = true;
 478     }
 479
 480     if (fromIEW->iewUnblock[tid]) {
 481         assert(stalls[tid].iew);
 482         stalls[tid].iew = false;
 483     }
 484
 485     if (fromCommit->commitBlock[tid]) {
 486         stalls[tid].commit = true;
 487     }
 488
 489     if (fromCommit->commitUnblock[tid]) {
 490         assert(stalls[tid].commit);
 491         stalls[tid].commit = false;
 492     }
 493 }
 494
 495 template <class Impl>
 496 bool
 497 DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid)
 498 {
 499     // Check if there's a squash signal, squash if there is.
 500     // Check stall signals, block if necessary.
 501     // If status was blocked
 502     //     Check if stall conditions have passed
 503     //         if so then go to unblocking
 504     // If status was Squashing
 505     //     check if squashing is not high.  Switch to running this cycle.
 506
 507     // Update the per thread stall statuses.
 508     readStallSignals(tid);
 509
 510     // Check squash signals from commit.
 511     if (fromCommit->commitInfo[tid].squash) {
 512
 513         DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
 514                 "from commit.\n", tid);
 515
 516         squash(tid);
 517
 518         return true;
 519     }
 520
 521     // Check ROB squash signals from commit.
 522     if (fromCommit->commitInfo[tid].robSquashing) {
 523         DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
 524
 525         // Continue to squash.
 526         decodeStatus[tid] = Squashing;
 527
 528         return true;
 529     }
 530
 531     if (checkStall(tid)) {
 532         return block(tid);
 533     }
 534
 535     if (decodeStatus[tid] == Blocked) {
 536         DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
 537                 tid);
 538
 539         decodeStatus[tid] = Unblocking;
 540
 541         unblock(tid);
 542
 543         return true;
 544     }
 545
 546     if (decodeStatus[tid] == Squashing) {
 547         // Switch status to running if decode isn't being told to block or
 548         // squash this cycle.
 549         DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
 550                 tid);
 551
 552         decodeStatus[tid] = Running;
 553
 554         return false;
 555     }
 556
 557     // If we've reached this point, we have not gotten any signals that
 558     // cause decode to change its status.  Decode remains the same as before.
 559     return false;
 560 }
 561
 562 template<class Impl>
 563 void
 564 DefaultDecode<Impl>::tick()
 565 {
 566     wroteToTimeBuffer = false;
 567
 568     bool status_change = false;
 569
 570     toRenameIndex = 0;
 571
 572     std::list<unsigned>::iterator threads = activeThreads->begin();
 573     std::list<unsigned>::iterator end = activeThreads->end();
 574
 575     sortInsts();
 576
 577     //Check stall and squash signals.
 578     while (threads != end) {
 579         unsigned tid = *threads++;
 580
 581         DPRINTF(Decode,"Processing [tid:%i]\n",tid);
 582         status_change =  checkSignalsAndUpdate(tid) || status_change;
 583
 584         decode(status_change, tid);
 585     }
 586
 587     if (status_change) {
 588         updateStatus();
 589     }
 590
 591     if (wroteToTimeBuffer) {
 592         DPRINTF(Activity, "Activity this cycle.\n");
 593
 594         cpu->activityThisCycle();
 595     }
 596 }
 597
 598 template<class Impl>
 599 void
 600 DefaultDecode<Impl>::decode(bool &status_change, unsigned tid)
 601 {
 602     // If status is Running or idle,
 603     //     call decodeInsts()
 604     // If status is Unblocking,
 605     //     buffer any instructions coming from fetch
 606     //     continue trying to empty skid buffer
 607     //     check if stall conditions have passed
 608
 609     if (decodeStatus[tid] == Blocked) {
 610         ++decodeBlockedCycles;
 611     } else if (decodeStatus[tid] == Squashing) {
 612         ++decodeSquashCycles;
 613     }
 614
 615     // Decode should try to decode as many instructions as its bandwidth
 616     // will allow, as long as it is not currently blocked.
 617     if (decodeStatus[tid] == Running ||
 618         decodeStatus[tid] == Idle) {
 619         DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run "
 620                 "stage.\n",tid);
 621
 622         decodeInsts(tid);
 623     } else if (decodeStatus[tid] == Unblocking) {
 624         // Make sure that the skid buffer has something in it if the
 625         // status is unblocking.
 626         assert(!skidsEmpty());
 627
 628         // If the status was unblocking, then instructions from the skid
 629         // buffer were used.  Remove those instructions and handle
 630         // the rest of unblocking.
 631         decodeInsts(tid);
 632
 633         if (fetchInstsValid()) {
 634             // Add the current inputs to the skid buffer so they can be
 635             // reprocessed when this stage unblocks.
 636             skidInsert(tid);
 637         }
 638
 639         status_change = unblock(tid) || status_change;
 640     }
 641 }
 642
 643 template <class Impl>
 644 void
 645 DefaultDecode<Impl>::decodeInsts(unsigned tid)
 646 {
 647     // Instructions can come either from the skid buffer or the list of
 648     // instructions coming from fetch, depending on decode's status.
 649     int insts_available = decodeStatus[tid] == Unblocking ?
 650         skidBuffer[tid].size() : insts[tid].size();
 651
 652     if (insts_available == 0) {
 653         DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
 654                 " early.\n",tid);
 655         // Should I change the status to idle?
 656         ++decodeIdleCycles;
 657         return;
 658     } else if (decodeStatus[tid] == Unblocking) {
 659         DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
 660                 "buffer.\n",tid);
 661         ++decodeUnblockCycles;
 662     } else if (decodeStatus[tid] == Running) {
 663         ++decodeRunCycles;
 664     }
 665
 666     DynInstPtr inst;
 667
 668     std::queue<DynInstPtr>
 669         &insts_to_decode = decodeStatus[tid] == Unblocking ?
 670         skidBuffer[tid] : insts[tid];
 671
 672     DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
 673
 674     while (insts_available > 0 && toRenameIndex < decodeWidth) {
 675         assert(!insts_to_decode.empty());
 676
 677         inst = insts_to_decode.front();
 678
 679         insts_to_decode.pop();
 680
 681         DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
 682                 "PC %#x\n",
 683                 tid, inst->seqNum, inst->readPC());
 684
 685         if (inst->isSquashed()) {
 686             DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is "
 687                     "squashed, skipping.\n",
 688                     tid, inst->seqNum, inst->readPC());
 689
 690             ++decodeSquashedInsts;
 691
 692             --insts_available;
 693
 694             continue;
 695         }
 696
 697         // Also check if instructions have no source registers.  Mark
 698         // them as ready to issue at any time.  Not sure if this check
 699         // should exist here or at a later stage; however it doesn't matter
 700         // too much for function correctness.
 701         if (inst->numSrcRegs() == 0) {
 702             inst->setCanIssue();
 703         }
 704
 705         // This current instruction is valid, so add it into the decode
 706         // queue.  The next instruction may not be valid, so check to
 707         // see if branches were predicted correctly.
 708         toRename->insts[toRenameIndex] = inst;
 709
 710         ++(toRename->size);
 711         ++toRenameIndex;
 712         ++decodeDecodedInsts;
 713         --insts_available;
 714
 715         // Ensure that if it was predicted as a branch, it really is a
 716         // branch.
 717         if (inst->readPredTaken() && !inst->isControl()) {
 718             DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n",
 719                     inst->readPredPC(), inst->readNextPC() + 4);
 720
 721             panic("Instruction predicted as a branch!");
 722
 723             ++decodeControlMispred;
 724
 725             // Might want to set some sort of boolean and just do
 726             // a check at the end
 727             squash(inst, inst->threadNumber);
 728
 729             break;
 730         }
 731
 732         // Go ahead and compute any PC-relative branches.
 733         if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
 734             ++decodeBranchResolved;
 735
 736             if (inst->branchTarget() != inst->readPredPC()) {
 737                 ++decodeBranchMispred;
 738
 739                 // Might want to set some sort of boolean and just do
 740                 // a check at the end
 741                 squash(inst, inst->threadNumber);
 742                 Addr target = inst->branchTarget();
 743
 744 #if ISA_HAS_DELAY_SLOT
 745                 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %#x  PredNextPC: %#x\n",
 746                         inst->seqNum, inst->readPC() + sizeof(TheISA::MachInst), target);
 747
 748                 //The micro pc after an instruction level branch should be 0
 749                 inst->setPredTarg(inst->readPC() + sizeof(TheISA::MachInst), target, 0);
 750 #else
 751                 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %#x  PredNextPC: %#x\n",
 752                         inst->seqNum, target, target + sizeof(TheISA::MachInst));
 753                 //The micro pc after an instruction level branch should be 0
 754                 inst->setPredTarg(target, target + sizeof(TheISA::MachInst), 0);
 755 #endif
 756                 break;
 757             }
 758         }
 759     }
 760
 761     // If we didn't process all instructions, then we will need to block
 762     // and put all those instructions into the skid buffer.
 763     if (!insts_to_decode.empty()) {
 764         block(tid);
 765     }
 766
 767     // Record that decode has written to the time buffer for activity
 768     // tracking.
 769     if (toRenameIndex) {
 770         wroteToTimeBuffer = true;
 771     }
 772 }