src/cpu/o3/decode_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "arch/types.hh"
  32 #include "base/trace.hh"
  33 #include "config/the_isa.hh"
  34 #include "cpu/o3/decode.hh"
  35 #include "cpu/inst_seq.hh"
  36 #include "debug/Activity.hh"
  37 #include "debug/Decode.hh"
  38 #include "params/DerivO3CPU.hh"
  39 #include "sim/full_system.hh"
  40
  41 using namespace std;
  42
  43 template<class Impl>
  44 DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
  45     : cpu(_cpu),
  46       renameToDecodeDelay(params->renameToDecodeDelay),
  47       iewToDecodeDelay(params->iewToDecodeDelay),
  48       commitToDecodeDelay(params->commitToDecodeDelay),
  49       fetchToDecodeDelay(params->fetchToDecodeDelay),
  50       decodeWidth(params->decodeWidth),
  51       numThreads(params->numThreads)
  52 {
  53     _status = Inactive;
  54
  55     // Setup status, make sure stall signals are clear.
  56     for (ThreadID tid = 0; tid < numThreads; ++tid) {
  57         decodeStatus[tid] = Idle;
  58
  59         stalls[tid].rename = false;
  60         stalls[tid].iew = false;
  61         stalls[tid].commit = false;
  62     }
  63
  64     // @todo: Make into a parameter
  65     skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth;
  66 }
  67
  68 template <class Impl>
  69 std::string
  70 DefaultDecode<Impl>::name() const
  71 {
  72     return cpu->name() + ".decode";
  73 }
  74
  75 template <class Impl>
  76 void
  77 DefaultDecode<Impl>::regStats()
  78 {
  79     decodeIdleCycles
  80         .name(name() + ".IdleCycles")
  81         .desc("Number of cycles decode is idle")
  82         .prereq(decodeIdleCycles);
  83     decodeBlockedCycles
  84         .name(name() + ".BlockedCycles")
  85         .desc("Number of cycles decode is blocked")
  86         .prereq(decodeBlockedCycles);
  87     decodeRunCycles
  88         .name(name() + ".RunCycles")
  89         .desc("Number of cycles decode is running")
  90         .prereq(decodeRunCycles);
  91     decodeUnblockCycles
  92         .name(name() + ".UnblockCycles")
  93         .desc("Number of cycles decode is unblocking")
  94         .prereq(decodeUnblockCycles);
  95     decodeSquashCycles
  96         .name(name() + ".SquashCycles")
  97         .desc("Number of cycles decode is squashing")
  98         .prereq(decodeSquashCycles);
  99     decodeBranchResolved
 100         .name(name() + ".BranchResolved")
 101         .desc("Number of times decode resolved a branch")
 102         .prereq(decodeBranchResolved);
 103     decodeBranchMispred
 104         .name(name() + ".BranchMispred")
 105         .desc("Number of times decode detected a branch misprediction")
 106         .prereq(decodeBranchMispred);
 107     decodeControlMispred
 108         .name(name() + ".ControlMispred")
 109         .desc("Number of times decode detected an instruction incorrectly"
 110               " predicted as a control")
 111         .prereq(decodeControlMispred);
 112     decodeDecodedInsts
 113         .name(name() + ".DecodedInsts")
 114         .desc("Number of instructions handled by decode")
 115         .prereq(decodeDecodedInsts);
 116     decodeSquashedInsts
 117         .name(name() + ".SquashedInsts")
 118         .desc("Number of squashed instructions handled by decode")
 119         .prereq(decodeSquashedInsts);
 120 }
 121
 122 template<class Impl>
 123 void
 124 DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 125 {
 126     timeBuffer = tb_ptr;
 127
 128     // Setup wire to write information back to fetch.
 129     toFetch = timeBuffer->getWire(0);
 130
 131     // Create wires to get information from proper places in time buffer.
 132     fromRename = timeBuffer->getWire(-renameToDecodeDelay);
 133     fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
 134     fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
 135 }
 136
 137 template<class Impl>
 138 void
 139 DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
 140 {
 141     decodeQueue = dq_ptr;
 142
 143     // Setup wire to write information to proper place in decode queue.
 144     toRename = decodeQueue->getWire(0);
 145 }
 146
 147 template<class Impl>
 148 void
 149 DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
 150 {
 151     fetchQueue = fq_ptr;
 152
 153     // Setup wire to read information from fetch queue.
 154     fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
 155 }
 156
 157 template<class Impl>
 158 void
 159 DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
 160 {
 161     activeThreads = at_ptr;
 162 }
 163
 164 template <class Impl>
 165 bool
 166 DefaultDecode<Impl>::drain()
 167 {
 168     // Decode is done draining at any time.
 169     cpu->signalDrained();
 170     return true;
 171 }
 172
 173 template <class Impl>
 174 void
 175 DefaultDecode<Impl>::takeOverFrom()
 176 {
 177     _status = Inactive;
 178
 179     // Be sure to reset state and clear out any old instructions.
 180     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 181         decodeStatus[tid] = Idle;
 182
 183         stalls[tid].rename = false;
 184         stalls[tid].iew = false;
 185         stalls[tid].commit = false;
 186         while (!insts[tid].empty())
 187             insts[tid].pop();
 188         while (!skidBuffer[tid].empty())
 189             skidBuffer[tid].pop();
 190         branchCount[tid] = 0;
 191     }
 192     wroteToTimeBuffer = false;
 193 }
 194
 195 template<class Impl>
 196 bool
 197 DefaultDecode<Impl>::checkStall(ThreadID tid) const
 198 {
 199     bool ret_val = false;
 200
 201     if (stalls[tid].rename) {
 202         DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
 203         ret_val = true;
 204     } else if (stalls[tid].iew) {
 205         DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
 206         ret_val = true;
 207     } else if (stalls[tid].commit) {
 208         DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
 209         ret_val = true;
 210     }
 211
 212     return ret_val;
 213 }
 214
 215 template<class Impl>
 216 inline bool
 217 DefaultDecode<Impl>::fetchInstsValid()
 218 {
 219     return fromFetch->size > 0;
 220 }
 221
 222 template<class Impl>
 223 bool
 224 DefaultDecode<Impl>::block(ThreadID tid)
 225 {
 226     DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
 227
 228     // Add the current inputs to the skid buffer so they can be
 229     // reprocessed when this stage unblocks.
 230     skidInsert(tid);
 231
 232     // If the decode status is blocked or unblocking then decode has not yet
 233     // signalled fetch to unblock. In that case, there is no need to tell
 234     // fetch to block.
 235     if (decodeStatus[tid] != Blocked) {
 236         // Set the status to Blocked.
 237         decodeStatus[tid] = Blocked;
 238
 239         if (decodeStatus[tid] != Unblocking) {
 240             toFetch->decodeBlock[tid] = true;
 241             wroteToTimeBuffer = true;
 242         }
 243
 244         return true;
 245     }
 246
 247     return false;
 248 }
 249
 250 template<class Impl>
 251 bool
 252 DefaultDecode<Impl>::unblock(ThreadID tid)
 253 {
 254     // Decode is done unblocking only if the skid buffer is empty.
 255     if (skidBuffer[tid].empty()) {
 256         DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
 257         toFetch->decodeUnblock[tid] = true;
 258         wroteToTimeBuffer = true;
 259
 260         decodeStatus[tid] = Running;
 261         return true;
 262     }
 263
 264     DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
 265
 266     return false;
 267 }
 268
 269 template<class Impl>
 270 void
 271 DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
 272 {
 273     DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch "
 274             "prediction detected at decode.\n", tid, inst->seqNum);
 275
 276     // Send back mispredict information.
 277     toFetch->decodeInfo[tid].branchMispredict = true;
 278     toFetch->decodeInfo[tid].predIncorrect = true;
 279     toFetch->decodeInfo[tid].squash = true;
 280     toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
 281     toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
 282     toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
 283     toFetch->decodeInfo[tid].squashInst = inst;
 284
 285     InstSeqNum squash_seq_num = inst->seqNum;
 286
 287     // Might have to tell fetch to unblock.
 288     if (decodeStatus[tid] == Blocked ||
 289         decodeStatus[tid] == Unblocking) {
 290         toFetch->decodeUnblock[tid] = 1;
 291     }
 292
 293     // Set status to squashing.
 294     decodeStatus[tid] = Squashing;
 295
 296     for (int i=0; i<fromFetch->size; i++) {
 297         if (fromFetch->insts[i]->threadNumber == tid &&
 298             fromFetch->insts[i]->seqNum > squash_seq_num) {
 299             fromFetch->insts[i]->setSquashed();
 300         }
 301     }
 302
 303     // Clear the instruction list and skid buffer in case they have any
 304     // insts in them.
 305     while (!insts[tid].empty()) {
 306         insts[tid].pop();
 307     }
 308
 309     while (!skidBuffer[tid].empty()) {
 310         skidBuffer[tid].pop();
 311     }
 312
 313     // Squash instructions up until this one
 314     cpu->removeInstsUntil(squash_seq_num, tid);
 315 }
 316
 317 template<class Impl>
 318 unsigned
 319 DefaultDecode<Impl>::squash(ThreadID tid)
 320 {
 321     DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
 322
 323     if (decodeStatus[tid] == Blocked ||
 324         decodeStatus[tid] == Unblocking) {
 325         if (FullSystem) {
 326             toFetch->decodeUnblock[tid] = 1;
 327         } else {
 328             // In syscall emulation, we can have both a block and a squash due
 329             // to a syscall in the same cycle.  This would cause both signals
 330             // to be high.  This shouldn't happen in full system.
 331             // @todo: Determine if this still happens.
 332             if (toFetch->decodeBlock[tid])
 333                 toFetch->decodeBlock[tid] = 0;
 334             else
 335                 toFetch->decodeUnblock[tid] = 1;
 336         }
 337     }
 338
 339     // Set status to squashing.
 340     decodeStatus[tid] = Squashing;
 341
 342     // Go through incoming instructions from fetch and squash them.
 343     unsigned squash_count = 0;
 344
 345     for (int i=0; i<fromFetch->size; i++) {
 346         if (fromFetch->insts[i]->threadNumber == tid) {
 347             fromFetch->insts[i]->setSquashed();
 348             squash_count++;
 349         }
 350     }
 351
 352     // Clear the instruction list and skid buffer in case they have any
 353     // insts in them.
 354     while (!insts[tid].empty()) {
 355         insts[tid].pop();
 356     }
 357
 358     while (!skidBuffer[tid].empty()) {
 359         skidBuffer[tid].pop();
 360     }
 361
 362     return squash_count;
 363 }
 364
 365 template<class Impl>
 366 void
 367 DefaultDecode<Impl>::skidInsert(ThreadID tid)
 368 {
 369     DynInstPtr inst = NULL;
 370
 371     while (!insts[tid].empty()) {
 372         inst = insts[tid].front();
 373
 374         insts[tid].pop();
 375
 376         assert(tid == inst->threadNumber);
 377
 378         DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n",
 379                 inst->seqNum, inst->pcState(), inst->threadNumber);
 380
 381         skidBuffer[tid].push(inst);
 382     }
 383
 384     // @todo: Eventually need to enforce this by not letting a thread
 385     // fetch past its skidbuffer
 386     assert(skidBuffer[tid].size() <= skidBufferMax);
 387 }
 388
 389 template<class Impl>
 390 bool
 391 DefaultDecode<Impl>::skidsEmpty()
 392 {
 393     list<ThreadID>::iterator threads = activeThreads->begin();
 394     list<ThreadID>::iterator end = activeThreads->end();
 395
 396     while (threads != end) {
 397         ThreadID tid = *threads++;
 398         if (!skidBuffer[tid].empty())
 399             return false;
 400     }
 401
 402     return true;
 403 }
 404
 405 template<class Impl>
 406 void
 407 DefaultDecode<Impl>::updateStatus()
 408 {
 409     bool any_unblocking = false;
 410
 411     list<ThreadID>::iterator threads = activeThreads->begin();
 412     list<ThreadID>::iterator end = activeThreads->end();
 413
 414     while (threads != end) {
 415         ThreadID tid = *threads++;
 416
 417         if (decodeStatus[tid] == Unblocking) {
 418             any_unblocking = true;
 419             break;
 420         }
 421     }
 422
 423     // Decode will have activity if it's unblocking.
 424     if (any_unblocking) {
 425         if (_status == Inactive) {
 426             _status = Active;
 427
 428             DPRINTF(Activity, "Activating stage.\n");
 429
 430             cpu->activateStage(O3CPU::DecodeIdx);
 431         }
 432     } else {
 433         // If it's not unblocking, then decode will not have any internal
 434         // activity.  Switch it to inactive.
 435         if (_status == Active) {
 436             _status = Inactive;
 437             DPRINTF(Activity, "Deactivating stage.\n");
 438
 439             cpu->deactivateStage(O3CPU::DecodeIdx);
 440         }
 441     }
 442 }
 443
 444 template <class Impl>
 445 void
 446 DefaultDecode<Impl>::sortInsts()
 447 {
 448     int insts_from_fetch = fromFetch->size;
 449     for (int i = 0; i < insts_from_fetch; ++i) {
 450         insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
 451     }
 452 }
 453
 454 template<class Impl>
 455 void
 456 DefaultDecode<Impl>::readStallSignals(ThreadID tid)
 457 {
 458     if (fromRename->renameBlock[tid]) {
 459         stalls[tid].rename = true;
 460     }
 461
 462     if (fromRename->renameUnblock[tid]) {
 463         assert(stalls[tid].rename);
 464         stalls[tid].rename = false;
 465     }
 466
 467     if (fromIEW->iewBlock[tid]) {
 468         stalls[tid].iew = true;
 469     }
 470
 471     if (fromIEW->iewUnblock[tid]) {
 472         assert(stalls[tid].iew);
 473         stalls[tid].iew = false;
 474     }
 475
 476     if (fromCommit->commitBlock[tid]) {
 477         stalls[tid].commit = true;
 478     }
 479
 480     if (fromCommit->commitUnblock[tid]) {
 481         assert(stalls[tid].commit);
 482         stalls[tid].commit = false;
 483     }
 484 }
 485
 486 template <class Impl>
 487 bool
 488 DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid)
 489 {
 490     // Check if there's a squash signal, squash if there is.
 491     // Check stall signals, block if necessary.
 492     // If status was blocked
 493     //     Check if stall conditions have passed
 494     //         if so then go to unblocking
 495     // If status was Squashing
 496     //     check if squashing is not high.  Switch to running this cycle.
 497
 498     // Update the per thread stall statuses.
 499     readStallSignals(tid);
 500
 501     // Check squash signals from commit.
 502     if (fromCommit->commitInfo[tid].squash) {
 503
 504         DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
 505                 "from commit.\n", tid);
 506
 507         squash(tid);
 508
 509         return true;
 510     }
 511
 512     // Check ROB squash signals from commit.
 513     if (fromCommit->commitInfo[tid].robSquashing) {
 514         DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
 515
 516         // Continue to squash.
 517         decodeStatus[tid] = Squashing;
 518
 519         return true;
 520     }
 521
 522     if (checkStall(tid)) {
 523         return block(tid);
 524     }
 525
 526     if (decodeStatus[tid] == Blocked) {
 527         DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
 528                 tid);
 529
 530         decodeStatus[tid] = Unblocking;
 531
 532         unblock(tid);
 533
 534         return true;
 535     }
 536
 537     if (decodeStatus[tid] == Squashing) {
 538         // Switch status to running if decode isn't being told to block or
 539         // squash this cycle.
 540         DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
 541                 tid);
 542
 543         decodeStatus[tid] = Running;
 544
 545         return false;
 546     }
 547
 548     // If we've reached this point, we have not gotten any signals that
 549     // cause decode to change its status.  Decode remains the same as before.
 550     return false;
 551 }
 552
 553 template<class Impl>
 554 void
 555 DefaultDecode<Impl>::tick()
 556 {
 557     wroteToTimeBuffer = false;
 558
 559     bool status_change = false;
 560
 561     toRenameIndex = 0;
 562
 563     list<ThreadID>::iterator threads = activeThreads->begin();
 564     list<ThreadID>::iterator end = activeThreads->end();
 565
 566     sortInsts();
 567
 568     //Check stall and squash signals.
 569     while (threads != end) {
 570         ThreadID tid = *threads++;
 571
 572         DPRINTF(Decode,"Processing [tid:%i]\n",tid);
 573         status_change =  checkSignalsAndUpdate(tid) || status_change;
 574
 575         decode(status_change, tid);
 576     }
 577
 578     if (status_change) {
 579         updateStatus();
 580     }
 581
 582     if (wroteToTimeBuffer) {
 583         DPRINTF(Activity, "Activity this cycle.\n");
 584
 585         cpu->activityThisCycle();
 586     }
 587 }
 588
 589 template<class Impl>
 590 void
 591 DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid)
 592 {
 593     // If status is Running or idle,
 594     //     call decodeInsts()
 595     // If status is Unblocking,
 596     //     buffer any instructions coming from fetch
 597     //     continue trying to empty skid buffer
 598     //     check if stall conditions have passed
 599
 600     if (decodeStatus[tid] == Blocked) {
 601         ++decodeBlockedCycles;
 602     } else if (decodeStatus[tid] == Squashing) {
 603         ++decodeSquashCycles;
 604     }
 605
 606     // Decode should try to decode as many instructions as its bandwidth
 607     // will allow, as long as it is not currently blocked.
 608     if (decodeStatus[tid] == Running ||
 609         decodeStatus[tid] == Idle) {
 610         DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run "
 611                 "stage.\n",tid);
 612
 613         decodeInsts(tid);
 614     } else if (decodeStatus[tid] == Unblocking) {
 615         // Make sure that the skid buffer has something in it if the
 616         // status is unblocking.
 617         assert(!skidsEmpty());
 618
 619         // If the status was unblocking, then instructions from the skid
 620         // buffer were used.  Remove those instructions and handle
 621         // the rest of unblocking.
 622         decodeInsts(tid);
 623
 624         if (fetchInstsValid()) {
 625             // Add the current inputs to the skid buffer so they can be
 626             // reprocessed when this stage unblocks.
 627             skidInsert(tid);
 628         }
 629
 630         status_change = unblock(tid) || status_change;
 631     }
 632 }
 633
 634 template <class Impl>
 635 void
 636 DefaultDecode<Impl>::decodeInsts(ThreadID tid)
 637 {
 638     // Instructions can come either from the skid buffer or the list of
 639     // instructions coming from fetch, depending on decode's status.
 640     int insts_available = decodeStatus[tid] == Unblocking ?
 641         skidBuffer[tid].size() : insts[tid].size();
 642
 643     if (insts_available == 0) {
 644         DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
 645                 " early.\n",tid);
 646         // Should I change the status to idle?
 647         ++decodeIdleCycles;
 648         return;
 649     } else if (decodeStatus[tid] == Unblocking) {
 650         DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
 651                 "buffer.\n",tid);
 652         ++decodeUnblockCycles;
 653     } else if (decodeStatus[tid] == Running) {
 654         ++decodeRunCycles;
 655     }
 656
 657     DynInstPtr inst;
 658
 659     std::queue<DynInstPtr>
 660         &insts_to_decode = decodeStatus[tid] == Unblocking ?
 661         skidBuffer[tid] : insts[tid];
 662
 663     DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
 664
 665     while (insts_available > 0 && toRenameIndex < decodeWidth) {
 666         assert(!insts_to_decode.empty());
 667
 668         inst = insts_to_decode.front();
 669
 670         insts_to_decode.pop();
 671
 672         DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
 673                 "PC %s\n", tid, inst->seqNum, inst->pcState());
 674
 675         if (inst->isSquashed()) {
 676             DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is "
 677                     "squashed, skipping.\n",
 678                     tid, inst->seqNum, inst->pcState());
 679
 680             ++decodeSquashedInsts;
 681
 682             --insts_available;
 683
 684             continue;
 685         }
 686
 687         // Also check if instructions have no source registers.  Mark
 688         // them as ready to issue at any time.  Not sure if this check
 689         // should exist here or at a later stage; however it doesn't matter
 690         // too much for function correctness.
 691         if (inst->numSrcRegs() == 0) {
 692             inst->setCanIssue();
 693         }
 694
 695         // This current instruction is valid, so add it into the decode
 696         // queue.  The next instruction may not be valid, so check to
 697         // see if branches were predicted correctly.
 698         toRename->insts[toRenameIndex] = inst;
 699
 700         ++(toRename->size);
 701         ++toRenameIndex;
 702         ++decodeDecodedInsts;
 703         --insts_available;
 704
 705 #if TRACING_ON
 706         inst->decodeTick = curTick();
 707 #endif
 708
 709         // Ensure that if it was predicted as a branch, it really is a
 710         // branch.
 711         if (inst->readPredTaken() && !inst->isControl()) {
 712             panic("Instruction predicted as a branch!");
 713
 714             ++decodeControlMispred;
 715
 716             // Might want to set some sort of boolean and just do
 717             // a check at the end
 718             squash(inst, inst->threadNumber);
 719
 720             break;
 721         }
 722
 723         // Go ahead and compute any PC-relative branches.
 724         if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
 725             ++decodeBranchResolved;
 726
 727             if (!(inst->branchTarget() == inst->readPredTarg())) {
 728                 ++decodeBranchMispred;
 729
 730                 // Might want to set some sort of boolean and just do
 731                 // a check at the end
 732                 squash(inst, inst->threadNumber);
 733                 TheISA::PCState target = inst->branchTarget();
 734
 735                 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n",
 736                         inst->seqNum, target);
 737                 //The micro pc after an instruction level branch should be 0
 738                 inst->setPredTarg(target);
 739                 break;
 740             }
 741         }
 742     }
 743
 744     // If we didn't process all instructions, then we will need to block
 745     // and put all those instructions into the skid buffer.
 746     if (!insts_to_decode.empty()) {
 747         block(tid);
 748     }
 749
 750     // Record that decode has written to the time buffer for activity
 751     // tracking.
 752     if (toRenameIndex) {
 753         wroteToTimeBuffer = true;
 754     }
 755 }