2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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31 #include "cpu/o3/decode.hh"
36 DefaultDecode<Impl>::DefaultDecode(Params *params)
37 : renameToDecodeDelay(params->renameToDecodeDelay),
38 iewToDecodeDelay(params->iewToDecodeDelay),
39 commitToDecodeDelay(params->commitToDecodeDelay),
40 fetchToDecodeDelay(params->fetchToDecodeDelay),
41 decodeWidth(params->decodeWidth),
42 numThreads(params->numberOfThreads)
46 // Setup status, make sure stall signals are clear.
47 for (int i = 0; i < numThreads; ++i) {
48 decodeStatus[i] = Idle;
50 stalls[i].rename = false;
51 stalls[i].iew = false;
52 stalls[i].commit = false;
55 // @todo: Make into a parameter
56 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth;
61 DefaultDecode<Impl>::name() const
63 return cpu->name() + ".decode";
68 DefaultDecode<Impl>::regStats()
71 .name(name() + ".DECODE:IdleCycles")
72 .desc("Number of cycles decode is idle")
73 .prereq(decodeIdleCycles);
75 .name(name() + ".DECODE:BlockedCycles")
76 .desc("Number of cycles decode is blocked")
77 .prereq(decodeBlockedCycles);
79 .name(name() + ".DECODE:RunCycles")
80 .desc("Number of cycles decode is running")
81 .prereq(decodeRunCycles);
83 .name(name() + ".DECODE:UnblockCycles")
84 .desc("Number of cycles decode is unblocking")
85 .prereq(decodeUnblockCycles);
87 .name(name() + ".DECODE:SquashCycles")
88 .desc("Number of cycles decode is squashing")
89 .prereq(decodeSquashCycles);
91 .name(name() + ".DECODE:BranchResolved")
92 .desc("Number of times decode resolved a branch")
93 .prereq(decodeBranchResolved);
95 .name(name() + ".DECODE:BranchMispred")
96 .desc("Number of times decode detected a branch misprediction")
97 .prereq(decodeBranchMispred);
99 .name(name() + ".DECODE:ControlMispred")
100 .desc("Number of times decode detected an instruction incorrectly"
101 " predicted as a control")
102 .prereq(decodeControlMispred);
104 .name(name() + ".DECODE:DecodedInsts")
105 .desc("Number of instructions handled by decode")
106 .prereq(decodeDecodedInsts);
108 .name(name() + ".DECODE:SquashedInsts")
109 .desc("Number of squashed instructions handled by decode")
110 .prereq(decodeSquashedInsts);
115 DefaultDecode<Impl>::setCPU(FullCPU *cpu_ptr)
117 DPRINTF(Decode, "Setting CPU pointer.\n");
123 DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
125 DPRINTF(Decode, "Setting time buffer pointer.\n");
128 // Setup wire to write information back to fetch.
129 toFetch = timeBuffer->getWire(0);
131 // Create wires to get information from proper places in time buffer.
132 fromRename = timeBuffer->getWire(-renameToDecodeDelay);
133 fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
134 fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
139 DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
141 DPRINTF(Decode, "Setting decode queue pointer.\n");
142 decodeQueue = dq_ptr;
144 // Setup wire to write information to proper place in decode queue.
145 toRename = decodeQueue->getWire(0);
150 DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
152 DPRINTF(Decode, "Setting fetch queue pointer.\n");
155 // Setup wire to read information from fetch queue.
156 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
161 DefaultDecode<Impl>::setActiveThreads(list<unsigned> *at_ptr)
163 DPRINTF(Decode, "Setting active threads list pointer.\n");
164 activeThreads = at_ptr;
167 template <class Impl>
169 DefaultDecode<Impl>::switchOut()
171 // Decode can immediately switch out.
172 cpu->signalSwitched();
175 template <class Impl>
177 DefaultDecode<Impl>::takeOverFrom()
181 // Be sure to reset state and clear out any old instructions.
182 for (int i = 0; i < numThreads; ++i) {
183 decodeStatus[i] = Idle;
185 stalls[i].rename = false;
186 stalls[i].iew = false;
187 stalls[i].commit = false;
188 while (!insts[i].empty())
190 while (!skidBuffer[i].empty())
194 wroteToTimeBuffer = false;
199 DefaultDecode<Impl>::checkStall(unsigned tid) const
201 bool ret_val = false;
203 if (stalls[tid].rename) {
204 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
206 } else if (stalls[tid].iew) {
207 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
209 } else if (stalls[tid].commit) {
210 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
219 DefaultDecode<Impl>::fetchInstsValid()
221 return fromFetch->size > 0;
226 DefaultDecode<Impl>::block(unsigned tid)
228 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
230 // Add the current inputs to the skid buffer so they can be
231 // reprocessed when this stage unblocks.
234 // If the decode status is blocked or unblocking then decode has not yet
235 // signalled fetch to unblock. In that case, there is no need to tell
237 if (decodeStatus[tid] != Blocked) {
238 // Set the status to Blocked.
239 decodeStatus[tid] = Blocked;
241 if (decodeStatus[tid] != Unblocking) {
242 toFetch->decodeBlock[tid] = true;
243 wroteToTimeBuffer = true;
254 DefaultDecode<Impl>::unblock(unsigned tid)
256 // Decode is done unblocking only if the skid buffer is empty.
257 if (skidBuffer[tid].empty()) {
258 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
259 toFetch->decodeUnblock[tid] = true;
260 wroteToTimeBuffer = true;
262 decodeStatus[tid] = Running;
266 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
273 DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
275 DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction "
276 "detected at decode.\n", tid);
278 // Send back mispredict information.
279 toFetch->decodeInfo[tid].branchMispredict = true;
280 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
281 toFetch->decodeInfo[tid].predIncorrect = true;
282 toFetch->decodeInfo[tid].squash = true;
283 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
284 toFetch->decodeInfo[tid].branchTaken =
285 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
287 // Might have to tell fetch to unblock.
288 if (decodeStatus[tid] == Blocked ||
289 decodeStatus[tid] == Unblocking) {
290 toFetch->decodeUnblock[tid] = 1;
293 // Set status to squashing.
294 decodeStatus[tid] = Squashing;
296 for (int i=0; i<fromFetch->size; i++) {
297 if (fromFetch->insts[i]->threadNumber == tid &&
298 fromFetch->insts[i]->seqNum > inst->seqNum) {
299 fromFetch->insts[i]->setSquashed();
303 // Clear the instruction list and skid buffer in case they have any
305 while (!insts[tid].empty()) {
309 while (!skidBuffer[tid].empty()) {
310 skidBuffer[tid].pop();
313 // Squash instructions up until this one
314 cpu->removeInstsUntil(inst->seqNum, tid);
319 DefaultDecode<Impl>::squash(unsigned tid)
321 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
323 if (decodeStatus[tid] == Blocked ||
324 decodeStatus[tid] == Unblocking) {
326 // In syscall emulation, we can have both a block and a squash due
327 // to a syscall in the same cycle. This would cause both signals to
328 // be high. This shouldn't happen in full system.
329 // @todo: Determine if this still happens.
330 if (toFetch->decodeBlock[tid]) {
331 toFetch->decodeBlock[tid] = 0;
333 toFetch->decodeUnblock[tid] = 1;
336 toFetch->decodeUnblock[tid] = 1;
340 // Set status to squashing.
341 decodeStatus[tid] = Squashing;
343 // Go through incoming instructions from fetch and squash them.
344 unsigned squash_count = 0;
346 for (int i=0; i<fromFetch->size; i++) {
347 if (fromFetch->insts[i]->threadNumber == tid) {
348 fromFetch->insts[i]->setSquashed();
353 // Clear the instruction list and skid buffer in case they have any
355 while (!insts[tid].empty()) {
359 while (!skidBuffer[tid].empty()) {
360 skidBuffer[tid].pop();
368 DefaultDecode<Impl>::skidInsert(unsigned tid)
370 DynInstPtr inst = NULL;
372 while (!insts[tid].empty()) {
373 inst = insts[tid].front();
377 assert(tid == inst->threadNumber);
379 DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n",
380 inst->seqNum, inst->readPC(), inst->threadNumber);
382 skidBuffer[tid].push(inst);
385 // @todo: Eventually need to enforce this by not letting a thread
386 // fetch past its skidbuffer
387 assert(skidBuffer[tid].size() <= skidBufferMax);
392 DefaultDecode<Impl>::skidsEmpty()
394 list<unsigned>::iterator threads = (*activeThreads).begin();
396 while (threads != (*activeThreads).end()) {
397 if (!skidBuffer[*threads++].empty())
406 DefaultDecode<Impl>::updateStatus()
408 bool any_unblocking = false;
410 list<unsigned>::iterator threads = (*activeThreads).begin();
412 threads = (*activeThreads).begin();
414 while (threads != (*activeThreads).end()) {
415 unsigned tid = *threads++;
417 if (decodeStatus[tid] == Unblocking) {
418 any_unblocking = true;
423 // Decode will have activity if it's unblocking.
424 if (any_unblocking) {
425 if (_status == Inactive) {
428 DPRINTF(Activity, "Activating stage.\n");
430 cpu->activateStage(FullCPU::DecodeIdx);
433 // If it's not unblocking, then decode will not have any internal
434 // activity. Switch it to inactive.
435 if (_status == Active) {
437 DPRINTF(Activity, "Deactivating stage.\n");
439 cpu->deactivateStage(FullCPU::DecodeIdx);
444 template <class Impl>
446 DefaultDecode<Impl>::sortInsts()
448 int insts_from_fetch = fromFetch->size;
450 for (int i=0; i < numThreads; i++)
451 assert(insts[i].empty());
453 for (int i = 0; i < insts_from_fetch; ++i) {
454 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
460 DefaultDecode<Impl>::readStallSignals(unsigned tid)
462 if (fromRename->renameBlock[tid]) {
463 stalls[tid].rename = true;
466 if (fromRename->renameUnblock[tid]) {
467 assert(stalls[tid].rename);
468 stalls[tid].rename = false;
471 if (fromIEW->iewBlock[tid]) {
472 stalls[tid].iew = true;
475 if (fromIEW->iewUnblock[tid]) {
476 assert(stalls[tid].iew);
477 stalls[tid].iew = false;
480 if (fromCommit->commitBlock[tid]) {
481 stalls[tid].commit = true;
484 if (fromCommit->commitUnblock[tid]) {
485 assert(stalls[tid].commit);
486 stalls[tid].commit = false;
490 template <class Impl>
492 DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid)
494 // Check if there's a squash signal, squash if there is.
495 // Check stall signals, block if necessary.
496 // If status was blocked
497 // Check if stall conditions have passed
498 // if so then go to unblocking
499 // If status was Squashing
500 // check if squashing is not high. Switch to running this cycle.
502 // Update the per thread stall statuses.
503 readStallSignals(tid);
505 // Check squash signals from commit.
506 if (fromCommit->commitInfo[tid].squash) {
508 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
509 "from commit.\n", tid);
516 // Check ROB squash signals from commit.
517 if (fromCommit->commitInfo[tid].robSquashing) {
518 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
520 // Continue to squash.
521 decodeStatus[tid] = Squashing;
526 if (checkStall(tid)) {
530 if (decodeStatus[tid] == Blocked) {
531 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
534 decodeStatus[tid] = Unblocking;
541 if (decodeStatus[tid] == Squashing) {
542 // Switch status to running if decode isn't being told to block or
543 // squash this cycle.
544 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
547 decodeStatus[tid] = Running;
552 // If we've reached this point, we have not gotten any signals that
553 // cause decode to change its status. Decode remains the same as before.
559 DefaultDecode<Impl>::tick()
561 wroteToTimeBuffer = false;
563 bool status_change = false;
567 list<unsigned>::iterator threads = (*activeThreads).begin();
571 //Check stall and squash signals.
572 while (threads != (*activeThreads).end()) {
573 unsigned tid = *threads++;
575 DPRINTF(Decode,"Processing [tid:%i]\n",tid);
576 status_change = checkSignalsAndUpdate(tid) || status_change;
578 decode(status_change, tid);
585 if (wroteToTimeBuffer) {
586 DPRINTF(Activity, "Activity this cycle.\n");
588 cpu->activityThisCycle();
594 DefaultDecode<Impl>::decode(bool &status_change, unsigned tid)
596 // If status is Running or idle,
597 // call decodeInsts()
598 // If status is Unblocking,
599 // buffer any instructions coming from fetch
600 // continue trying to empty skid buffer
601 // check if stall conditions have passed
603 if (decodeStatus[tid] == Blocked) {
604 ++decodeBlockedCycles;
605 } else if (decodeStatus[tid] == Squashing) {
606 ++decodeSquashCycles;
609 // Decode should try to decode as many instructions as its bandwidth
610 // will allow, as long as it is not currently blocked.
611 if (decodeStatus[tid] == Running ||
612 decodeStatus[tid] == Idle) {
613 DPRINTF(Decode, "[tid:%u] Not blocked, so attempting to run "
617 } else if (decodeStatus[tid] == Unblocking) {
618 // Make sure that the skid buffer has something in it if the
619 // status is unblocking.
620 assert(!skidsEmpty());
622 // If the status was unblocking, then instructions from the skid
623 // buffer were used. Remove those instructions and handle
624 // the rest of unblocking.
627 if (fetchInstsValid()) {
628 // Add the current inputs to the skid buffer so they can be
629 // reprocessed when this stage unblocks.
633 status_change = unblock(tid) || status_change;
637 template <class Impl>
639 DefaultDecode<Impl>::decodeInsts(unsigned tid)
641 // Instructions can come either from the skid buffer or the list of
642 // instructions coming from fetch, depending on decode's status.
643 int insts_available = decodeStatus[tid] == Unblocking ?
644 skidBuffer[tid].size() : insts[tid].size();
646 if (insts_available == 0) {
647 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
649 // Should I change the status to idle?
652 } else if (decodeStatus[tid] == Unblocking) {
653 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
655 ++decodeUnblockCycles;
656 } else if (decodeStatus[tid] == Running) {
662 std::queue<DynInstPtr>
663 &insts_to_decode = decodeStatus[tid] == Unblocking ?
664 skidBuffer[tid] : insts[tid];
666 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
668 while (insts_available > 0 && toRenameIndex < decodeWidth) {
669 assert(!insts_to_decode.empty());
671 inst = insts_to_decode.front();
673 insts_to_decode.pop();
675 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
677 tid, inst->seqNum, inst->readPC());
679 if (inst->isSquashed()) {
680 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is "
681 "squashed, skipping.\n",
682 tid, inst->seqNum, inst->readPC());
684 ++decodeSquashedInsts;
691 // Also check if instructions have no source registers. Mark
692 // them as ready to issue at any time. Not sure if this check
693 // should exist here or at a later stage; however it doesn't matter
694 // too much for function correctness.
695 if (inst->numSrcRegs() == 0) {
699 // This current instruction is valid, so add it into the decode
700 // queue. The next instruction may not be valid, so check to
701 // see if branches were predicted correctly.
702 toRename->insts[toRenameIndex] = inst;
706 ++decodeDecodedInsts;
709 // Ensure that if it was predicted as a branch, it really is a
711 if (inst->predTaken() && !inst->isControl()) {
712 panic("Instruction predicted as a branch!");
714 ++decodeControlMispred;
716 // Might want to set some sort of boolean and just do
717 // a check at the end
718 squash(inst, inst->threadNumber);
723 // Go ahead and compute any PC-relative branches.
724 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
725 ++decodeBranchResolved;
727 if (inst->branchTarget() != inst->readPredTarg()) {
728 ++decodeBranchMispred;
730 // Might want to set some sort of boolean and just do
731 // a check at the end
732 squash(inst, inst->threadNumber);
733 inst->setPredTarg(inst->branchTarget());
740 // If we didn't process all instructions, then we will need to block
741 // and put all those instructions into the skid buffer.
742 if (!insts_to_decode.empty()) {
746 // Record that decode has written to the time buffer for activity
749 wroteToTimeBuffer = true;