src/cpu/o3/dyn_inst.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_O3_DYN_INST_HH__
  32 #define __CPU_O3_DYN_INST_HH__
  33
  34 #include "arch/isa_traits.hh"
  35 #include "cpu/base_dyn_inst.hh"
  36 #include "cpu/inst_seq.hh"
  37 #include "cpu/o3/cpu.hh"
  38 #include "cpu/o3/isa_specific.hh"
  39
  40 class Packet;
  41
  42 /**
  43  * Mostly implementation & ISA specific AlphaDynInst. As with most
  44  * other classes in the new CPU model, it is templated on the Impl to
  45  * allow for passing in of all types, such as the CPU type and the ISA
  46  * type. The AlphaDynInst serves as the primary interface to the CPU
  47  * for instructions that are executing.
  48  */
  49 template <class Impl>
  50 class BaseO3DynInst : public BaseDynInst<Impl>
  51 {
  52   public:
  53     /** Typedef for the CPU. */
  54     typedef typename Impl::O3CPU O3CPU;
  55
  56     /** Binary machine instruction type. */
  57     typedef TheISA::MachInst MachInst;
  58     /** Extended machine instruction type. */
  59     typedef TheISA::ExtMachInst ExtMachInst;
  60     /** Logical register index type. */
  61     typedef TheISA::RegIndex RegIndex;
  62     /** Integer register index type. */
  63     typedef TheISA::IntReg   IntReg;
  64     typedef TheISA::FloatReg FloatReg;
  65     typedef TheISA::FloatRegBits FloatRegBits;
  66     /** Misc register index type. */
  67     typedef TheISA::MiscReg  MiscReg;
  68
  69     enum {
  70         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
  71         MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
  72     };
  73
  74   public:
  75     /** BaseDynInst constructor given a binary instruction. */
  76     BaseO3DynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC,
  77                  Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC,
  78                  InstSeqNum seq_num, O3CPU *cpu);
  79
  80     /** BaseDynInst constructor given a binary instruction. */
  81     BaseO3DynInst(ExtMachInst inst, Addr PC, Addr NPC, Addr microPC,
  82                  Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC,
  83                  InstSeqNum seq_num, O3CPU *cpu);
  84
  85     /** BaseDynInst constructor given a static inst pointer. */
  86     BaseO3DynInst(StaticInstPtr &_staticInst);
  87
  88     /** Executes the instruction.*/
  89     Fault execute();
  90
  91     /** Initiates the access.  Only valid for memory operations. */
  92     Fault initiateAcc();
  93
  94     /** Completes the access.  Only valid for memory operations. */
  95     Fault completeAcc(PacketPtr pkt);
  96
  97   private:
  98     /** Initializes variables. */
  99     void initVars();
 100
 101   public:
 102     /** Reads a miscellaneous register. */
 103     MiscReg readMiscRegNoEffect(int misc_reg)
 104     {
 105         return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber);
 106     }
 107
 108     /** Reads a misc. register, including any side-effects the read
 109      * might have as defined by the architecture.
 110      */
 111     MiscReg readMiscReg(int misc_reg)
 112     {
 113         return this->cpu->readMiscReg(misc_reg, this->threadNumber);
 114     }
 115
 116     /** Sets a misc. register. */
 117     void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 118     {
 119         this->instResult.integer = val;
 120         return this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber);
 121     }
 122
 123     /** Sets a misc. register, including any side-effects the write
 124      * might have as defined by the architecture.
 125      */
 126     void setMiscReg(int misc_reg, const MiscReg &val)
 127     {
 128         return this->cpu->setMiscReg(misc_reg, val,
 129                                                this->threadNumber);
 130     }
 131
 132     /** Reads a miscellaneous register. */
 133     TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
 134     {
 135         return this->cpu->readMiscRegNoEffect(
 136                 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
 137                 this->threadNumber);
 138     }
 139
 140     /** Reads a misc. register, including any side-effects the read
 141      * might have as defined by the architecture.
 142      */
 143     TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
 144     {
 145         return this->cpu->readMiscReg(
 146                 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
 147                 this->threadNumber);
 148     }
 149
 150     /** Sets a misc. register. */
 151     void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val)
 152     {
 153         this->instResult.integer = val;
 154         return this->cpu->setMiscRegNoEffect(
 155                 si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
 156                 val, this->threadNumber);
 157     }
 158
 159     /** Sets a misc. register, including any side-effects the write
 160      * might have as defined by the architecture.
 161      */
 162     void setMiscRegOperand(const StaticInst *si, int idx,
 163                                      const MiscReg &val)
 164     {
 165         return this->cpu->setMiscReg(
 166                 si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
 167                 val, this->threadNumber);
 168     }
 169
 170 #if FULL_SYSTEM
 171     /** Traps to handle specified fault. */
 172     void trap(Fault fault);
 173 #else
 174     /** Calls a syscall. */
 175     void syscall(int64_t callnum);
 176 #endif
 177
 178   public:
 179
 180     // The register accessor methods provide the index of the
 181     // instruction's operand (e.g., 0 or 1), not the architectural
 182     // register index, to simplify the implementation of register
 183     // renaming.  We find the architectural register index by indexing
 184     // into the instruction's own operand index table.  Note that a
 185     // raw pointer to the StaticInst is provided instead of a
 186     // ref-counted StaticInstPtr to redice overhead.  This is fine as
 187     // long as these methods don't copy the pointer into any long-term
 188     // storage (which is pretty hard to imagine they would have reason
 189     // to do).
 190
 191     uint64_t readIntRegOperand(const StaticInst *si, int idx)
 192     {
 193         return this->cpu->readIntReg(this->_srcRegIdx[idx]);
 194     }
 195
 196     FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
 197     {
 198         return this->cpu->readFloatReg(this->_srcRegIdx[idx], width);
 199     }
 200
 201     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
 202     {
 203         return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
 204     }
 205
 206     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
 207                                          int width)
 208     {
 209         return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width);
 210     }
 211
 212     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
 213     {
 214         return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
 215     }
 216
 217     /** @todo: Make results into arrays so they can handle multiple dest
 218      *  registers.
 219      */
 220     void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
 221     {
 222         this->cpu->setIntReg(this->_destRegIdx[idx], val);
 223         BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
 224     }
 225
 226     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
 227                             int width)
 228     {
 229         this->cpu->setFloatReg(this->_destRegIdx[idx], val, width);
 230         BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
 231     }
 232
 233     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
 234     {
 235         this->cpu->setFloatReg(this->_destRegIdx[idx], val);
 236         BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
 237     }
 238
 239     void setFloatRegOperandBits(const StaticInst *si, int idx,
 240                                 FloatRegBits val, int width)
 241     {
 242         this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width);
 243         BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
 244     }
 245
 246     void setFloatRegOperandBits(const StaticInst *si, int idx,
 247                                 FloatRegBits val)
 248     {
 249         this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
 250         BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
 251     }
 252
 253 #if THE_ISA == MIPS_ISA
 254     uint64_t readRegOtherThread(int misc_reg)
 255     {
 256         panic("MIPS MT not defined for O3 CPU.\n");
 257         return 0;
 258     }
 259
 260     void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
 261     {
 262         panic("MIPS MT not defined for O3 CPU.\n");
 263     }
 264 #endif
 265
 266   public:
 267     /** Calculates EA part of a memory instruction. Currently unused,
 268      * though it may be useful in the future if we want to split
 269      * memory operations into EA calculation and memory access parts.
 270      */
 271     Fault calcEA()
 272     {
 273         return this->staticInst->eaCompInst()->execute(this, this->traceData);
 274     }
 275
 276     /** Does the memory access part of a memory instruction. Currently unused,
 277      * though it may be useful in the future if we want to split
 278      * memory operations into EA calculation and memory access parts.
 279      */
 280     Fault memAccess()
 281     {
 282         return this->staticInst->memAccInst()->execute(this, this->traceData);
 283     }
 284 };
 285
 286 #endif // __CPU_O3_ALPHA_DYN_INST_HH__
 287