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43 #ifndef __CPU_O3_DYN_INST_HH__
44 #define __CPU_O3_DYN_INST_HH__
46 #include "arch/isa_traits.hh"
47 #include "config/the_isa.hh"
48 #include "cpu/o3/cpu.hh"
49 #include "cpu/o3/isa_specific.hh"
50 #include "cpu/base_dyn_inst.hh"
51 #include "cpu/inst_seq.hh"
56 * Mostly implementation & ISA specific AlphaDynInst. As with most
57 * other classes in the new CPU model, it is templated on the Impl to
58 * allow for passing in of all types, such as the CPU type and the ISA
59 * type. The AlphaDynInst serves as the primary interface to the CPU
60 * for instructions that are executing.
63 class BaseO3DynInst : public BaseDynInst<Impl>
66 /** Typedef for the CPU. */
67 typedef typename Impl::O3CPU O3CPU;
69 /** Binary machine instruction type. */
70 typedef TheISA::MachInst MachInst;
71 /** Extended machine instruction type. */
72 typedef TheISA::ExtMachInst ExtMachInst;
73 /** Logical register index type. */
74 typedef TheISA::RegIndex RegIndex;
75 /** Integer register index type. */
76 typedef TheISA::IntReg IntReg;
77 typedef TheISA::FloatReg FloatReg;
78 typedef TheISA::FloatRegBits FloatRegBits;
79 /** Misc register index type. */
80 typedef TheISA::MiscReg MiscReg;
83 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
84 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
88 /** BaseDynInst constructor given a binary instruction. */
89 BaseO3DynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
90 TheISA::PCState pc, TheISA::PCState predPC,
91 InstSeqNum seq_num, O3CPU *cpu);
93 /** BaseDynInst constructor given a static inst pointer. */
94 BaseO3DynInst(StaticInstPtr _staticInst, StaticInstPtr _macroop);
96 /** Executes the instruction.*/
99 /** Initiates the access. Only valid for memory operations. */
102 /** Completes the access. Only valid for memory operations. */
103 Fault completeAcc(PacketPtr pkt);
106 /** Initializes variables. */
110 /** Values to be written to the destination misc. registers. */
111 MiscReg _destMiscRegVal[TheISA::MaxMiscDestRegs];
113 /** Indexes of the destination misc. registers. They are needed to defer
114 * the write accesses to the misc. registers until the commit stage, when
115 * the instruction is out of its speculative state.
117 short _destMiscRegIdx[TheISA::MaxMiscDestRegs];
119 /** Number of destination misc. registers. */
120 uint8_t _numDestMiscRegs;
125 /** Tick records used for the pipeline activity viewer. */
129 uint32_t dispatchTick;
131 uint32_t completeTick;
134 /** Reads a misc. register, including any side-effects the read
135 * might have as defined by the architecture.
137 MiscReg readMiscReg(int misc_reg)
139 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
142 /** Sets a misc. register, including any side-effects the write
143 * might have as defined by the architecture.
145 void setMiscReg(int misc_reg, const MiscReg &val)
147 /** Writes to misc. registers are recorded and deferred until the
148 * commit stage, when updateMiscRegs() is called.
150 assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs);
151 _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
152 _destMiscRegVal[_numDestMiscRegs] = val;
156 /** Reads a misc. register, including any side-effects the read
157 * might have as defined by the architecture.
159 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
161 return this->cpu->readMiscReg(
162 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
166 /** Sets a misc. register, including any side-effects the write
167 * might have as defined by the architecture.
169 void setMiscRegOperand(const StaticInst *si, int idx,
172 int misc_reg = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
173 setMiscReg(misc_reg, val);
176 /** Called at the commit stage to update the misc. registers. */
177 void updateMiscRegs()
179 // @todo: Pretty convoluted way to avoid squashing from happening when
180 // using the TC during an instruction's execution (specifically for
181 // instructions that have side-effects that use the TC). Fix this.
182 // See cpu/o3/dyn_inst_impl.hh.
183 bool in_syscall = this->thread->inSyscall;
184 this->thread->inSyscall = true;
186 for (int i = 0; i < _numDestMiscRegs; i++)
187 this->cpu->setMiscReg(
188 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
190 this->thread->inSyscall = in_syscall;
193 void forwardOldRegs()
196 for (int idx = 0; idx < this->numDestRegs(); idx++) {
197 PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
198 TheISA::RegIndex original_dest_reg = this->staticInst->destRegIdx(idx);
199 if (original_dest_reg < TheISA::FP_Base_DepTag)
200 this->setIntRegOperand(this->staticInst.get(), idx, this->cpu->readIntReg(prev_phys_reg));
201 else if (original_dest_reg < TheISA::Ctrl_Base_DepTag)
202 this->setFloatRegOperandBits(this->staticInst.get(), idx, this->cpu->readFloatRegBits(prev_phys_reg));
205 /** Calls hardware return from error interrupt. */
207 /** Traps to handle specified fault. */
208 void trap(Fault fault);
209 bool simPalCheck(int palFunc);
211 /** Emulates a syscall. */
212 void syscall(int64_t callnum);
216 // The register accessor methods provide the index of the
217 // instruction's operand (e.g., 0 or 1), not the architectural
218 // register index, to simplify the implementation of register
219 // renaming. We find the architectural register index by indexing
220 // into the instruction's own operand index table. Note that a
221 // raw pointer to the StaticInst is provided instead of a
222 // ref-counted StaticInstPtr to redice overhead. This is fine as
223 // long as these methods don't copy the pointer into any long-term
224 // storage (which is pretty hard to imagine they would have reason
227 uint64_t readIntRegOperand(const StaticInst *si, int idx)
229 return this->cpu->readIntReg(this->_srcRegIdx[idx]);
232 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
234 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
237 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
239 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
242 /** @todo: Make results into arrays so they can handle multiple dest
245 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
247 this->cpu->setIntReg(this->_destRegIdx[idx], val);
248 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
251 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
253 this->cpu->setFloatReg(this->_destRegIdx[idx], val);
254 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
257 void setFloatRegOperandBits(const StaticInst *si, int idx,
260 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
261 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
264 #if THE_ISA == MIPS_ISA
265 uint64_t readRegOtherThread(int misc_reg)
267 panic("MIPS MT not defined for O3 CPU.\n");
271 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
273 panic("MIPS MT not defined for O3 CPU.\n");
278 /** Calculates EA part of a memory instruction. Currently unused,
279 * though it may be useful in the future if we want to split
280 * memory operations into EA calculation and memory access parts.
284 return this->staticInst->eaCompInst()->execute(this, this->traceData);
287 /** Does the memory access part of a memory instruction. Currently unused,
288 * though it may be useful in the future if we want to split
289 * memory operations into EA calculation and memory access parts.
293 return this->staticInst->memAccInst()->execute(this, this->traceData);
297 #endif // __CPU_O3_ALPHA_DYN_INST_HH__