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44 #ifndef __CPU_O3_DYN_INST_HH__
45 #define __CPU_O3_DYN_INST_HH__
49 #include "arch/isa_traits.hh"
50 #include "config/the_isa.hh"
51 #include "cpu/o3/cpu.hh"
52 #include "cpu/o3/isa_specific.hh"
53 #include "cpu/base_dyn_inst.hh"
54 #include "cpu/inst_seq.hh"
55 #include "cpu/reg_class.hh"
60 class BaseO3DynInst : public BaseDynInst<Impl>
63 /** Typedef for the CPU. */
64 typedef typename Impl::O3CPU O3CPU;
66 /** Binary machine instruction type. */
67 typedef TheISA::MachInst MachInst;
68 /** Register types. */
69 using VecRegContainer = TheISA::VecRegContainer;
70 using VecElem = TheISA::VecElem;
71 static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
72 using VecPredRegContainer = TheISA::VecPredRegContainer;
75 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
76 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
80 /** BaseDynInst constructor given a binary instruction. */
81 BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr
82 ¯oop, TheISA::PCState pc, TheISA::PCState predPC,
83 InstSeqNum seq_num, O3CPU *cpu);
85 /** BaseDynInst constructor given a static inst pointer. */
86 BaseO3DynInst(const StaticInstPtr &_staticInst,
87 const StaticInstPtr &_macroop);
91 /** Executes the instruction.*/
94 /** Initiates the access. Only valid for memory operations. */
97 /** Completes the access. Only valid for memory operations. */
98 Fault completeAcc(PacketPtr pkt);
101 /** Initializes variables. */
105 /** Explicitation of dependent names. */
106 using BaseDynInst<Impl>::cpu;
107 using BaseDynInst<Impl>::_srcRegIdx;
108 using BaseDynInst<Impl>::_destRegIdx;
110 /** Values to be written to the destination misc. registers. */
111 std::array<RegVal, TheISA::MaxMiscDestRegs> _destMiscRegVal;
113 /** Indexes of the destination misc. registers. They are needed to defer
114 * the write accesses to the misc. registers until the commit stage, when
115 * the instruction is out of its speculative state.
117 std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx;
119 /** Number of destination misc. registers. */
120 uint8_t _numDestMiscRegs;
125 /** Tick records used for the pipeline activity viewer. */
126 Tick fetchTick; // instruction fetch is completed.
127 int32_t decodeTick; // instruction enters decode phase
128 int32_t renameTick; // instruction enters rename phase
129 int32_t dispatchTick;
131 int32_t completeTick;
136 /** Reads a misc. register, including any side-effects the read
137 * might have as defined by the architecture.
140 readMiscReg(int misc_reg) override
142 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
145 /** Sets a misc. register, including any side-effects the write
146 * might have as defined by the architecture.
149 setMiscReg(int misc_reg, RegVal val) override
151 /** Writes to misc. registers are recorded and deferred until the
152 * commit stage, when updateMiscRegs() is called. First, check if
153 * the misc reg has been written before and update its value to be
154 * committed instead of making a new entry. If not, make a new
155 * entry and record the write.
157 for (int idx = 0; idx < _numDestMiscRegs; idx++) {
158 if (_destMiscRegIdx[idx] == misc_reg) {
159 _destMiscRegVal[idx] = val;
164 assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs);
165 _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
166 _destMiscRegVal[_numDestMiscRegs] = val;
170 /** Reads a misc. register, including any side-effects the read
171 * might have as defined by the architecture.
174 readMiscRegOperand(const StaticInst *si, int idx) override
176 const RegId& reg = si->srcRegIdx(idx);
177 assert(reg.isMiscReg());
178 return this->cpu->readMiscReg(reg.index(), this->threadNumber);
181 /** Sets a misc. register, including any side-effects the write
182 * might have as defined by the architecture.
185 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
187 const RegId& reg = si->destRegIdx(idx);
188 assert(reg.isMiscReg());
189 setMiscReg(reg.index(), val);
192 /** Called at the commit stage to update the misc. registers. */
196 // @todo: Pretty convoluted way to avoid squashing from happening when
197 // using the TC during an instruction's execution (specifically for
198 // instructions that have side-effects that use the TC). Fix this.
199 // See cpu/o3/dyn_inst_impl.hh.
200 bool no_squash_from_TC = this->thread->noSquashFromTC;
201 this->thread->noSquashFromTC = true;
203 for (int i = 0; i < _numDestMiscRegs; i++)
204 this->cpu->setMiscReg(
205 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
207 this->thread->noSquashFromTC = no_squash_from_TC;
210 void forwardOldRegs()
213 for (int idx = 0; idx < this->numDestRegs(); idx++) {
214 PhysRegIdPtr prev_phys_reg = this->prevDestRegIdx(idx);
215 const RegId& original_dest_reg =
216 this->staticInst->destRegIdx(idx);
217 switch (original_dest_reg.classValue()) {
219 this->setIntRegOperand(this->staticInst.get(), idx,
220 this->cpu->readIntReg(prev_phys_reg));
223 this->setFloatRegOperandBits(this->staticInst.get(), idx,
224 this->cpu->readFloatReg(prev_phys_reg));
227 this->setVecRegOperand(this->staticInst.get(), idx,
228 this->cpu->readVecReg(prev_phys_reg));
231 this->setVecElemOperand(this->staticInst.get(), idx,
232 this->cpu->readVecElem(prev_phys_reg));
234 case VecPredRegClass:
235 this->setVecPredRegOperand(this->staticInst.get(), idx,
236 this->cpu->readVecPredReg(prev_phys_reg));
239 this->setCCRegOperand(this->staticInst.get(), idx,
240 this->cpu->readCCReg(prev_phys_reg));
243 // no need to forward misc reg values
246 panic("Unknown register class: %d",
247 (int)original_dest_reg.classValue());
251 /** Traps to handle specified fault. */
252 void trap(const Fault &fault);
254 /** Emulates a syscall. */
255 void syscall(Fault *fault) override;
259 // The register accessor methods provide the index of the
260 // instruction's operand (e.g., 0 or 1), not the architectural
261 // register index, to simplify the implementation of register
262 // renaming. We find the architectural register index by indexing
263 // into the instruction's own operand index table. Note that a
264 // raw pointer to the StaticInst is provided instead of a
265 // ref-counted StaticInstPtr to redice overhead. This is fine as
266 // long as these methods don't copy the pointer into any long-term
267 // storage (which is pretty hard to imagine they would have reason
271 readIntRegOperand(const StaticInst *si, int idx) override
273 return this->cpu->readIntReg(this->_srcRegIdx[idx]);
277 readFloatRegOperandBits(const StaticInst *si, int idx) override
279 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
282 const VecRegContainer&
283 readVecRegOperand(const StaticInst *si, int idx) const override
285 return this->cpu->readVecReg(this->_srcRegIdx[idx]);
289 * Read destination vector register operand for modification.
292 getWritableVecRegOperand(const StaticInst *si, int idx) override
294 return this->cpu->getWritableVecReg(this->_destRegIdx[idx]);
297 /** Vector Register Lane Interfaces. */
299 /** Reads source vector 8bit operand. */
301 readVec8BitLaneOperand(const StaticInst *si, int idx) const override
303 return cpu->template readVecLane<uint8_t>(_srcRegIdx[idx]);
306 /** Reads source vector 16bit operand. */
308 readVec16BitLaneOperand(const StaticInst *si, int idx) const override
310 return cpu->template readVecLane<uint16_t>(_srcRegIdx[idx]);
313 /** Reads source vector 32bit operand. */
315 readVec32BitLaneOperand(const StaticInst *si, int idx) const override
317 return cpu->template readVecLane<uint32_t>(_srcRegIdx[idx]);
320 /** Reads source vector 64bit operand. */
322 readVec64BitLaneOperand(const StaticInst *si, int idx) const override
324 return cpu->template readVecLane<uint64_t>(_srcRegIdx[idx]);
327 /** Write a lane of the destination vector operand. */
328 template <typename LD>
330 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
332 return cpu->template setVecLane(_destRegIdx[idx], val);
335 setVecLaneOperand(const StaticInst *si, int idx,
336 const LaneData<LaneSize::Byte>& val) override
338 return setVecLaneOperandT(si, idx, val);
341 setVecLaneOperand(const StaticInst *si, int idx,
342 const LaneData<LaneSize::TwoByte>& val) override
344 return setVecLaneOperandT(si, idx, val);
347 setVecLaneOperand(const StaticInst *si, int idx,
348 const LaneData<LaneSize::FourByte>& val) override
350 return setVecLaneOperandT(si, idx, val);
353 setVecLaneOperand(const StaticInst *si, int idx,
354 const LaneData<LaneSize::EightByte>& val) override
356 return setVecLaneOperandT(si, idx, val);
360 VecElem readVecElemOperand(const StaticInst *si, int idx) const override
362 return this->cpu->readVecElem(this->_srcRegIdx[idx]);
365 const VecPredRegContainer&
366 readVecPredRegOperand(const StaticInst *si, int idx) const override
368 return this->cpu->readVecPredReg(this->_srcRegIdx[idx]);
372 getWritableVecPredRegOperand(const StaticInst *si, int idx) override
374 return this->cpu->getWritableVecPredReg(this->_destRegIdx[idx]);
378 readCCRegOperand(const StaticInst *si, int idx) override
380 return this->cpu->readCCReg(this->_srcRegIdx[idx]);
383 /** @todo: Make results into arrays so they can handle multiple dest
387 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
389 this->cpu->setIntReg(this->_destRegIdx[idx], val);
390 BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
394 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
396 this->cpu->setFloatReg(this->_destRegIdx[idx], val);
397 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
401 setVecRegOperand(const StaticInst *si, int idx,
402 const VecRegContainer& val) override
404 this->cpu->setVecReg(this->_destRegIdx[idx], val);
405 BaseDynInst<Impl>::setVecRegOperand(si, idx, val);
408 void setVecElemOperand(const StaticInst *si, int idx,
409 const VecElem val) override
412 this->cpu->setVecElem(this->_destRegIdx[reg_idx], val);
413 BaseDynInst<Impl>::setVecElemOperand(si, idx, val);
417 setVecPredRegOperand(const StaticInst *si, int idx,
418 const VecPredRegContainer& val) override
420 this->cpu->setVecPredReg(this->_destRegIdx[idx], val);
421 BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val);
424 void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
426 this->cpu->setCCReg(this->_destRegIdx[idx], val);
427 BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
431 #endif // __CPU_O3_ALPHA_DYN_INST_HH__