src/cpu/o3/dyn_inst.hh

   1 /*
   2  * Copyright (c) 2010, 2016 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
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  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #ifndef __CPU_O3_DYN_INST_HH__
  43 #define __CPU_O3_DYN_INST_HH__
  44
  45 #include <array>
  46
  47 #include "config/the_isa.hh"
  48 #include "cpu/o3/cpu.hh"
  49 #include "cpu/o3/isa_specific.hh"
  50 #include "cpu/base_dyn_inst.hh"
  51 #include "cpu/inst_seq.hh"
  52 #include "cpu/reg_class.hh"
  53
  54 class Packet;
  55
  56 template <class Impl>
  57 class BaseO3DynInst : public BaseDynInst<Impl>
  58 {
  59   public:
  60     /** Typedef for the CPU. */
  61     typedef typename Impl::O3CPU O3CPU;
  62
  63     /** Register types. */
  64     static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
  65
  66   public:
  67     /** BaseDynInst constructor given a binary instruction. */
  68     BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr
  69             &macroop, TheISA::PCState pc, TheISA::PCState predPC,
  70             InstSeqNum seq_num, O3CPU *cpu);
  71
  72     /** BaseDynInst constructor given a static inst pointer. */
  73     BaseO3DynInst(const StaticInstPtr &_staticInst,
  74                   const StaticInstPtr &_macroop);
  75
  76     ~BaseO3DynInst();
  77
  78     /** Executes the instruction.*/
  79     Fault execute();
  80
  81     /** Initiates the access.  Only valid for memory operations. */
  82     Fault initiateAcc();
  83
  84     /** Completes the access.  Only valid for memory operations. */
  85     Fault completeAcc(PacketPtr pkt);
  86
  87   private:
  88     /** Initializes variables. */
  89     void initVars();
  90
  91   protected:
  92     /** Explicitation of dependent names. */
  93     using BaseDynInst<Impl>::cpu;
  94
  95     /** Values to be written to the destination misc. registers. */
  96     std::array<RegVal, TheISA::MaxMiscDestRegs> _destMiscRegVal;
  97
  98     /** Indexes of the destination misc. registers. They are needed to defer
  99      * the write accesses to the misc. registers until the commit stage, when
 100      * the instruction is out of its speculative state.
 101      */
 102     std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx;
 103
 104     /** Number of destination misc. registers. */
 105     uint8_t _numDestMiscRegs;
 106
 107
 108   public:
 109 #if TRACING_ON
 110     /** Tick records used for the pipeline activity viewer. */
 111     Tick fetchTick;      // instruction fetch is completed.
 112     int32_t decodeTick;  // instruction enters decode phase
 113     int32_t renameTick;  // instruction enters rename phase
 114     int32_t dispatchTick;
 115     int32_t issueTick;
 116     int32_t completeTick;
 117     int32_t commitTick;
 118     int32_t storeTick;
 119 #endif
 120
 121     /** Reads a misc. register, including any side-effects the read
 122      * might have as defined by the architecture.
 123      */
 124     RegVal
 125     readMiscReg(int misc_reg) override
 126     {
 127         return this->cpu->readMiscReg(misc_reg, this->threadNumber);
 128     }
 129
 130     /** Sets a misc. register, including any side-effects the write
 131      * might have as defined by the architecture.
 132      */
 133     void
 134     setMiscReg(int misc_reg, RegVal val) override
 135     {
 136         /** Writes to misc. registers are recorded and deferred until the
 137          * commit stage, when updateMiscRegs() is called. First, check if
 138          * the misc reg has been written before and update its value to be
 139          * committed instead of making a new entry. If not, make a new
 140          * entry and record the write.
 141          */
 142         for (int idx = 0; idx < _numDestMiscRegs; idx++) {
 143             if (_destMiscRegIdx[idx] == misc_reg) {
 144                _destMiscRegVal[idx] = val;
 145                return;
 146             }
 147         }
 148
 149         assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs);
 150         _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
 151         _destMiscRegVal[_numDestMiscRegs] = val;
 152         _numDestMiscRegs++;
 153     }
 154
 155     /** Reads a misc. register, including any side-effects the read
 156      * might have as defined by the architecture.
 157      */
 158     RegVal
 159     readMiscRegOperand(const StaticInst *si, int idx) override
 160     {
 161         const RegId& reg = si->srcRegIdx(idx);
 162         assert(reg.isMiscReg());
 163         return this->cpu->readMiscReg(reg.index(), this->threadNumber);
 164     }
 165
 166     /** Sets a misc. register, including any side-effects the write
 167      * might have as defined by the architecture.
 168      */
 169     void
 170     setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
 171     {
 172         const RegId& reg = si->destRegIdx(idx);
 173         assert(reg.isMiscReg());
 174         setMiscReg(reg.index(), val);
 175     }
 176
 177     /** Called at the commit stage to update the misc. registers. */
 178     void
 179     updateMiscRegs()
 180     {
 181         // @todo: Pretty convoluted way to avoid squashing from happening when
 182         // using the TC during an instruction's execution (specifically for
 183         // instructions that have side-effects that use the TC).  Fix this.
 184         // See cpu/o3/dyn_inst_impl.hh.
 185         bool no_squash_from_TC = this->thread->noSquashFromTC;
 186         this->thread->noSquashFromTC = true;
 187
 188         for (int i = 0; i < _numDestMiscRegs; i++)
 189             this->cpu->setMiscReg(
 190                 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
 191
 192         this->thread->noSquashFromTC = no_squash_from_TC;
 193     }
 194
 195     void forwardOldRegs()
 196     {
 197
 198         for (int idx = 0; idx < this->numDestRegs(); idx++) {
 199             PhysRegIdPtr prev_phys_reg = this->regs.prevDestIdx(idx);
 200             const RegId& original_dest_reg =
 201                 this->staticInst->destRegIdx(idx);
 202             switch (original_dest_reg.classValue()) {
 203               case IntRegClass:
 204                 this->setIntRegOperand(this->staticInst.get(), idx,
 205                                this->cpu->readIntReg(prev_phys_reg));
 206                 break;
 207               case FloatRegClass:
 208                 this->setFloatRegOperandBits(this->staticInst.get(), idx,
 209                                this->cpu->readFloatReg(prev_phys_reg));
 210                 break;
 211               case VecRegClass:
 212                 this->setVecRegOperand(this->staticInst.get(), idx,
 213                                this->cpu->readVecReg(prev_phys_reg));
 214                 break;
 215               case VecElemClass:
 216                 this->setVecElemOperand(this->staticInst.get(), idx,
 217                                this->cpu->readVecElem(prev_phys_reg));
 218                 break;
 219               case VecPredRegClass:
 220                 this->setVecPredRegOperand(this->staticInst.get(), idx,
 221                                this->cpu->readVecPredReg(prev_phys_reg));
 222                 break;
 223               case CCRegClass:
 224                 this->setCCRegOperand(this->staticInst.get(), idx,
 225                                this->cpu->readCCReg(prev_phys_reg));
 226                 break;
 227               case MiscRegClass:
 228                 // no need to forward misc reg values
 229                 break;
 230               default:
 231                 panic("Unknown register class: %d",
 232                         (int)original_dest_reg.classValue());
 233             }
 234         }
 235     }
 236     /** Traps to handle specified fault. */
 237     void trap(const Fault &fault);
 238
 239   public:
 240
 241     // The register accessor methods provide the index of the
 242     // instruction's operand (e.g., 0 or 1), not the architectural
 243     // register index, to simplify the implementation of register
 244     // renaming.  We find the architectural register index by indexing
 245     // into the instruction's own operand index table.  Note that a
 246     // raw pointer to the StaticInst is provided instead of a
 247     // ref-counted StaticInstPtr to redice overhead.  This is fine as
 248     // long as these methods don't copy the pointer into any long-term
 249     // storage (which is pretty hard to imagine they would have reason
 250     // to do).
 251
 252     RegVal
 253     readIntRegOperand(const StaticInst *si, int idx) override
 254     {
 255         return this->cpu->readIntReg(this->regs.renamedSrcIdx(idx));
 256     }
 257
 258     RegVal
 259     readFloatRegOperandBits(const StaticInst *si, int idx) override
 260     {
 261         return this->cpu->readFloatReg(this->regs.renamedSrcIdx(idx));
 262     }
 263
 264     const TheISA::VecRegContainer&
 265     readVecRegOperand(const StaticInst *si, int idx) const override
 266     {
 267         return this->cpu->readVecReg(this->regs.renamedSrcIdx(idx));
 268     }
 269
 270     /**
 271      * Read destination vector register operand for modification.
 272      */
 273     TheISA::VecRegContainer&
 274     getWritableVecRegOperand(const StaticInst *si, int idx) override
 275     {
 276         return this->cpu->getWritableVecReg(this->regs.renamedDestIdx(idx));
 277     }
 278
 279     /** Vector Register Lane Interfaces. */
 280     /** @{ */
 281     /** Reads source vector 8bit operand. */
 282     ConstVecLane8
 283     readVec8BitLaneOperand(const StaticInst *si, int idx) const override
 284     {
 285         return cpu->template readVecLane<uint8_t>(
 286                 this->regs.renamedSrcIdx(idx));
 287     }
 288
 289     /** Reads source vector 16bit operand. */
 290     ConstVecLane16
 291     readVec16BitLaneOperand(const StaticInst *si, int idx) const override
 292     {
 293         return cpu->template readVecLane<uint16_t>(
 294                 this->regs.renamedSrcIdx(idx));
 295     }
 296
 297     /** Reads source vector 32bit operand. */
 298     ConstVecLane32
 299     readVec32BitLaneOperand(const StaticInst *si, int idx) const override
 300     {
 301         return cpu->template readVecLane<uint32_t>(
 302                 this->regs.renamedSrcIdx(idx));
 303     }
 304
 305     /** Reads source vector 64bit operand. */
 306     ConstVecLane64
 307     readVec64BitLaneOperand(const StaticInst *si, int idx) const override
 308     {
 309         return cpu->template readVecLane<uint64_t>(
 310                 this->regs.renamedSrcIdx(idx));
 311     }
 312
 313     /** Write a lane of the destination vector operand. */
 314     template <typename LD>
 315     void
 316     setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
 317     {
 318         return cpu->template setVecLane(this->regs.renamedDestIdx(idx), val);
 319     }
 320     virtual void
 321     setVecLaneOperand(const StaticInst *si, int idx,
 322             const LaneData<LaneSize::Byte>& val) override
 323     {
 324         return setVecLaneOperandT(si, idx, val);
 325     }
 326     virtual void
 327     setVecLaneOperand(const StaticInst *si, int idx,
 328             const LaneData<LaneSize::TwoByte>& val) override
 329     {
 330         return setVecLaneOperandT(si, idx, val);
 331     }
 332     virtual void
 333     setVecLaneOperand(const StaticInst *si, int idx,
 334             const LaneData<LaneSize::FourByte>& val) override
 335     {
 336         return setVecLaneOperandT(si, idx, val);
 337     }
 338     virtual void
 339     setVecLaneOperand(const StaticInst *si, int idx,
 340             const LaneData<LaneSize::EightByte>& val) override
 341     {
 342         return setVecLaneOperandT(si, idx, val);
 343     }
 344     /** @} */
 345
 346     TheISA::VecElem
 347     readVecElemOperand(const StaticInst *si, int idx) const override
 348     {
 349         return this->cpu->readVecElem(this->regs.renamedSrcIdx(idx));
 350     }
 351
 352     const TheISA::VecPredRegContainer&
 353     readVecPredRegOperand(const StaticInst *si, int idx) const override
 354     {
 355         return this->cpu->readVecPredReg(this->regs.renamedSrcIdx(idx));
 356     }
 357
 358     TheISA::VecPredRegContainer&
 359     getWritableVecPredRegOperand(const StaticInst *si, int idx) override
 360     {
 361         return this->cpu->getWritableVecPredReg(
 362                 this->regs.renamedDestIdx(idx));
 363     }
 364
 365     RegVal
 366     readCCRegOperand(const StaticInst *si, int idx) override
 367     {
 368         return this->cpu->readCCReg(this->regs.renamedSrcIdx(idx));
 369     }
 370
 371     /** @todo: Make results into arrays so they can handle multiple dest
 372      *  registers.
 373      */
 374     void
 375     setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
 376     {
 377         this->cpu->setIntReg(this->regs.renamedDestIdx(idx), val);
 378         BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
 379     }
 380
 381     void
 382     setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
 383     {
 384         this->cpu->setFloatReg(this->regs.renamedDestIdx(idx), val);
 385         BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
 386     }
 387
 388     void
 389     setVecRegOperand(const StaticInst *si, int idx,
 390                      const TheISA::VecRegContainer& val) override
 391     {
 392         this->cpu->setVecReg(this->regs.renamedDestIdx(idx), val);
 393         BaseDynInst<Impl>::setVecRegOperand(si, idx, val);
 394     }
 395
 396     void
 397     setVecElemOperand(const StaticInst *si, int idx,
 398             const TheISA::VecElem val) override
 399     {
 400         int reg_idx = idx;
 401         this->cpu->setVecElem(this->regs.renamedDestIdx(reg_idx), val);
 402         BaseDynInst<Impl>::setVecElemOperand(si, idx, val);
 403     }
 404
 405     void
 406     setVecPredRegOperand(const StaticInst *si, int idx,
 407                          const TheISA::VecPredRegContainer& val) override
 408     {
 409         this->cpu->setVecPredReg(this->regs.renamedDestIdx(idx), val);
 410         BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val);
 411     }
 412
 413     void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
 414     {
 415         this->cpu->setCCReg(this->regs.renamedDestIdx(idx), val);
 416         BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
 417     }
 418 };
 419
 420 #endif // __CPU_O3_ALPHA_DYN_INST_HH__
 421