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43 #include "base/cp_annotate.hh"
44 #include "cpu/o3/dyn_inst.hh"
45 #include "sim/full_system.hh"
46 #include "debug/O3PipeView.hh"
49 BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
50 StaticInstPtr macroop,
51 TheISA::PCState pc, TheISA::PCState predPC,
52 InstSeqNum seq_num, O3CPU *cpu)
53 : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
59 BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr _staticInst,
60 StaticInstPtr _macroop)
61 : BaseDynInst<Impl>(_staticInst, _macroop)
66 template <class Impl>BaseO3DynInst<Impl>::~BaseO3DynInst()
69 Tick val, fetch = this->fetchTick;
70 // Print info needed by the pipeline activity viewer.
71 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
76 this->staticInst->disassemble(this->instAddr()));
77 val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick;
78 DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val);
79 val = (this->renameTick == -1) ? 0 : fetch + this->renameTick;
80 DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", val);
81 val = (this->dispatchTick == -1) ? 0 : fetch + this->dispatchTick;
82 DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", val);
83 val = (this->issueTick == -1) ? 0 : fetch + this->issueTick;
84 DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", val);
85 val = (this->completeTick == -1) ? 0 : fetch + this->completeTick;
86 DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", val);
87 val = (this->commitTick == -1) ? 0 : fetch + this->commitTick;
88 DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", val);
95 BaseO3DynInst<Impl>::initVars()
97 // Make sure to have the renamed register entries set to the same
98 // as the normal register entries. It will allow the IQ to work
99 // without any modifications.
100 for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
101 this->_destRegIdx[i] = this->staticInst->destRegIdx(i);
104 for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
105 this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
108 this->_readySrcRegIdx.reset();
110 _numDestMiscRegs = 0;
113 // Value -1 indicates that particular phase
114 // hasn't happened (yet).
125 template <class Impl>
127 BaseO3DynInst<Impl>::execute()
129 // @todo: Pretty convoluted way to avoid squashing from happening
130 // when using the TC during an instruction's execution
131 // (specifically for instructions that have side-effects that use
132 // the TC). Fix this.
133 bool in_syscall = this->thread->inSyscall;
134 this->thread->inSyscall = true;
136 this->fault = this->staticInst->execute(this, this->traceData);
138 this->thread->inSyscall = in_syscall;
143 template <class Impl>
145 BaseO3DynInst<Impl>::initiateAcc()
147 // @todo: Pretty convoluted way to avoid squashing from happening
148 // when using the TC during an instruction's execution
149 // (specifically for instructions that have side-effects that use
150 // the TC). Fix this.
151 bool in_syscall = this->thread->inSyscall;
152 this->thread->inSyscall = true;
154 this->fault = this->staticInst->initiateAcc(this, this->traceData);
156 this->thread->inSyscall = in_syscall;
161 template <class Impl>
163 BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
165 // @todo: Pretty convoluted way to avoid squashing from happening
166 // when using the TC during an instruction's execution
167 // (specifically for instructions that have side-effects that use
168 // the TC). Fix this.
169 bool in_syscall = this->thread->inSyscall;
170 this->thread->inSyscall = true;
172 if (this->cpu->checker) {
173 if (this->isStoreConditional()) {
174 this->reqToVerify->setExtraData(pkt->req->getExtraData());
178 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
180 this->thread->inSyscall = in_syscall;
185 template <class Impl>
187 BaseO3DynInst<Impl>::hwrei()
189 #if THE_ISA == ALPHA_ISA
190 // Can only do a hwrei when in pal mode.
191 if (!(this->instAddr() & 0x3))
192 return new AlphaISA::UnimplementedOpcodeFault;
194 // Set the next PC based on the value of the EXC_ADDR IPR.
195 AlphaISA::PCState pc = this->pcState();
196 pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
197 this->threadNumber));
199 if (CPA::available()) {
200 ThreadContext *tc = this->cpu->tcBase(this->threadNumber);
201 CPA::cpa()->swAutoBegin(tc, this->nextInstAddr());
204 // Tell CPU to clear any state it needs to if a hwrei is taken.
205 this->cpu->hwrei(this->threadNumber);
209 // FIXME: XXX check for interrupts? XXX
213 template <class Impl>
215 BaseO3DynInst<Impl>::trap(Fault fault)
217 this->cpu->trap(fault, this->threadNumber, this->staticInst);
220 template <class Impl>
222 BaseO3DynInst<Impl>::simPalCheck(int palFunc)
224 #if THE_ISA != ALPHA_ISA
225 panic("simPalCheck called, but PAL only exists in Alpha!\n");
227 return this->cpu->simPalCheck(palFunc, this->threadNumber);
230 template <class Impl>
232 BaseO3DynInst<Impl>::syscall(int64_t callnum)
235 panic("Syscall emulation isn't available in FS mode.\n");
237 // HACK: check CPU's nextPC before and after syscall. If it
238 // changes, update this instruction's nextPC because the syscall
239 // must have changed the nextPC.
240 TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
241 this->cpu->syscall(callnum, this->threadNumber);
242 TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
243 if (!(curPC == newPC)) {
244 this->pcState(newPC);