src/cpu/o3/dyn_inst_impl.hh

   1 /*
   2  * Copyright (c) 2010-2011 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  */
  42
  43 #ifndef __CPU_O3_DYN_INST_IMPL_HH__
  44 #define __CPU_O3_DYN_INST_IMPL_HH__
  45
  46 #include "base/cp_annotate.hh"
  47 #include "cpu/o3/dyn_inst.hh"
  48 #include "debug/O3PipeView.hh"
  49
  50 template <class Impl>
  51 BaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &staticInst,
  52                                    const StaticInstPtr &macroop,
  53                                    TheISA::PCState pc, TheISA::PCState predPC,
  54                                    InstSeqNum seq_num, O3CPU *cpu)
  55     : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
  56 {
  57     initVars();
  58 }
  59
  60 template <class Impl>
  61 BaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &_staticInst,
  62                                    const StaticInstPtr &_macroop)
  63     : BaseDynInst<Impl>(_staticInst, _macroop)
  64 {
  65     initVars();
  66 }
  67
  68 template <class Impl>BaseO3DynInst<Impl>::~BaseO3DynInst()
  69 {
  70 #if TRACING_ON
  71     if (DTRACE(O3PipeView)) {
  72         Tick fetch = this->fetchTick;
  73         // fetchTick can be -1 if the instruction fetched outside the trace window.
  74         if (fetch != -1) {
  75             Tick val;
  76             // Print info needed by the pipeline activity viewer.
  77             DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
  78                      fetch,
  79                      this->instAddr(),
  80                      this->microPC(),
  81                      this->seqNum,
  82                      this->staticInst->disassemble(this->instAddr()));
  83
  84             val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick;
  85             DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val);
  86             val = (this->renameTick == -1) ? 0 : fetch + this->renameTick;
  87             DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", val);
  88             val = (this->dispatchTick == -1) ? 0 : fetch + this->dispatchTick;
  89             DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", val);
  90             val = (this->issueTick == -1) ? 0 : fetch + this->issueTick;
  91             DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", val);
  92             val = (this->completeTick == -1) ? 0 : fetch + this->completeTick;
  93             DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", val);
  94             val = (this->commitTick == -1) ? 0 : fetch + this->commitTick;
  95
  96             Tick valS = (this->storeTick == -1) ? 0 : fetch + this->storeTick;
  97             DPRINTFR(O3PipeView, "O3PipeView:retire:%llu:store:%llu\n", val, valS);
  98         }
  99     }
 100 #endif
 101 };
 102
 103
 104 template <class Impl>
 105 void
 106 BaseO3DynInst<Impl>::initVars()
 107 {
 108     this->_readySrcRegIdx.reset();
 109
 110     _numDestMiscRegs = 0;
 111
 112 #if TRACING_ON
 113     // Value -1 indicates that particular phase
 114     // hasn't happened (yet).
 115     fetchTick = -1;
 116     decodeTick = -1;
 117     renameTick = -1;
 118     dispatchTick = -1;
 119     issueTick = -1;
 120     completeTick = -1;
 121     commitTick = -1;
 122     storeTick = -1;
 123 #endif
 124 }
 125
 126 template <class Impl>
 127 Fault
 128 BaseO3DynInst<Impl>::execute()
 129 {
 130     // @todo: Pretty convoluted way to avoid squashing from happening
 131     // when using the TC during an instruction's execution
 132     // (specifically for instructions that have side-effects that use
 133     // the TC).  Fix this.
 134     bool no_squash_from_TC = this->thread->noSquashFromTC;
 135     this->thread->noSquashFromTC = true;
 136
 137     this->fault = this->staticInst->execute(this, this->traceData);
 138
 139     this->thread->noSquashFromTC = no_squash_from_TC;
 140
 141     return this->fault;
 142 }
 143
 144 template <class Impl>
 145 Fault
 146 BaseO3DynInst<Impl>::initiateAcc()
 147 {
 148     // @todo: Pretty convoluted way to avoid squashing from happening
 149     // when using the TC during an instruction's execution
 150     // (specifically for instructions that have side-effects that use
 151     // the TC).  Fix this.
 152     bool no_squash_from_TC = this->thread->noSquashFromTC;
 153     this->thread->noSquashFromTC = true;
 154
 155     this->fault = this->staticInst->initiateAcc(this, this->traceData);
 156
 157     this->thread->noSquashFromTC = no_squash_from_TC;
 158
 159     return this->fault;
 160 }
 161
 162 template <class Impl>
 163 Fault
 164 BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
 165 {
 166     // @todo: Pretty convoluted way to avoid squashing from happening
 167     // when using the TC during an instruction's execution
 168     // (specifically for instructions that have side-effects that use
 169     // the TC).  Fix this.
 170     bool no_squash_from_TC = this->thread->noSquashFromTC;
 171     this->thread->noSquashFromTC = true;
 172
 173     if (this->cpu->checker) {
 174         if (this->isStoreConditional()) {
 175             this->reqToVerify->setExtraData(pkt->req->getExtraData());
 176         }
 177     }
 178
 179     this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
 180
 181     this->thread->noSquashFromTC = no_squash_from_TC;
 182
 183     return this->fault;
 184 }
 185
 186 template <class Impl>
 187 void
 188 BaseO3DynInst<Impl>::trap(const Fault &fault)
 189 {
 190     this->cpu->trap(fault, this->threadNumber, this->staticInst);
 191 }
 192
 193 template <class Impl>
 194 void
 195 BaseO3DynInst<Impl>::syscall(Fault *fault)
 196 {
 197     // HACK: check CPU's nextPC before and after syscall. If it
 198     // changes, update this instruction's nextPC because the syscall
 199     // must have changed the nextPC.
 200     TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
 201     this->cpu->syscall(this->threadNumber, fault);
 202     TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
 203     if (!(curPC == newPC)) {
 204         this->pcState(newPC);
 205     }
 206 }
 207
 208 #endif//__CPU_O3_DYN_INST_IMPL_HH__