src/cpu/o3/dyn_inst_impl.hh

   1 /*
   2  * Copyright (c) 2010-2011 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  */
  42
  43 #ifndef __CPU_O3_DYN_INST_IMPL_HH__
  44 #define __CPU_O3_DYN_INST_IMPL_HH__
  45
  46 #include "base/cp_annotate.hh"
  47 #include "cpu/o3/dyn_inst.hh"
  48 #include "sim/full_system.hh"
  49 #include "debug/O3PipeView.hh"
  50
  51 template <class Impl>
  52 BaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &staticInst,
  53                                    const StaticInstPtr &macroop,
  54                                    TheISA::PCState pc, TheISA::PCState predPC,
  55                                    InstSeqNum seq_num, O3CPU *cpu)
  56     : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
  57 {
  58     initVars();
  59 }
  60
  61 template <class Impl>
  62 BaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &_staticInst,
  63                                    const StaticInstPtr &_macroop)
  64     : BaseDynInst<Impl>(_staticInst, _macroop)
  65 {
  66     initVars();
  67 }
  68
  69 template <class Impl>BaseO3DynInst<Impl>::~BaseO3DynInst()
  70 {
  71 #if TRACING_ON
  72     if (DTRACE(O3PipeView)) {
  73         Tick fetch = this->fetchTick;
  74         // fetchTick can be -1 if the instruction fetched outside the trace window.
  75         if (fetch != -1) {
  76             Tick val;
  77             // Print info needed by the pipeline activity viewer.
  78             DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
  79                      fetch,
  80                      this->instAddr(),
  81                      this->microPC(),
  82                      this->seqNum,
  83                      this->staticInst->disassemble(this->instAddr()));
  84
  85             val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick;
  86             DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val);
  87             val = (this->renameTick == -1) ? 0 : fetch + this->renameTick;
  88             DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", val);
  89             val = (this->dispatchTick == -1) ? 0 : fetch + this->dispatchTick;
  90             DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", val);
  91             val = (this->issueTick == -1) ? 0 : fetch + this->issueTick;
  92             DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", val);
  93             val = (this->completeTick == -1) ? 0 : fetch + this->completeTick;
  94             DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", val);
  95             val = (this->commitTick == -1) ? 0 : fetch + this->commitTick;
  96
  97             Tick valS = (this->storeTick == -1) ? 0 : fetch + this->storeTick;
  98             DPRINTFR(O3PipeView, "O3PipeView:retire:%llu:store:%llu\n", val, valS);
  99         }
 100     }
 101 #endif
 102 };
 103
 104
 105 template <class Impl>
 106 void
 107 BaseO3DynInst<Impl>::initVars()
 108 {
 109     this->_readySrcRegIdx.reset();
 110
 111     _numDestMiscRegs = 0;
 112
 113 #if TRACING_ON
 114     // Value -1 indicates that particular phase
 115     // hasn't happened (yet).
 116     fetchTick = -1;
 117     decodeTick = -1;
 118     renameTick = -1;
 119     dispatchTick = -1;
 120     issueTick = -1;
 121     completeTick = -1;
 122     commitTick = -1;
 123     storeTick = -1;
 124 #endif
 125 }
 126
 127 template <class Impl>
 128 Fault
 129 BaseO3DynInst<Impl>::execute()
 130 {
 131     // @todo: Pretty convoluted way to avoid squashing from happening
 132     // when using the TC during an instruction's execution
 133     // (specifically for instructions that have side-effects that use
 134     // the TC).  Fix this.
 135     bool no_squash_from_TC = this->thread->noSquashFromTC;
 136     this->thread->noSquashFromTC = true;
 137
 138     this->fault = this->staticInst->execute(this, this->traceData);
 139
 140     this->thread->noSquashFromTC = no_squash_from_TC;
 141
 142     return this->fault;
 143 }
 144
 145 template <class Impl>
 146 Fault
 147 BaseO3DynInst<Impl>::initiateAcc()
 148 {
 149     // @todo: Pretty convoluted way to avoid squashing from happening
 150     // when using the TC during an instruction's execution
 151     // (specifically for instructions that have side-effects that use
 152     // the TC).  Fix this.
 153     bool no_squash_from_TC = this->thread->noSquashFromTC;
 154     this->thread->noSquashFromTC = true;
 155
 156     this->fault = this->staticInst->initiateAcc(this, this->traceData);
 157
 158     this->thread->noSquashFromTC = no_squash_from_TC;
 159
 160     return this->fault;
 161 }
 162
 163 template <class Impl>
 164 Fault
 165 BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
 166 {
 167     // @todo: Pretty convoluted way to avoid squashing from happening
 168     // when using the TC during an instruction's execution
 169     // (specifically for instructions that have side-effects that use
 170     // the TC).  Fix this.
 171     bool no_squash_from_TC = this->thread->noSquashFromTC;
 172     this->thread->noSquashFromTC = true;
 173
 174     if (this->cpu->checker) {
 175         if (this->isStoreConditional()) {
 176             this->reqToVerify->setExtraData(pkt->req->getExtraData());
 177         }
 178     }
 179
 180     this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
 181
 182     this->thread->noSquashFromTC = no_squash_from_TC;
 183
 184     return this->fault;
 185 }
 186
 187 template <class Impl>
 188 void
 189 BaseO3DynInst<Impl>::trap(const Fault &fault)
 190 {
 191     this->cpu->trap(fault, this->threadNumber, this->staticInst);
 192 }
 193
 194 template <class Impl>
 195 void
 196 BaseO3DynInst<Impl>::syscall(int64_t callnum, Fault *fault)
 197 {
 198     if (FullSystem)
 199         panic("Syscall emulation isn't available in FS mode.\n");
 200
 201     // HACK: check CPU's nextPC before and after syscall. If it
 202     // changes, update this instruction's nextPC because the syscall
 203     // must have changed the nextPC.
 204     TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
 205     this->cpu->syscall(callnum, this->threadNumber, fault);
 206     TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
 207     if (!(curPC == newPC)) {
 208         this->pcState(newPC);
 209     }
 210 }
 211
 212 #endif//__CPU_O3_DYN_INST_IMPL_HH__