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44 #ifndef __CPU_O3_FETCH_HH__
45 #define __CPU_O3_FETCH_HH__
47 #include "arch/decoder.hh"
48 #include "arch/utility.hh"
49 #include "base/statistics.hh"
50 #include "config/the_isa.hh"
51 #include "cpu/pc_event.hh"
52 #include "cpu/timebuf.hh"
53 #include "cpu/translation.hh"
54 #include "mem/packet.hh"
55 #include "mem/port.hh"
56 #include "sim/eventq.hh"
58 struct DerivO3CPUParams;
61 * DefaultFetch class handles both single threaded and SMT fetch. Its
62 * width is specified by the parameters; each cycle it tries to fetch
63 * that many instructions. It supports using a branch predictor to
64 * predict direction and targets.
65 * It supports the idling functionality of the CPU by indicating to
66 * the CPU when it is active and inactive.
72 /** Typedefs from Impl. */
73 typedef typename Impl::CPUPol CPUPol;
74 typedef typename Impl::DynInst DynInst;
75 typedef typename Impl::DynInstPtr DynInstPtr;
76 typedef typename Impl::O3CPU O3CPU;
78 /** Typedefs from the CPU policy. */
79 typedef typename CPUPol::BPredUnit BPredUnit;
80 typedef typename CPUPol::FetchStruct FetchStruct;
81 typedef typename CPUPol::TimeStruct TimeStruct;
83 /** Typedefs from ISA. */
84 typedef TheISA::MachInst MachInst;
85 typedef TheISA::ExtMachInst ExtMachInst;
87 class FetchTranslation : public BaseTLB::Translation
90 DefaultFetch<Impl> *fetch;
93 FetchTranslation(DefaultFetch<Impl> *_fetch)
102 finish(Fault fault, RequestPtr req, ThreadContext *tc,
105 assert(mode == BaseTLB::Execute);
106 fetch->finishTranslation(fault, req);
112 /* Event to delay delivery of a fetch translation result in case of
113 * a fault and the nop to carry the fault cannot be generated
115 class FinishTranslationEvent : public Event
118 DefaultFetch<Impl> *fetch;
123 FinishTranslationEvent(DefaultFetch<Impl> *_fetch)
127 void setFault(Fault _fault)
132 void setReq(RequestPtr _req)
137 /** Process the delayed finish translation */
140 assert(fetch->numInst < fetch->fetchWidth);
141 fetch->finishTranslation(fault, req);
144 const char *description() const
146 return "FullO3CPU FetchFinishTranslation";
151 /** Overall fetch status. Used to determine if the CPU can
152 * deschedule itsef due to a lack of activity.
159 /** Individual thread status. */
172 IcacheAccessComplete,
176 /** Fetching Policy, Add new policies here.*/
189 /** Per-thread status. */
190 ThreadStatus fetchStatus[Impl::MaxThreads];
193 FetchPriority fetchPolicy;
195 /** List that has the threads organized by priority. */
196 std::list<ThreadID> priorityList;
199 /** DefaultFetch constructor. */
200 DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
202 /** Returns the name of fetch. */
203 std::string name() const;
205 /** Registers statistics. */
208 /** Sets the main backwards communication time buffer pointer. */
209 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
211 /** Sets pointer to list of active threads. */
212 void setActiveThreads(std::list<ThreadID> *at_ptr);
214 /** Sets pointer to time buffer used to communicate to the next stage. */
215 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
217 /** Initialize stage. */
220 /** Tells the fetch stage that the Icache is set. */
223 /** Handles retrying the fetch access. */
226 /** Processes cache completion event. */
227 void processCacheCompletion(PacketPtr pkt);
229 /** Begins the drain of the fetch stage. */
232 /** Resumes execution after a drain. */
235 /** Tells fetch stage to prepare to be switched out. */
238 /** Takes over from another CPU's thread. */
241 /** Checks if the fetch stage is switched out. */
242 bool isSwitchedOut() { return switchedOut; }
244 /** Tells fetch to wake up from a quiesce instruction. */
245 void wakeFromQuiesce();
248 /** Changes the status of this stage to active, and indicates this
251 inline void switchToActive();
253 /** Changes the status of this stage to inactive, and indicates
256 inline void switchToInactive();
259 * Looks up in the branch predictor to see if the next PC should be
260 * either next PC+=MachInst or a branch target.
261 * @param next_PC Next PC variable passed in by reference. It is
262 * expected to be set to the current PC; it will be updated with what
263 * the next PC will be.
264 * @param next_NPC Used for ISAs which use delay slots.
265 * @return Whether or not a branch was predicted as taken.
267 bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc);
270 * Fetches the cache line that contains fetch_PC. Returns any
271 * fault that happened. Puts the data into the class variable
273 * @param vaddr The memory address that is being fetched from.
274 * @param ret_fault The fault reference that will be set to the result of
276 * @param tid Thread id.
277 * @param pc The actual PC of the current instruction.
278 * @return Any fault that occured.
280 bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
281 void finishTranslation(Fault fault, RequestPtr mem_req);
284 /** Check if an interrupt is pending and that we need to handle
287 checkInterrupt(Addr pc)
289 return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3)));
292 /** Squashes a specific thread and resets the PC. */
293 inline void doSquash(const TheISA::PCState &newPC,
294 const DynInstPtr squashInst, ThreadID tid);
296 /** Squashes a specific thread and resets the PC. Also tells the CPU to
297 * remove any instructions between fetch and decode that should be sqaushed.
299 void squashFromDecode(const TheISA::PCState &newPC,
300 const DynInstPtr squashInst,
301 const InstSeqNum seq_num, ThreadID tid);
303 /** Checks if a thread is stalled. */
304 bool checkStall(ThreadID tid) const;
306 /** Updates overall fetch stage status; to be called at the end of each
308 FetchStatus updateFetchStatus();
311 /** Squashes a specific thread and resets the PC. Also tells the CPU to
312 * remove any instructions that are not in the ROB. The source of this
313 * squash should be the commit stage.
315 void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
316 DynInstPtr squashInst, ThreadID tid);
318 /** Ticks the fetch stage, processing all inputs signals and fetching
319 * as many instructions as possible.
323 /** Checks all input signals and updates the status as necessary.
324 * @return: Returns if the status has changed due to input signals.
326 bool checkSignalsAndUpdate(ThreadID tid);
328 /** Does the actual fetching of instructions and passing them on to the
330 * @param status_change fetch() sets this variable if there was a status
331 * change (ie switching to IcacheMissStall).
333 void fetch(bool &status_change);
335 /** Align a PC to the start of an I-cache block. */
336 Addr icacheBlockAlignPC(Addr addr)
338 return (addr & ~(cacheBlkMask));
342 TheISA::Decoder *decoder[Impl::MaxThreads];
345 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
346 StaticInstPtr curMacroop, TheISA::PCState thisPC,
347 TheISA::PCState nextPC, bool trace);
349 /** Returns the appropriate thread to fetch, given the fetch policy. */
350 ThreadID getFetchingThread(FetchPriority &fetch_priority);
352 /** Returns the appropriate thread to fetch using a round robin policy. */
353 ThreadID roundRobin();
355 /** Returns the appropriate thread to fetch using the IQ count policy. */
358 /** Returns the appropriate thread to fetch using the LSQ count policy. */
361 /** Returns the appropriate thread to fetch using the branch count
363 ThreadID branchCount();
365 /** Pipeline the next I-cache access to the current one. */
366 void pipelineIcacheAccesses(ThreadID tid);
368 /** Profile the reasons of fetch stall. */
369 void profileStall(ThreadID tid);
372 /** Pointer to the O3CPU. */
375 /** Time buffer interface. */
376 TimeBuffer<TimeStruct> *timeBuffer;
378 /** Wire to get decode's information from backwards time buffer. */
379 typename TimeBuffer<TimeStruct>::wire fromDecode;
381 /** Wire to get rename's information from backwards time buffer. */
382 typename TimeBuffer<TimeStruct>::wire fromRename;
384 /** Wire to get iew's information from backwards time buffer. */
385 typename TimeBuffer<TimeStruct>::wire fromIEW;
387 /** Wire to get commit's information from backwards time buffer. */
388 typename TimeBuffer<TimeStruct>::wire fromCommit;
390 /** Internal fetch instruction queue. */
391 TimeBuffer<FetchStruct> *fetchQueue;
393 //Might be annoying how this name is different than the queue.
394 /** Wire used to write any information heading to decode. */
395 typename TimeBuffer<FetchStruct>::wire toDecode;
398 BPredUnit branchPred;
400 TheISA::PCState pc[Impl::MaxThreads];
402 Addr fetchOffset[Impl::MaxThreads];
404 StaticInstPtr macroop[Impl::MaxThreads];
406 /** Can the fetch stage redirect from an interrupt on this instruction? */
407 bool delayedCommit[Impl::MaxThreads];
409 /** Memory request used to access cache. */
410 RequestPtr memReq[Impl::MaxThreads];
412 /** Variable that tracks if fetch has written to the time buffer this
413 * cycle. Used to tell CPU if there is activity this cycle.
415 bool wroteToTimeBuffer;
417 /** Tracks how many instructions has been fetched this cycle. */
420 /** Source of possible stalls. */
428 /** Tracks which stages are telling fetch to stall. */
429 Stalls stalls[Impl::MaxThreads];
431 /** Decode to fetch delay, in ticks. */
432 unsigned decodeToFetchDelay;
434 /** Rename to fetch delay, in ticks. */
435 unsigned renameToFetchDelay;
437 /** IEW to fetch delay, in ticks. */
438 unsigned iewToFetchDelay;
440 /** Commit to fetch delay, in ticks. */
441 unsigned commitToFetchDelay;
443 /** The width of fetch in instructions. */
446 /** Is the cache blocked? If so no threads can access it. */
449 /** The packet that is waiting to be retried. */
452 /** The thread that is waiting on the cache to tell fetch to retry. */
455 /** Cache block size. */
458 /** Mask to get a cache block's address. */
461 /** The cache line being fetched. */
462 uint8_t *cacheData[Impl::MaxThreads];
464 /** The PC of the cacheline that has been loaded. */
465 Addr cacheDataPC[Impl::MaxThreads];
467 /** Whether or not the cache data is valid. */
468 bool cacheDataValid[Impl::MaxThreads];
470 /** Size of instructions. */
473 /** Icache stall statistics. */
474 Counter lastIcacheStall[Impl::MaxThreads];
476 /** List of Active Threads */
477 std::list<ThreadID> *activeThreads;
479 /** Number of threads. */
482 /** Number of threads that are actively fetching. */
483 ThreadID numFetchingThreads;
485 /** Thread ID being fetched. */
486 ThreadID threadFetched;
488 /** Checks if there is an interrupt pending. If there is, fetch
489 * must stop once it is not fetching PAL instructions.
491 bool interruptPending;
493 /** Is there a drain pending. */
496 /** Records if fetch is switched out. */
499 /** Set to true if a pipelined I-cache request should be issued. */
500 bool issuePipelinedIfetch[Impl::MaxThreads];
502 /** Event used to delay fault generation of translation faults */
503 FinishTranslationEvent finishTranslationEvent;
505 // @todo: Consider making these vectors and tracking on a per thread basis.
506 /** Stat for total number of cycles stalled due to an icache miss. */
507 Stats::Scalar icacheStallCycles;
508 /** Stat for total number of fetched instructions. */
509 Stats::Scalar fetchedInsts;
510 /** Total number of fetched branches. */
511 Stats::Scalar fetchedBranches;
512 /** Stat for total number of predicted branches. */
513 Stats::Scalar predictedBranches;
514 /** Stat for total number of cycles spent fetching. */
515 Stats::Scalar fetchCycles;
516 /** Stat for total number of cycles spent squashing. */
517 Stats::Scalar fetchSquashCycles;
518 /** Stat for total number of cycles spent waiting for translation */
519 Stats::Scalar fetchTlbCycles;
520 /** Stat for total number of cycles spent blocked due to other stages in
523 Stats::Scalar fetchIdleCycles;
524 /** Total number of cycles spent blocked. */
525 Stats::Scalar fetchBlockedCycles;
526 /** Total number of cycles spent in any other state. */
527 Stats::Scalar fetchMiscStallCycles;
528 /** Total number of cycles spent in waiting for drains. */
529 Stats::Scalar fetchPendingDrainCycles;
530 /** Total number of stall cycles caused by no active threads to run. */
531 Stats::Scalar fetchNoActiveThreadStallCycles;
532 /** Total number of stall cycles caused by pending traps. */
533 Stats::Scalar fetchPendingTrapStallCycles;
534 /** Total number of stall cycles caused by pending quiesce instructions. */
535 Stats::Scalar fetchPendingQuiesceStallCycles;
536 /** Total number of stall cycles caused by I-cache wait retrys. */
537 Stats::Scalar fetchIcacheWaitRetryStallCycles;
538 /** Stat for total number of fetched cache lines. */
539 Stats::Scalar fetchedCacheLines;
540 /** Total number of outstanding icache accesses that were dropped
543 Stats::Scalar fetchIcacheSquashes;
544 /** Total number of outstanding tlb accesses that were dropped
547 Stats::Scalar fetchTlbSquashes;
548 /** Distribution of number of instructions fetched each cycle. */
549 Stats::Distribution fetchNisnDist;
550 /** Rate of how often fetch was idle. */
551 Stats::Formula idleRate;
552 /** Number of branch fetches per cycle. */
553 Stats::Formula branchRate;
554 /** Number of instruction fetched per cycle. */
555 Stats::Formula fetchRate;
558 #endif //__CPU_O3_FETCH_HH__