src/cpu/o3/fetch.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  *          Korey Sewell
  42  */
  43
  44 #ifndef __CPU_O3_FETCH_HH__
  45 #define __CPU_O3_FETCH_HH__
  46
  47 #include "arch/predecoder.hh"
  48 #include "arch/utility.hh"
  49 #include "base/statistics.hh"
  50 #include "config/the_isa.hh"
  51 #include "cpu/pc_event.hh"
  52 #include "cpu/timebuf.hh"
  53 #include "cpu/translation.hh"
  54 #include "mem/packet.hh"
  55 #include "mem/port.hh"
  56 #include "sim/eventq.hh"
  57
  58 class DerivO3CPUParams;
  59
  60 /**
  61  * DefaultFetch class handles both single threaded and SMT fetch. Its
  62  * width is specified by the parameters; each cycle it tries to fetch
  63  * that many instructions. It supports using a branch predictor to
  64  * predict direction and targets.
  65  * It supports the idling functionality of the CPU by indicating to
  66  * the CPU when it is active and inactive.
  67  */
  68 template <class Impl>
  69 class DefaultFetch
  70 {
  71   public:
  72     /** Typedefs from Impl. */
  73     typedef typename Impl::CPUPol CPUPol;
  74     typedef typename Impl::DynInst DynInst;
  75     typedef typename Impl::DynInstPtr DynInstPtr;
  76     typedef typename Impl::O3CPU O3CPU;
  77
  78     /** Typedefs from the CPU policy. */
  79     typedef typename CPUPol::BPredUnit BPredUnit;
  80     typedef typename CPUPol::FetchStruct FetchStruct;
  81     typedef typename CPUPol::TimeStruct TimeStruct;
  82
  83     /** Typedefs from ISA. */
  84     typedef TheISA::MachInst MachInst;
  85     typedef TheISA::ExtMachInst ExtMachInst;
  86
  87     /** IcachePort class for DefaultFetch.  Handles doing the
  88      * communication with the cache/memory.
  89      */
  90     class IcachePort : public Port
  91     {
  92       protected:
  93         /** Pointer to fetch. */
  94         DefaultFetch<Impl> *fetch;
  95
  96       public:
  97         /** Default constructor. */
  98         IcachePort(DefaultFetch<Impl> *_fetch)
  99             : Port(_fetch->name() + "-iport", _fetch->cpu), fetch(_fetch)
 100         { }
 101
 102         bool snoopRangeSent;
 103
 104         virtual void setPeer(Port *port);
 105
 106       protected:
 107         /** Atomic version of receive.  Panics. */
 108         virtual Tick recvAtomic(PacketPtr pkt);
 109
 110         /** Functional version of receive.  Panics. */
 111         virtual void recvFunctional(PacketPtr pkt);
 112
 113         /** Receives status change.  Other than range changing, panics. */
 114         virtual void recvStatusChange(Status status);
 115
 116         /** Returns the address ranges of this device. */
 117         virtual void getDeviceAddressRanges(AddrRangeList &resp,
 118                                             bool &snoop)
 119         { resp.clear(); snoop = true; }
 120
 121         /** Timing version of receive.  Handles setting fetch to the
 122          * proper status to start fetching. */
 123         virtual bool recvTiming(PacketPtr pkt);
 124
 125         /** Handles doing a retry of a failed fetch. */
 126         virtual void recvRetry();
 127     };
 128
 129     class FetchTranslation : public BaseTLB::Translation
 130     {
 131       protected:
 132         DefaultFetch<Impl> *fetch;
 133
 134       public:
 135         FetchTranslation(DefaultFetch<Impl> *_fetch)
 136             : fetch(_fetch)
 137         {}
 138
 139         void
 140         markDelayed()
 141         {}
 142
 143         void
 144         finish(Fault fault, RequestPtr req, ThreadContext *tc,
 145                BaseTLB::Mode mode)
 146         {
 147             assert(mode == BaseTLB::Execute);
 148             fetch->finishTranslation(fault, req);
 149             delete this;
 150         }
 151     };
 152
 153   private:
 154     /* Event to delay delivery of a fetch translation result in case of
 155      * a fault and the nop to carry the fault cannot be generated
 156      * immediately */
 157     class FinishTranslationEvent : public Event
 158     {
 159       private:
 160         DefaultFetch<Impl> *fetch;
 161         Fault fault;
 162         RequestPtr req;
 163
 164       public:
 165         FinishTranslationEvent(DefaultFetch<Impl> *_fetch)
 166             : fetch(_fetch)
 167         {}
 168
 169         void setFault(Fault _fault)
 170         {
 171             fault = _fault;
 172         }
 173
 174         void setReq(RequestPtr _req)
 175         {
 176             req = _req;
 177         }
 178
 179         /** Process the delayed finish translation */
 180         void process()
 181         {
 182             assert(fetch->numInst < fetch->fetchWidth);
 183             fetch->finishTranslation(fault, req);
 184         }
 185
 186         const char *description() const
 187         {
 188             return "FullO3CPU FetchFinishTranslation";
 189         }
 190       };
 191
 192   public:
 193     /** Overall fetch status. Used to determine if the CPU can
 194      * deschedule itsef due to a lack of activity.
 195      */
 196     enum FetchStatus {
 197         Active,
 198         Inactive
 199     };
 200
 201     /** Individual thread status. */
 202     enum ThreadStatus {
 203         Running,
 204         Idle,
 205         Squashing,
 206         Blocked,
 207         Fetching,
 208         TrapPending,
 209         QuiescePending,
 210         SwitchOut,
 211         ItlbWait,
 212         IcacheWaitResponse,
 213         IcacheWaitRetry,
 214         IcacheAccessComplete,
 215         NoGoodAddr
 216     };
 217
 218     /** Fetching Policy, Add new policies here.*/
 219     enum FetchPriority {
 220         SingleThread,
 221         RoundRobin,
 222         Branch,
 223         IQ,
 224         LSQ
 225     };
 226
 227   private:
 228     /** Fetch status. */
 229     FetchStatus _status;
 230
 231     /** Per-thread status. */
 232     ThreadStatus fetchStatus[Impl::MaxThreads];
 233
 234     /** Fetch policy. */
 235     FetchPriority fetchPolicy;
 236
 237     /** List that has the threads organized by priority. */
 238     std::list<ThreadID> priorityList;
 239
 240   public:
 241     /** DefaultFetch constructor. */
 242     DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
 243
 244     /** Returns the name of fetch. */
 245     std::string name() const;
 246
 247     /** Registers statistics. */
 248     void regStats();
 249
 250     /** Returns the icache port. */
 251     Port *getIcachePort() { return icachePort; }
 252
 253     /** Sets the main backwards communication time buffer pointer. */
 254     void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
 255
 256     /** Sets pointer to list of active threads. */
 257     void setActiveThreads(std::list<ThreadID> *at_ptr);
 258
 259     /** Sets pointer to time buffer used to communicate to the next stage. */
 260     void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
 261
 262     /** Initialize stage. */
 263     void initStage();
 264
 265     /** Tells the fetch stage that the Icache is set. */
 266     void setIcache();
 267
 268     /** Processes cache completion event. */
 269     void processCacheCompletion(PacketPtr pkt);
 270
 271     /** Begins the drain of the fetch stage. */
 272     bool drain();
 273
 274     /** Resumes execution after a drain. */
 275     void resume();
 276
 277     /** Tells fetch stage to prepare to be switched out. */
 278     void switchOut();
 279
 280     /** Takes over from another CPU's thread. */
 281     void takeOverFrom();
 282
 283     /** Checks if the fetch stage is switched out. */
 284     bool isSwitchedOut() { return switchedOut; }
 285
 286     /** Tells fetch to wake up from a quiesce instruction. */
 287     void wakeFromQuiesce();
 288
 289   private:
 290     /** Changes the status of this stage to active, and indicates this
 291      * to the CPU.
 292      */
 293     inline void switchToActive();
 294
 295     /** Changes the status of this stage to inactive, and indicates
 296      * this to the CPU.
 297      */
 298     inline void switchToInactive();
 299
 300     /**
 301      * Looks up in the branch predictor to see if the next PC should be
 302      * either next PC+=MachInst or a branch target.
 303      * @param next_PC Next PC variable passed in by reference.  It is
 304      * expected to be set to the current PC; it will be updated with what
 305      * the next PC will be.
 306      * @param next_NPC Used for ISAs which use delay slots.
 307      * @return Whether or not a branch was predicted as taken.
 308      */
 309     bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc);
 310
 311     /**
 312      * Fetches the cache line that contains fetch_PC.  Returns any
 313      * fault that happened.  Puts the data into the class variable
 314      * cacheData.
 315      * @param vaddr The memory address that is being fetched from.
 316      * @param ret_fault The fault reference that will be set to the result of
 317      * the icache access.
 318      * @param tid Thread id.
 319      * @param pc The actual PC of the current instruction.
 320      * @return Any fault that occured.
 321      */
 322     bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
 323     void finishTranslation(Fault fault, RequestPtr mem_req);
 324
 325
 326     /** Check if an interrupt is pending and that we need to handle
 327      */
 328     bool
 329     checkInterrupt(Addr pc)
 330     {
 331         return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3)));
 332     }
 333
 334     /** Squashes a specific thread and resets the PC. */
 335     inline void doSquash(const TheISA::PCState &newPC,
 336                          const DynInstPtr squashInst, ThreadID tid);
 337
 338     /** Squashes a specific thread and resets the PC. Also tells the CPU to
 339      * remove any instructions between fetch and decode that should be sqaushed.
 340      */
 341     void squashFromDecode(const TheISA::PCState &newPC,
 342                           const DynInstPtr squashInst,
 343                           const InstSeqNum seq_num, ThreadID tid);
 344
 345     /** Checks if a thread is stalled. */
 346     bool checkStall(ThreadID tid) const;
 347
 348     /** Updates overall fetch stage status; to be called at the end of each
 349      * cycle. */
 350     FetchStatus updateFetchStatus();
 351
 352   public:
 353     /** Squashes a specific thread and resets the PC. Also tells the CPU to
 354      * remove any instructions that are not in the ROB. The source of this
 355      * squash should be the commit stage.
 356      */
 357     void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
 358                 DynInstPtr squashInst, ThreadID tid);
 359
 360     /** Ticks the fetch stage, processing all inputs signals and fetching
 361      * as many instructions as possible.
 362      */
 363     void tick();
 364
 365     /** Checks all input signals and updates the status as necessary.
 366      *  @return: Returns if the status has changed due to input signals.
 367      */
 368     bool checkSignalsAndUpdate(ThreadID tid);
 369
 370     /** Does the actual fetching of instructions and passing them on to the
 371      * next stage.
 372      * @param status_change fetch() sets this variable if there was a status
 373      * change (ie switching to IcacheMissStall).
 374      */
 375     void fetch(bool &status_change);
 376
 377     /** Align a PC to the start of an I-cache block. */
 378     Addr icacheBlockAlignPC(Addr addr)
 379     {
 380         return (addr & ~(cacheBlkMask));
 381     }
 382
 383   private:
 384     DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
 385                          StaticInstPtr curMacroop, TheISA::PCState thisPC,
 386                          TheISA::PCState nextPC, bool trace);
 387
 388     /** Handles retrying the fetch access. */
 389     void recvRetry();
 390
 391     /** Returns the appropriate thread to fetch, given the fetch policy. */
 392     ThreadID getFetchingThread(FetchPriority &fetch_priority);
 393
 394     /** Returns the appropriate thread to fetch using a round robin policy. */
 395     ThreadID roundRobin();
 396
 397     /** Returns the appropriate thread to fetch using the IQ count policy. */
 398     ThreadID iqCount();
 399
 400     /** Returns the appropriate thread to fetch using the LSQ count policy. */
 401     ThreadID lsqCount();
 402
 403     /** Returns the appropriate thread to fetch using the branch count
 404      * policy. */
 405     ThreadID branchCount();
 406
 407     /** Pipeline the next I-cache access to the current one. */
 408     void pipelineIcacheAccesses(ThreadID tid);
 409
 410     /** Profile the reasons of fetch stall. */
 411     void profileStall(ThreadID tid);
 412
 413   private:
 414     /** Pointer to the O3CPU. */
 415     O3CPU *cpu;
 416
 417     /** Time buffer interface. */
 418     TimeBuffer<TimeStruct> *timeBuffer;
 419
 420     /** Wire to get decode's information from backwards time buffer. */
 421     typename TimeBuffer<TimeStruct>::wire fromDecode;
 422
 423     /** Wire to get rename's information from backwards time buffer. */
 424     typename TimeBuffer<TimeStruct>::wire fromRename;
 425
 426     /** Wire to get iew's information from backwards time buffer. */
 427     typename TimeBuffer<TimeStruct>::wire fromIEW;
 428
 429     /** Wire to get commit's information from backwards time buffer. */
 430     typename TimeBuffer<TimeStruct>::wire fromCommit;
 431
 432     /** Internal fetch instruction queue. */
 433     TimeBuffer<FetchStruct> *fetchQueue;
 434
 435     //Might be annoying how this name is different than the queue.
 436     /** Wire used to write any information heading to decode. */
 437     typename TimeBuffer<FetchStruct>::wire toDecode;
 438
 439     /** Icache interface. */
 440     IcachePort *icachePort;
 441
 442     /** BPredUnit. */
 443     BPredUnit branchPred;
 444
 445     /** Predecoder. */
 446     TheISA::Predecoder predecoder;
 447
 448     TheISA::PCState pc[Impl::MaxThreads];
 449
 450     Addr fetchOffset[Impl::MaxThreads];
 451
 452     StaticInstPtr macroop[Impl::MaxThreads];
 453
 454     /** Can the fetch stage redirect from an interrupt on this instruction? */
 455     bool delayedCommit[Impl::MaxThreads];
 456
 457     /** Memory request used to access cache. */
 458     RequestPtr memReq[Impl::MaxThreads];
 459
 460     /** Variable that tracks if fetch has written to the time buffer this
 461      * cycle. Used to tell CPU if there is activity this cycle.
 462      */
 463     bool wroteToTimeBuffer;
 464
 465     /** Tracks how many instructions has been fetched this cycle. */
 466     int numInst;
 467
 468     /** Source of possible stalls. */
 469     struct Stalls {
 470         bool decode;
 471         bool rename;
 472         bool iew;
 473         bool commit;
 474     };
 475
 476     /** Tracks which stages are telling fetch to stall. */
 477     Stalls stalls[Impl::MaxThreads];
 478
 479     /** Decode to fetch delay, in ticks. */
 480     unsigned decodeToFetchDelay;
 481
 482     /** Rename to fetch delay, in ticks. */
 483     unsigned renameToFetchDelay;
 484
 485     /** IEW to fetch delay, in ticks. */
 486     unsigned iewToFetchDelay;
 487
 488     /** Commit to fetch delay, in ticks. */
 489     unsigned commitToFetchDelay;
 490
 491     /** The width of fetch in instructions. */
 492     unsigned fetchWidth;
 493
 494     /** Is the cache blocked?  If so no threads can access it. */
 495     bool cacheBlocked;
 496
 497     /** The packet that is waiting to be retried. */
 498     PacketPtr retryPkt;
 499
 500     /** The thread that is waiting on the cache to tell fetch to retry. */
 501     ThreadID retryTid;
 502
 503     /** Cache block size. */
 504     int cacheBlkSize;
 505
 506     /** Mask to get a cache block's address. */
 507     Addr cacheBlkMask;
 508
 509     /** The cache line being fetched. */
 510     uint8_t *cacheData[Impl::MaxThreads];
 511
 512     /** The PC of the cacheline that has been loaded. */
 513     Addr cacheDataPC[Impl::MaxThreads];
 514
 515     /** Whether or not the cache data is valid. */
 516     bool cacheDataValid[Impl::MaxThreads];
 517
 518     /** Size of instructions. */
 519     int instSize;
 520
 521     /** Icache stall statistics. */
 522     Counter lastIcacheStall[Impl::MaxThreads];
 523
 524     /** List of Active Threads */
 525     std::list<ThreadID> *activeThreads;
 526
 527     /** Number of threads. */
 528     ThreadID numThreads;
 529
 530     /** Number of threads that are actively fetching. */
 531     ThreadID numFetchingThreads;
 532
 533     /** Thread ID being fetched. */
 534     ThreadID threadFetched;
 535
 536     /** Checks if there is an interrupt pending.  If there is, fetch
 537      * must stop once it is not fetching PAL instructions.
 538      */
 539     bool interruptPending;
 540
 541     /** Is there a drain pending. */
 542     bool drainPending;
 543
 544     /** Records if fetch is switched out. */
 545     bool switchedOut;
 546
 547     /** Set to true if a pipelined I-cache request should be issued. */
 548     bool issuePipelinedIfetch[Impl::MaxThreads];
 549
 550     /** Event used to delay fault generation of translation faults */
 551     FinishTranslationEvent finishTranslationEvent;
 552
 553     // @todo: Consider making these vectors and tracking on a per thread basis.
 554     /** Stat for total number of cycles stalled due to an icache miss. */
 555     Stats::Scalar icacheStallCycles;
 556     /** Stat for total number of fetched instructions. */
 557     Stats::Scalar fetchedInsts;
 558     /** Total number of fetched branches. */
 559     Stats::Scalar fetchedBranches;
 560     /** Stat for total number of predicted branches. */
 561     Stats::Scalar predictedBranches;
 562     /** Stat for total number of cycles spent fetching. */
 563     Stats::Scalar fetchCycles;
 564     /** Stat for total number of cycles spent squashing. */
 565     Stats::Scalar fetchSquashCycles;
 566     /** Stat for total number of cycles spent waiting for translation */
 567     Stats::Scalar fetchTlbCycles;
 568     /** Stat for total number of cycles spent blocked due to other stages in
 569      * the pipeline.
 570      */
 571     Stats::Scalar fetchIdleCycles;
 572     /** Total number of cycles spent blocked. */
 573     Stats::Scalar fetchBlockedCycles;
 574     /** Total number of cycles spent in any other state. */
 575     Stats::Scalar fetchMiscStallCycles;
 576     /** Total number of cycles spent in waiting for drains. */
 577     Stats::Scalar fetchPendingDrainCycles;
 578     /** Total number of stall cycles caused by no active threads to run. */
 579     Stats::Scalar fetchNoActiveThreadStallCycles;
 580     /** Total number of stall cycles caused by pending traps. */
 581     Stats::Scalar fetchPendingTrapStallCycles;
 582     /** Total number of stall cycles caused by pending quiesce instructions. */
 583     Stats::Scalar fetchPendingQuiesceStallCycles;
 584     /** Total number of stall cycles caused by I-cache wait retrys. */
 585     Stats::Scalar fetchIcacheWaitRetryStallCycles;
 586     /** Stat for total number of fetched cache lines. */
 587     Stats::Scalar fetchedCacheLines;
 588     /** Total number of outstanding icache accesses that were dropped
 589      * due to a squash.
 590      */
 591     Stats::Scalar fetchIcacheSquashes;
 592     /** Total number of outstanding tlb accesses that were dropped
 593      * due to a squash.
 594      */
 595     Stats::Scalar fetchTlbSquashes;
 596     /** Distribution of number of instructions fetched each cycle. */
 597     Stats::Distribution fetchNisnDist;
 598     /** Rate of how often fetch was idle. */
 599     Stats::Formula idleRate;
 600     /** Number of branch fetches per cycle. */
 601     Stats::Formula branchRate;
 602     /** Number of instruction fetched per cycle. */
 603     Stats::Formula fetchRate;
 604 };
 605
 606 #endif //__CPU_O3_FETCH_HH__