src/cpu/o3/fetch.hh

   1 /*
   2  * Copyright (c) 2010-2012, 2014 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
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  20  * notice, this list of conditions and the following disclaimer;
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  26  * this software without specific prior written permission.
  27  *
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  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __CPU_O3_FETCH_HH__
  42 #define __CPU_O3_FETCH_HH__
  43
  44 #include "arch/decoder.hh"
  45 #include "arch/utility.hh"
  46 #include "base/statistics.hh"
  47 #include "config/the_isa.hh"
  48 #include "cpu/pc_event.hh"
  49 #include "cpu/pred/bpred_unit.hh"
  50 #include "cpu/timebuf.hh"
  51 #include "cpu/translation.hh"
  52 #include "enums/FetchPolicy.hh"
  53 #include "mem/packet.hh"
  54 #include "mem/port.hh"
  55 #include "sim/eventq.hh"
  56 #include "sim/probe/probe.hh"
  57
  58 struct DerivO3CPUParams;
  59 template <class Impl>
  60 class FullO3CPU;
  61
  62 /**
  63  * DefaultFetch class handles both single threaded and SMT fetch. Its
  64  * width is specified by the parameters; each cycle it tries to fetch
  65  * that many instructions. It supports using a branch predictor to
  66  * predict direction and targets.
  67  * It supports the idling functionality of the CPU by indicating to
  68  * the CPU when it is active and inactive.
  69  */
  70 template <class Impl>
  71 class DefaultFetch
  72 {
  73   public:
  74     /** Typedefs from Impl. */
  75     typedef typename Impl::CPUPol CPUPol;
  76     typedef typename Impl::DynInst DynInst;
  77     typedef typename Impl::DynInstPtr DynInstPtr;
  78     typedef typename Impl::O3CPU O3CPU;
  79
  80     /** Typedefs from the CPU policy. */
  81     typedef typename CPUPol::FetchStruct FetchStruct;
  82     typedef typename CPUPol::TimeStruct TimeStruct;
  83
  84     /** Typedefs from ISA. */
  85     typedef TheISA::MachInst MachInst;
  86
  87     /**
  88      * IcachePort class for instruction fetch.
  89      */
  90     class IcachePort : public MasterPort
  91     {
  92       protected:
  93         /** Pointer to fetch. */
  94         DefaultFetch<Impl> *fetch;
  95
  96       public:
  97         /** Default constructor. */
  98         IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
  99             : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
 100         { }
 101
 102       protected:
 103
 104         /** Timing version of receive.  Handles setting fetch to the
 105          * proper status to start fetching. */
 106         virtual bool recvTimingResp(PacketPtr pkt);
 107
 108         /** Handles doing a retry of a failed fetch. */
 109         virtual void recvReqRetry();
 110     };
 111
 112     class FetchTranslation : public BaseTLB::Translation
 113     {
 114       protected:
 115         DefaultFetch<Impl> *fetch;
 116
 117       public:
 118         FetchTranslation(DefaultFetch<Impl> *_fetch)
 119             : fetch(_fetch)
 120         {}
 121
 122         void
 123         markDelayed()
 124         {}
 125
 126         void
 127         finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
 128                BaseTLB::Mode mode)
 129         {
 130             assert(mode == BaseTLB::Execute);
 131             fetch->finishTranslation(fault, req);
 132             delete this;
 133         }
 134     };
 135
 136   private:
 137     /* Event to delay delivery of a fetch translation result in case of
 138      * a fault and the nop to carry the fault cannot be generated
 139      * immediately */
 140     class FinishTranslationEvent : public Event
 141     {
 142       private:
 143         DefaultFetch<Impl> *fetch;
 144         Fault fault;
 145         RequestPtr req;
 146
 147       public:
 148         FinishTranslationEvent(DefaultFetch<Impl> *_fetch)
 149             : fetch(_fetch), req(nullptr)
 150         {}
 151
 152         void setFault(Fault _fault)
 153         {
 154             fault = _fault;
 155         }
 156
 157         void setReq(const RequestPtr &_req)
 158         {
 159             req = _req;
 160         }
 161
 162         /** Process the delayed finish translation */
 163         void process()
 164         {
 165             assert(fetch->numInst < fetch->fetchWidth);
 166             fetch->finishTranslation(fault, req);
 167         }
 168
 169         const char *description() const
 170         {
 171             return "FullO3CPU FetchFinishTranslation";
 172         }
 173       };
 174
 175   public:
 176     /** Overall fetch status. Used to determine if the CPU can
 177      * deschedule itsef due to a lack of activity.
 178      */
 179     enum FetchStatus {
 180         Active,
 181         Inactive
 182     };
 183
 184     /** Individual thread status. */
 185     enum ThreadStatus {
 186         Running,
 187         Idle,
 188         Squashing,
 189         Blocked,
 190         Fetching,
 191         TrapPending,
 192         QuiescePending,
 193         ItlbWait,
 194         IcacheWaitResponse,
 195         IcacheWaitRetry,
 196         IcacheAccessComplete,
 197         NoGoodAddr
 198     };
 199
 200   private:
 201     /** Fetch status. */
 202     FetchStatus _status;
 203
 204     /** Per-thread status. */
 205     ThreadStatus fetchStatus[Impl::MaxThreads];
 206
 207     /** Fetch policy. */
 208     FetchPolicy fetchPolicy;
 209
 210     /** List that has the threads organized by priority. */
 211     std::list<ThreadID> priorityList;
 212
 213     /** Probe points. */
 214     ProbePointArg<DynInstPtr> *ppFetch;
 215     /** To probe when a fetch request is successfully sent. */
 216     ProbePointArg<RequestPtr> *ppFetchRequestSent;
 217
 218   public:
 219     /** DefaultFetch constructor. */
 220     DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
 221
 222     /** Returns the name of fetch. */
 223     std::string name() const;
 224
 225     /** Registers statistics. */
 226     void regStats();
 227
 228     /** Registers probes. */
 229     void regProbePoints();
 230
 231     /** Sets the main backwards communication time buffer pointer. */
 232     void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
 233
 234     /** Sets pointer to list of active threads. */
 235     void setActiveThreads(std::list<ThreadID> *at_ptr);
 236
 237     /** Sets pointer to time buffer used to communicate to the next stage. */
 238     void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
 239
 240     /** Initialize stage. */
 241     void startupStage();
 242
 243     /** Clear all thread-specific states*/
 244     void clearStates(ThreadID tid);
 245
 246     /** Handles retrying the fetch access. */
 247     void recvReqRetry();
 248
 249     /** Processes cache completion event. */
 250     void processCacheCompletion(PacketPtr pkt);
 251
 252     /** Resume after a drain. */
 253     void drainResume();
 254
 255     /** Perform sanity checks after a drain. */
 256     void drainSanityCheck() const;
 257
 258     /** Has the stage drained? */
 259     bool isDrained() const;
 260
 261     /** Takes over from another CPU's thread. */
 262     void takeOverFrom();
 263
 264     /**
 265      * Stall the fetch stage after reaching a safe drain point.
 266      *
 267      * The CPU uses this method to stop fetching instructions from a
 268      * thread that has been drained. The drain stall is different from
 269      * all other stalls in that it is signaled instantly from the
 270      * commit stage (without the normal communication delay) when it
 271      * has reached a safe point to drain from.
 272      */
 273     void drainStall(ThreadID tid);
 274
 275     /** Tells fetch to wake up from a quiesce instruction. */
 276     void wakeFromQuiesce();
 277
 278     /** For priority-based fetch policies, need to keep update priorityList */
 279     void deactivateThread(ThreadID tid);
 280   private:
 281     /** Reset this pipeline stage */
 282     void resetStage();
 283
 284     /** Changes the status of this stage to active, and indicates this
 285      * to the CPU.
 286      */
 287     inline void switchToActive();
 288
 289     /** Changes the status of this stage to inactive, and indicates
 290      * this to the CPU.
 291      */
 292     inline void switchToInactive();
 293
 294     /**
 295      * Looks up in the branch predictor to see if the next PC should be
 296      * either next PC+=MachInst or a branch target.
 297      * @param next_PC Next PC variable passed in by reference.  It is
 298      * expected to be set to the current PC; it will be updated with what
 299      * the next PC will be.
 300      * @param next_NPC Used for ISAs which use delay slots.
 301      * @return Whether or not a branch was predicted as taken.
 302      */
 303     bool lookupAndUpdateNextPC(const DynInstPtr &inst, TheISA::PCState &pc);
 304
 305     /**
 306      * Fetches the cache line that contains the fetch PC.  Returns any
 307      * fault that happened.  Puts the data into the class variable
 308      * fetchBuffer, which may not hold the entire fetched cache line.
 309      * @param vaddr The memory address that is being fetched from.
 310      * @param ret_fault The fault reference that will be set to the result of
 311      * the icache access.
 312      * @param tid Thread id.
 313      * @param pc The actual PC of the current instruction.
 314      * @return Any fault that occured.
 315      */
 316     bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
 317     void finishTranslation(const Fault &fault, const RequestPtr &mem_req);
 318
 319
 320     /** Check if an interrupt is pending and that we need to handle
 321      */
 322     bool
 323     checkInterrupt(Addr pc)
 324     {
 325         return interruptPending;
 326     }
 327
 328     /** Squashes a specific thread and resets the PC. */
 329     inline void doSquash(const TheISA::PCState &newPC,
 330                          const DynInstPtr squashInst, ThreadID tid);
 331
 332     /** Squashes a specific thread and resets the PC. Also tells the CPU to
 333      * remove any instructions between fetch and decode that should be sqaushed.
 334      */
 335     void squashFromDecode(const TheISA::PCState &newPC,
 336                           const DynInstPtr squashInst,
 337                           const InstSeqNum seq_num, ThreadID tid);
 338
 339     /** Checks if a thread is stalled. */
 340     bool checkStall(ThreadID tid) const;
 341
 342     /** Updates overall fetch stage status; to be called at the end of each
 343      * cycle. */
 344     FetchStatus updateFetchStatus();
 345
 346   public:
 347     /** Squashes a specific thread and resets the PC. Also tells the CPU to
 348      * remove any instructions that are not in the ROB. The source of this
 349      * squash should be the commit stage.
 350      */
 351     void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
 352                 DynInstPtr squashInst, ThreadID tid);
 353
 354     /** Ticks the fetch stage, processing all inputs signals and fetching
 355      * as many instructions as possible.
 356      */
 357     void tick();
 358
 359     /** Checks all input signals and updates the status as necessary.
 360      *  @return: Returns if the status has changed due to input signals.
 361      */
 362     bool checkSignalsAndUpdate(ThreadID tid);
 363
 364     /** Does the actual fetching of instructions and passing them on to the
 365      * next stage.
 366      * @param status_change fetch() sets this variable if there was a status
 367      * change (ie switching to IcacheMissStall).
 368      */
 369     void fetch(bool &status_change);
 370
 371     /** Align a PC to the start of a fetch buffer block. */
 372     Addr fetchBufferAlignPC(Addr addr)
 373     {
 374         return (addr & ~(fetchBufferMask));
 375     }
 376
 377     /** The decoder. */
 378     TheISA::Decoder *decoder[Impl::MaxThreads];
 379
 380     MasterPort &getInstPort() { return icachePort; }
 381
 382   private:
 383     DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
 384                          StaticInstPtr curMacroop, TheISA::PCState thisPC,
 385                          TheISA::PCState nextPC, bool trace);
 386
 387     /** Returns the appropriate thread to fetch, given the fetch policy. */
 388     ThreadID getFetchingThread();
 389
 390     /** Returns the appropriate thread to fetch using a round robin policy. */
 391     ThreadID roundRobin();
 392
 393     /** Returns the appropriate thread to fetch using the IQ count policy. */
 394     ThreadID iqCount();
 395
 396     /** Returns the appropriate thread to fetch using the LSQ count policy. */
 397     ThreadID lsqCount();
 398
 399     /** Returns the appropriate thread to fetch using the branch count
 400      * policy. */
 401     ThreadID branchCount();
 402
 403     /** Pipeline the next I-cache access to the current one. */
 404     void pipelineIcacheAccesses(ThreadID tid);
 405
 406     /** Profile the reasons of fetch stall. */
 407     void profileStall(ThreadID tid);
 408
 409   private:
 410     /** Pointer to the O3CPU. */
 411     O3CPU *cpu;
 412
 413     /** Time buffer interface. */
 414     TimeBuffer<TimeStruct> *timeBuffer;
 415
 416     /** Wire to get decode's information from backwards time buffer. */
 417     typename TimeBuffer<TimeStruct>::wire fromDecode;
 418
 419     /** Wire to get rename's information from backwards time buffer. */
 420     typename TimeBuffer<TimeStruct>::wire fromRename;
 421
 422     /** Wire to get iew's information from backwards time buffer. */
 423     typename TimeBuffer<TimeStruct>::wire fromIEW;
 424
 425     /** Wire to get commit's information from backwards time buffer. */
 426     typename TimeBuffer<TimeStruct>::wire fromCommit;
 427
 428     //Might be annoying how this name is different than the queue.
 429     /** Wire used to write any information heading to decode. */
 430     typename TimeBuffer<FetchStruct>::wire toDecode;
 431
 432     /** BPredUnit. */
 433     BPredUnit *branchPred;
 434
 435     TheISA::PCState pc[Impl::MaxThreads];
 436
 437     Addr fetchOffset[Impl::MaxThreads];
 438
 439     StaticInstPtr macroop[Impl::MaxThreads];
 440
 441     /** Can the fetch stage redirect from an interrupt on this instruction? */
 442     bool delayedCommit[Impl::MaxThreads];
 443
 444     /** Memory request used to access cache. */
 445     RequestPtr memReq[Impl::MaxThreads];
 446
 447     /** Variable that tracks if fetch has written to the time buffer this
 448      * cycle. Used to tell CPU if there is activity this cycle.
 449      */
 450     bool wroteToTimeBuffer;
 451
 452     /** Tracks how many instructions has been fetched this cycle. */
 453     int numInst;
 454
 455     /** Source of possible stalls. */
 456     struct Stalls {
 457         bool decode;
 458         bool drain;
 459     };
 460
 461     /** Tracks which stages are telling fetch to stall. */
 462     Stalls stalls[Impl::MaxThreads];
 463
 464     /** Decode to fetch delay. */
 465     Cycles decodeToFetchDelay;
 466
 467     /** Rename to fetch delay. */
 468     Cycles renameToFetchDelay;
 469
 470     /** IEW to fetch delay. */
 471     Cycles iewToFetchDelay;
 472
 473     /** Commit to fetch delay. */
 474     Cycles commitToFetchDelay;
 475
 476     /** The width of fetch in instructions. */
 477     unsigned fetchWidth;
 478
 479     /** The width of decode in instructions. */
 480     unsigned decodeWidth;
 481
 482     /** Is the cache blocked?  If so no threads can access it. */
 483     bool cacheBlocked;
 484
 485     /** The packet that is waiting to be retried. */
 486     PacketPtr retryPkt;
 487
 488     /** The thread that is waiting on the cache to tell fetch to retry. */
 489     ThreadID retryTid;
 490
 491     /** Cache block size. */
 492     unsigned int cacheBlkSize;
 493
 494     /** The size of the fetch buffer in bytes. The fetch buffer
 495      *  itself may be smaller than a cache line.
 496      */
 497     unsigned fetchBufferSize;
 498
 499     /** Mask to align a fetch address to a fetch buffer boundary. */
 500     Addr fetchBufferMask;
 501
 502     /** The fetch data that is being fetched and buffered. */
 503     uint8_t *fetchBuffer[Impl::MaxThreads];
 504
 505     /** The PC of the first instruction loaded into the fetch buffer. */
 506     Addr fetchBufferPC[Impl::MaxThreads];
 507
 508     /** The size of the fetch queue in micro-ops */
 509     unsigned fetchQueueSize;
 510
 511     /** Queue of fetched instructions. Per-thread to prevent HoL blocking. */
 512     std::deque<DynInstPtr> fetchQueue[Impl::MaxThreads];
 513
 514     /** Whether or not the fetch buffer data is valid. */
 515     bool fetchBufferValid[Impl::MaxThreads];
 516
 517     /** Size of instructions. */
 518     int instSize;
 519
 520     /** Icache stall statistics. */
 521     Counter lastIcacheStall[Impl::MaxThreads];
 522
 523     /** List of Active Threads */
 524     std::list<ThreadID> *activeThreads;
 525
 526     /** Number of threads. */
 527     ThreadID numThreads;
 528
 529     /** Number of threads that are actively fetching. */
 530     ThreadID numFetchingThreads;
 531
 532     /** Thread ID being fetched. */
 533     ThreadID threadFetched;
 534
 535     /** Checks if there is an interrupt pending.  If there is, fetch
 536      * must stop once it is not fetching PAL instructions.
 537      */
 538     bool interruptPending;
 539
 540     /** Instruction port. Note that it has to appear after the fetch stage. */
 541     IcachePort icachePort;
 542
 543     /** Set to true if a pipelined I-cache request should be issued. */
 544     bool issuePipelinedIfetch[Impl::MaxThreads];
 545
 546     /** Event used to delay fault generation of translation faults */
 547     FinishTranslationEvent finishTranslationEvent;
 548
 549     // @todo: Consider making these vectors and tracking on a per thread basis.
 550     /** Stat for total number of cycles stalled due to an icache miss. */
 551     Stats::Scalar icacheStallCycles;
 552     /** Stat for total number of fetched instructions. */
 553     Stats::Scalar fetchedInsts;
 554     /** Total number of fetched branches. */
 555     Stats::Scalar fetchedBranches;
 556     /** Stat for total number of predicted branches. */
 557     Stats::Scalar predictedBranches;
 558     /** Stat for total number of cycles spent fetching. */
 559     Stats::Scalar fetchCycles;
 560     /** Stat for total number of cycles spent squashing. */
 561     Stats::Scalar fetchSquashCycles;
 562     /** Stat for total number of cycles spent waiting for translation */
 563     Stats::Scalar fetchTlbCycles;
 564     /** Stat for total number of cycles spent blocked due to other stages in
 565      * the pipeline.
 566      */
 567     Stats::Scalar fetchIdleCycles;
 568     /** Total number of cycles spent blocked. */
 569     Stats::Scalar fetchBlockedCycles;
 570     /** Total number of cycles spent in any other state. */
 571     Stats::Scalar fetchMiscStallCycles;
 572     /** Total number of cycles spent in waiting for drains. */
 573     Stats::Scalar fetchPendingDrainCycles;
 574     /** Total number of stall cycles caused by no active threads to run. */
 575     Stats::Scalar fetchNoActiveThreadStallCycles;
 576     /** Total number of stall cycles caused by pending traps. */
 577     Stats::Scalar fetchPendingTrapStallCycles;
 578     /** Total number of stall cycles caused by pending quiesce instructions. */
 579     Stats::Scalar fetchPendingQuiesceStallCycles;
 580     /** Total number of stall cycles caused by I-cache wait retrys. */
 581     Stats::Scalar fetchIcacheWaitRetryStallCycles;
 582     /** Stat for total number of fetched cache lines. */
 583     Stats::Scalar fetchedCacheLines;
 584     /** Total number of outstanding icache accesses that were dropped
 585      * due to a squash.
 586      */
 587     Stats::Scalar fetchIcacheSquashes;
 588     /** Total number of outstanding tlb accesses that were dropped
 589      * due to a squash.
 590      */
 591     Stats::Scalar fetchTlbSquashes;
 592     /** Distribution of number of instructions fetched each cycle. */
 593     Stats::Distribution fetchNisnDist;
 594     /** Rate of how often fetch was idle. */
 595     Stats::Formula idleRate;
 596     /** Number of branch fetches per cycle. */
 597     Stats::Formula branchRate;
 598     /** Number of instruction fetched per cycle. */
 599     Stats::Formula fetchRate;
 600 };
 601
 602 #endif //__CPU_O3_FETCH_HH__