src/cpu/o3/fetch.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Korey Sewell
  30  */
  31
  32 #ifndef __CPU_O3_FETCH_HH__
  33 #define __CPU_O3_FETCH_HH__
  34
  35 #include "arch/utility.hh"
  36 #include "base/statistics.hh"
  37 #include "base/timebuf.hh"
  38 #include "cpu/pc_event.hh"
  39 #include "mem/packet_impl.hh"
  40 #include "mem/port.hh"
  41 #include "sim/eventq.hh"
  42
  43 /**
  44  * DefaultFetch class handles both single threaded and SMT fetch. Its
  45  * width is specified by the parameters; each cycle it tries to fetch
  46  * that many instructions. It supports using a branch predictor to
  47  * predict direction and targets.
  48  * It supports the idling functionality of the CPU by indicating to
  49  * the CPU when it is active and inactive.
  50  */
  51 template <class Impl>
  52 class DefaultFetch
  53 {
  54   public:
  55     /** Typedefs from Impl. */
  56     typedef typename Impl::CPUPol CPUPol;
  57     typedef typename Impl::DynInst DynInst;
  58     typedef typename Impl::DynInstPtr DynInstPtr;
  59     typedef typename Impl::O3CPU O3CPU;
  60     typedef typename Impl::Params Params;
  61
  62     /** Typedefs from the CPU policy. */
  63     typedef typename CPUPol::BPredUnit BPredUnit;
  64     typedef typename CPUPol::FetchStruct FetchStruct;
  65     typedef typename CPUPol::TimeStruct TimeStruct;
  66
  67     /** Typedefs from ISA. */
  68     typedef TheISA::MachInst MachInst;
  69     typedef TheISA::ExtMachInst ExtMachInst;
  70
  71     /** IcachePort class for DefaultFetch.  Handles doing the
  72      * communication with the cache/memory.
  73      */
  74     class IcachePort : public Port
  75     {
  76       protected:
  77         /** Pointer to fetch. */
  78         DefaultFetch<Impl> *fetch;
  79
  80       public:
  81         /** Default constructor. */
  82         IcachePort(DefaultFetch<Impl> *_fetch)
  83             : Port(_fetch->name() + "-iport"), fetch(_fetch)
  84         { }
  85
  86       protected:
  87         /** Atomic version of receive.  Panics. */
  88         virtual Tick recvAtomic(PacketPtr pkt);
  89
  90         /** Functional version of receive.  Panics. */
  91         virtual void recvFunctional(PacketPtr pkt);
  92
  93         /** Receives status change.  Other than range changing, panics. */
  94         virtual void recvStatusChange(Status status);
  95
  96         /** Returns the address ranges of this device. */
  97         virtual void getDeviceAddressRanges(AddrRangeList &resp,
  98                                             AddrRangeList &snoop)
  99         { resp.clear(); snoop.clear(); }
 100
 101         /** Timing version of receive.  Handles setting fetch to the
 102          * proper status to start fetching. */
 103         virtual bool recvTiming(PacketPtr pkt);
 104
 105         /** Handles doing a retry of a failed fetch. */
 106         virtual void recvRetry();
 107     };
 108
 109   public:
 110     /** Overall fetch status. Used to determine if the CPU can
 111      * deschedule itsef due to a lack of activity.
 112      */
 113     enum FetchStatus {
 114         Active,
 115         Inactive
 116     };
 117
 118     /** Individual thread status. */
 119     enum ThreadStatus {
 120         Running,
 121         Idle,
 122         Squashing,
 123         Blocked,
 124         Fetching,
 125         TrapPending,
 126         QuiescePending,
 127         SwitchOut,
 128         IcacheWaitResponse,
 129         IcacheWaitRetry,
 130         IcacheAccessComplete
 131     };
 132
 133     /** Fetching Policy, Add new policies here.*/
 134     enum FetchPriority {
 135         SingleThread,
 136         RoundRobin,
 137         Branch,
 138         IQ,
 139         LSQ
 140     };
 141
 142   private:
 143     /** Fetch status. */
 144     FetchStatus _status;
 145
 146     /** Per-thread status. */
 147     ThreadStatus fetchStatus[Impl::MaxThreads];
 148
 149     /** Fetch policy. */
 150     FetchPriority fetchPolicy;
 151
 152     /** List that has the threads organized by priority. */
 153     std::list<unsigned> priorityList;
 154
 155   public:
 156     /** DefaultFetch constructor. */
 157     DefaultFetch(Params *params);
 158
 159     /** Returns the name of fetch. */
 160     std::string name() const;
 161
 162     /** Registers statistics. */
 163     void regStats();
 164
 165     /** Returns the icache port. */
 166     Port *getIcachePort() { return icachePort; }
 167
 168     /** Sets CPU pointer. */
 169     void setCPU(O3CPU *cpu_ptr);
 170
 171     /** Sets the main backwards communication time buffer pointer. */
 172     void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
 173
 174     /** Sets pointer to list of active threads. */
 175     void setActiveThreads(std::list<unsigned> *at_ptr);
 176
 177     /** Sets pointer to time buffer used to communicate to the next stage. */
 178     void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
 179
 180     /** Initialize stage. */
 181     void initStage();
 182
 183     /** Processes cache completion event. */
 184     void processCacheCompletion(PacketPtr pkt);
 185
 186     /** Begins the drain of the fetch stage. */
 187     bool drain();
 188
 189     /** Resumes execution after a drain. */
 190     void resume();
 191
 192     /** Tells fetch stage to prepare to be switched out. */
 193     void switchOut();
 194
 195     /** Takes over from another CPU's thread. */
 196     void takeOverFrom();
 197
 198     /** Checks if the fetch stage is switched out. */
 199     bool isSwitchedOut() { return switchedOut; }
 200
 201     /** Tells fetch to wake up from a quiesce instruction. */
 202     void wakeFromQuiesce();
 203
 204   private:
 205     /** Changes the status of this stage to active, and indicates this
 206      * to the CPU.
 207      */
 208     inline void switchToActive();
 209
 210     /** Changes the status of this stage to inactive, and indicates
 211      * this to the CPU.
 212      */
 213     inline void switchToInactive();
 214
 215     /**
 216      * Looks up in the branch predictor to see if the next PC should be
 217      * either next PC+=MachInst or a branch target.
 218      * @param next_PC Next PC variable passed in by reference.  It is
 219      * expected to be set to the current PC; it will be updated with what
 220      * the next PC will be.
 221      * @return Whether or not a branch was predicted as taken.
 222      */
 223     bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC);
 224
 225     /**
 226      * Fetches the cache line that contains fetch_PC.  Returns any
 227      * fault that happened.  Puts the data into the class variable
 228      * cacheData.
 229      * @param fetch_PC The PC address that is being fetched from.
 230      * @param ret_fault The fault reference that will be set to the result of
 231      * the icache access.
 232      * @param tid Thread id.
 233      * @return Any fault that occured.
 234      */
 235     bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
 236
 237     /** Squashes a specific thread and resets the PC. */
 238     inline void doSquash(const Addr &new_PC, unsigned tid);
 239
 240     /** Squashes a specific thread and resets the PC. Also tells the CPU to
 241      * remove any instructions between fetch and decode that should be sqaushed.
 242      */
 243     void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
 244                           unsigned tid);
 245
 246     /** Checks if a thread is stalled. */
 247     bool checkStall(unsigned tid) const;
 248
 249     /** Updates overall fetch stage status; to be called at the end of each
 250      * cycle. */
 251     FetchStatus updateFetchStatus();
 252
 253   public:
 254     /** Squashes a specific thread and resets the PC. Also tells the CPU to
 255      * remove any instructions that are not in the ROB. The source of this
 256      * squash should be the commit stage.
 257      */
 258     void squash(const Addr &new_PC, unsigned tid);
 259
 260     /** Ticks the fetch stage, processing all inputs signals and fetching
 261      * as many instructions as possible.
 262      */
 263     void tick();
 264
 265     /** Checks all input signals and updates the status as necessary.
 266      *  @return: Returns if the status has changed due to input signals.
 267      */
 268     bool checkSignalsAndUpdate(unsigned tid);
 269
 270     /** Does the actual fetching of instructions and passing them on to the
 271      * next stage.
 272      * @param status_change fetch() sets this variable if there was a status
 273      * change (ie switching to IcacheMissStall).
 274      */
 275     void fetch(bool &status_change);
 276
 277     /** Align a PC to the start of an I-cache block. */
 278     Addr icacheBlockAlignPC(Addr addr)
 279     {
 280         addr = TheISA::realPCToFetchPC(addr);
 281         return (addr & ~(cacheBlkMask));
 282     }
 283
 284   private:
 285     /** Handles retrying the fetch access. */
 286     void recvRetry();
 287
 288     /** Returns the appropriate thread to fetch, given the fetch policy. */
 289     int getFetchingThread(FetchPriority &fetch_priority);
 290
 291     /** Returns the appropriate thread to fetch using a round robin policy. */
 292     int roundRobin();
 293
 294     /** Returns the appropriate thread to fetch using the IQ count policy. */
 295     int iqCount();
 296
 297     /** Returns the appropriate thread to fetch using the LSQ count policy. */
 298     int lsqCount();
 299
 300     /** Returns the appropriate thread to fetch using the branch count policy. */
 301     int branchCount();
 302
 303   private:
 304     /** Pointer to the O3CPU. */
 305     O3CPU *cpu;
 306
 307     /** Time buffer interface. */
 308     TimeBuffer<TimeStruct> *timeBuffer;
 309
 310     /** Wire to get decode's information from backwards time buffer. */
 311     typename TimeBuffer<TimeStruct>::wire fromDecode;
 312
 313     /** Wire to get rename's information from backwards time buffer. */
 314     typename TimeBuffer<TimeStruct>::wire fromRename;
 315
 316     /** Wire to get iew's information from backwards time buffer. */
 317     typename TimeBuffer<TimeStruct>::wire fromIEW;
 318
 319     /** Wire to get commit's information from backwards time buffer. */
 320     typename TimeBuffer<TimeStruct>::wire fromCommit;
 321
 322     /** Internal fetch instruction queue. */
 323     TimeBuffer<FetchStruct> *fetchQueue;
 324
 325     //Might be annoying how this name is different than the queue.
 326     /** Wire used to write any information heading to decode. */
 327     typename TimeBuffer<FetchStruct>::wire toDecode;
 328
 329     MemObject *mem;
 330
 331     /** Icache interface. */
 332     IcachePort *icachePort;
 333
 334     /** BPredUnit. */
 335     BPredUnit branchPred;
 336
 337     /** Per-thread fetch PC. */
 338     Addr PC[Impl::MaxThreads];
 339
 340     /** Per-thread next PC. */
 341     Addr nextPC[Impl::MaxThreads];
 342
 343 #if THE_ISA != ALPHA_ISA
 344     /** Per-thread next Next PC.
 345      *  This is not a real register but is used for
 346      *  architectures that use a branch-delay slot.
 347      *  (such as MIPS or Sparc)
 348      */
 349     Addr nextNPC[Impl::MaxThreads];
 350 #endif
 351
 352     /** Memory request used to access cache. */
 353     RequestPtr memReq[Impl::MaxThreads];
 354
 355     /** Variable that tracks if fetch has written to the time buffer this
 356      * cycle. Used to tell CPU if there is activity this cycle.
 357      */
 358     bool wroteToTimeBuffer;
 359
 360     /** Tracks how many instructions has been fetched this cycle. */
 361     int numInst;
 362
 363     /** Source of possible stalls. */
 364     struct Stalls {
 365         bool decode;
 366         bool rename;
 367         bool iew;
 368         bool commit;
 369     };
 370
 371     /** Tracks which stages are telling fetch to stall. */
 372     Stalls stalls[Impl::MaxThreads];
 373
 374     /** Decode to fetch delay, in ticks. */
 375     unsigned decodeToFetchDelay;
 376
 377     /** Rename to fetch delay, in ticks. */
 378     unsigned renameToFetchDelay;
 379
 380     /** IEW to fetch delay, in ticks. */
 381     unsigned iewToFetchDelay;
 382
 383     /** Commit to fetch delay, in ticks. */
 384     unsigned commitToFetchDelay;
 385
 386     /** The width of fetch in instructions. */
 387     unsigned fetchWidth;
 388
 389     /** Is the cache blocked?  If so no threads can access it. */
 390     bool cacheBlocked;
 391
 392     /** The packet that is waiting to be retried. */
 393     PacketPtr retryPkt;
 394
 395     /** The thread that is waiting on the cache to tell fetch to retry. */
 396     int retryTid;
 397
 398     /** Cache block size. */
 399     int cacheBlkSize;
 400
 401     /** Mask to get a cache block's address. */
 402     Addr cacheBlkMask;
 403
 404     /** The cache line being fetched. */
 405     uint8_t *cacheData[Impl::MaxThreads];
 406
 407     /** Size of instructions. */
 408     int instSize;
 409
 410     /** Icache stall statistics. */
 411     Counter lastIcacheStall[Impl::MaxThreads];
 412
 413     /** List of Active Threads */
 414     std::list<unsigned> *activeThreads;
 415
 416     /** Number of threads. */
 417     unsigned numThreads;
 418
 419     /** Number of threads that are actively fetching. */
 420     unsigned numFetchingThreads;
 421
 422     /** Thread ID being fetched. */
 423     int threadFetched;
 424
 425     /** Checks if there is an interrupt pending.  If there is, fetch
 426      * must stop once it is not fetching PAL instructions.
 427      */
 428     bool interruptPending;
 429
 430     /** Is there a drain pending. */
 431     bool drainPending;
 432
 433     /** Records if fetch is switched out. */
 434     bool switchedOut;
 435
 436     // @todo: Consider making these vectors and tracking on a per thread basis.
 437     /** Stat for total number of cycles stalled due to an icache miss. */
 438     Stats::Scalar<> icacheStallCycles;
 439     /** Stat for total number of fetched instructions. */
 440     Stats::Scalar<> fetchedInsts;
 441     /** Total number of fetched branches. */
 442     Stats::Scalar<> fetchedBranches;
 443     /** Stat for total number of predicted branches. */
 444     Stats::Scalar<> predictedBranches;
 445     /** Stat for total number of cycles spent fetching. */
 446     Stats::Scalar<> fetchCycles;
 447     /** Stat for total number of cycles spent squashing. */
 448     Stats::Scalar<> fetchSquashCycles;
 449     /** Stat for total number of cycles spent blocked due to other stages in
 450      * the pipeline.
 451      */
 452     Stats::Scalar<> fetchIdleCycles;
 453     /** Total number of cycles spent blocked. */
 454     Stats::Scalar<> fetchBlockedCycles;
 455     /** Total number of cycles spent in any other state. */
 456     Stats::Scalar<> fetchMiscStallCycles;
 457     /** Stat for total number of fetched cache lines. */
 458     Stats::Scalar<> fetchedCacheLines;
 459     /** Total number of outstanding icache accesses that were dropped
 460      * due to a squash.
 461      */
 462     Stats::Scalar<> fetchIcacheSquashes;
 463     /** Distribution of number of instructions fetched each cycle. */
 464     Stats::Distribution<> fetchNisnDist;
 465     /** Rate of how often fetch was idle. */
 466     Stats::Formula idleRate;
 467     /** Number of branch fetches per cycle. */
 468     Stats::Formula branchRate;
 469     /** Number of instruction fetched per cycle. */
 470     Stats::Formula fetchRate;
 471 };
 472
 473 #endif //__CPU_O3_FETCH_HH__