src/cpu/o3/fetch.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Korey Sewell
  30  */
  31
  32 #ifndef __CPU_O3_FETCH_HH__
  33 #define __CPU_O3_FETCH_HH__
  34
  35 #include "arch/utility.hh"
  36 #include "base/statistics.hh"
  37 #include "base/timebuf.hh"
  38 #include "cpu/pc_event.hh"
  39 #include "mem/packet.hh"
  40 #include "mem/port.hh"
  41 #include "sim/eventq.hh"
  42
  43 /**
  44  * DefaultFetch class handles both single threaded and SMT fetch. Its
  45  * width is specified by the parameters; each cycle it tries to fetch
  46  * that many instructions. It supports using a branch predictor to
  47  * predict direction and targets.
  48  * It supports the idling functionality of the CPU by indicating to
  49  * the CPU when it is active and inactive.
  50  */
  51 template <class Impl>
  52 class DefaultFetch
  53 {
  54   public:
  55     /** Typedefs from Impl. */
  56     typedef typename Impl::CPUPol CPUPol;
  57     typedef typename Impl::DynInst DynInst;
  58     typedef typename Impl::DynInstPtr DynInstPtr;
  59     typedef typename Impl::O3CPU O3CPU;
  60     typedef typename Impl::Params Params;
  61
  62     /** Typedefs from the CPU policy. */
  63     typedef typename CPUPol::BPredUnit BPredUnit;
  64     typedef typename CPUPol::FetchStruct FetchStruct;
  65     typedef typename CPUPol::TimeStruct TimeStruct;
  66
  67     /** Typedefs from ISA. */
  68     typedef TheISA::MachInst MachInst;
  69     typedef TheISA::ExtMachInst ExtMachInst;
  70
  71     /** IcachePort class for DefaultFetch.  Handles doing the
  72      * communication with the cache/memory.
  73      */
  74     class IcachePort : public Port
  75     {
  76       protected:
  77         /** Pointer to fetch. */
  78         DefaultFetch<Impl> *fetch;
  79
  80       public:
  81         /** Default constructor. */
  82         IcachePort(DefaultFetch<Impl> *_fetch)
  83             : Port(_fetch->name() + "-iport"), fetch(_fetch)
  84         { }
  85
  86         bool snoopRangeSent;
  87
  88       protected:
  89         /** Atomic version of receive.  Panics. */
  90         virtual Tick recvAtomic(PacketPtr pkt);
  91
  92         /** Functional version of receive.  Panics. */
  93         virtual void recvFunctional(PacketPtr pkt);
  94
  95         /** Receives status change.  Other than range changing, panics. */
  96         virtual void recvStatusChange(Status status);
  97
  98         /** Returns the address ranges of this device. */
  99         virtual void getDeviceAddressRanges(AddrRangeList &resp,
 100                                             AddrRangeList &snoop)
 101         { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
 102
 103         /** Timing version of receive.  Handles setting fetch to the
 104          * proper status to start fetching. */
 105         virtual bool recvTiming(PacketPtr pkt);
 106
 107         /** Handles doing a retry of a failed fetch. */
 108         virtual void recvRetry();
 109     };
 110
 111
 112   public:
 113     /** Overall fetch status. Used to determine if the CPU can
 114      * deschedule itsef due to a lack of activity.
 115      */
 116     enum FetchStatus {
 117         Active,
 118         Inactive
 119     };
 120
 121     /** Individual thread status. */
 122     enum ThreadStatus {
 123         Running,
 124         Idle,
 125         Squashing,
 126         Blocked,
 127         Fetching,
 128         TrapPending,
 129         QuiescePending,
 130         SwitchOut,
 131         IcacheWaitResponse,
 132         IcacheWaitRetry,
 133         IcacheAccessComplete
 134     };
 135
 136     /** Fetching Policy, Add new policies here.*/
 137     enum FetchPriority {
 138         SingleThread,
 139         RoundRobin,
 140         Branch,
 141         IQ,
 142         LSQ
 143     };
 144
 145   private:
 146     /** Fetch status. */
 147     FetchStatus _status;
 148
 149     /** Per-thread status. */
 150     ThreadStatus fetchStatus[Impl::MaxThreads];
 151
 152     /** Fetch policy. */
 153     FetchPriority fetchPolicy;
 154
 155     /** List that has the threads organized by priority. */
 156     std::list<unsigned> priorityList;
 157
 158   public:
 159     /** DefaultFetch constructor. */
 160     DefaultFetch(Params *params);
 161
 162     /** Returns the name of fetch. */
 163     std::string name() const;
 164
 165     /** Registers statistics. */
 166     void regStats();
 167
 168     /** Returns the icache port. */
 169     Port *getIcachePort() { return icachePort; }
 170
 171     /** Sets CPU pointer. */
 172     void setCPU(O3CPU *cpu_ptr);
 173
 174     /** Sets the main backwards communication time buffer pointer. */
 175     void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
 176
 177     /** Sets pointer to list of active threads. */
 178     void setActiveThreads(std::list<unsigned> *at_ptr);
 179
 180     /** Sets pointer to time buffer used to communicate to the next stage. */
 181     void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
 182
 183     /** Initialize stage. */
 184     void initStage();
 185
 186     /** Processes cache completion event. */
 187     void processCacheCompletion(PacketPtr pkt);
 188
 189     /** Begins the drain of the fetch stage. */
 190     bool drain();
 191
 192     /** Resumes execution after a drain. */
 193     void resume();
 194
 195     /** Tells fetch stage to prepare to be switched out. */
 196     void switchOut();
 197
 198     /** Takes over from another CPU's thread. */
 199     void takeOverFrom();
 200
 201     /** Checks if the fetch stage is switched out. */
 202     bool isSwitchedOut() { return switchedOut; }
 203
 204     /** Tells fetch to wake up from a quiesce instruction. */
 205     void wakeFromQuiesce();
 206
 207   private:
 208     /** Changes the status of this stage to active, and indicates this
 209      * to the CPU.
 210      */
 211     inline void switchToActive();
 212
 213     /** Changes the status of this stage to inactive, and indicates
 214      * this to the CPU.
 215      */
 216     inline void switchToInactive();
 217
 218     /**
 219      * Looks up in the branch predictor to see if the next PC should be
 220      * either next PC+=MachInst or a branch target.
 221      * @param next_PC Next PC variable passed in by reference.  It is
 222      * expected to be set to the current PC; it will be updated with what
 223      * the next PC will be.
 224      * @param next_NPC Used for ISAs which use delay slots.
 225      * @return Whether or not a branch was predicted as taken.
 226      */
 227     bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC);
 228
 229     /**
 230      * Fetches the cache line that contains fetch_PC.  Returns any
 231      * fault that happened.  Puts the data into the class variable
 232      * cacheData.
 233      * @param fetch_PC The PC address that is being fetched from.
 234      * @param ret_fault The fault reference that will be set to the result of
 235      * the icache access.
 236      * @param tid Thread id.
 237      * @return Any fault that occured.
 238      */
 239     bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
 240
 241     /** Squashes a specific thread and resets the PC. */
 242     inline void doSquash(const Addr &new_PC, const Addr &new_NPC, unsigned tid);
 243
 244     /** Squashes a specific thread and resets the PC. Also tells the CPU to
 245      * remove any instructions between fetch and decode that should be sqaushed.
 246      */
 247     void squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
 248                           const InstSeqNum &seq_num, unsigned tid);
 249
 250     /** Checks if a thread is stalled. */
 251     bool checkStall(unsigned tid) const;
 252
 253     /** Updates overall fetch stage status; to be called at the end of each
 254      * cycle. */
 255     FetchStatus updateFetchStatus();
 256
 257   public:
 258     /** Squashes a specific thread and resets the PC. Also tells the CPU to
 259      * remove any instructions that are not in the ROB. The source of this
 260      * squash should be the commit stage.
 261      */
 262     void squash(const Addr &new_PC, const Addr &new_NPC,
 263                 const InstSeqNum &seq_num,
 264                 bool squash_delay_slot, unsigned tid);
 265
 266     /** Ticks the fetch stage, processing all inputs signals and fetching
 267      * as many instructions as possible.
 268      */
 269     void tick();
 270
 271     /** Checks all input signals and updates the status as necessary.
 272      *  @return: Returns if the status has changed due to input signals.
 273      */
 274     bool checkSignalsAndUpdate(unsigned tid);
 275
 276     /** Does the actual fetching of instructions and passing them on to the
 277      * next stage.
 278      * @param status_change fetch() sets this variable if there was a status
 279      * change (ie switching to IcacheMissStall).
 280      */
 281     void fetch(bool &status_change);
 282
 283     /** Align a PC to the start of an I-cache block. */
 284     Addr icacheBlockAlignPC(Addr addr)
 285     {
 286         addr = TheISA::realPCToFetchPC(addr);
 287         return (addr & ~(cacheBlkMask));
 288     }
 289
 290   private:
 291     /** Handles retrying the fetch access. */
 292     void recvRetry();
 293
 294     /** Returns the appropriate thread to fetch, given the fetch policy. */
 295     int getFetchingThread(FetchPriority &fetch_priority);
 296
 297     /** Returns the appropriate thread to fetch using a round robin policy. */
 298     int roundRobin();
 299
 300     /** Returns the appropriate thread to fetch using the IQ count policy. */
 301     int iqCount();
 302
 303     /** Returns the appropriate thread to fetch using the LSQ count policy. */
 304     int lsqCount();
 305
 306     /** Returns the appropriate thread to fetch using the branch count policy. */
 307     int branchCount();
 308
 309   private:
 310     /** Pointer to the O3CPU. */
 311     O3CPU *cpu;
 312
 313     /** Time buffer interface. */
 314     TimeBuffer<TimeStruct> *timeBuffer;
 315
 316     /** Wire to get decode's information from backwards time buffer. */
 317     typename TimeBuffer<TimeStruct>::wire fromDecode;
 318
 319     /** Wire to get rename's information from backwards time buffer. */
 320     typename TimeBuffer<TimeStruct>::wire fromRename;
 321
 322     /** Wire to get iew's information from backwards time buffer. */
 323     typename TimeBuffer<TimeStruct>::wire fromIEW;
 324
 325     /** Wire to get commit's information from backwards time buffer. */
 326     typename TimeBuffer<TimeStruct>::wire fromCommit;
 327
 328     /** Internal fetch instruction queue. */
 329     TimeBuffer<FetchStruct> *fetchQueue;
 330
 331     //Might be annoying how this name is different than the queue.
 332     /** Wire used to write any information heading to decode. */
 333     typename TimeBuffer<FetchStruct>::wire toDecode;
 334
 335     /** Icache interface. */
 336     IcachePort *icachePort;
 337
 338     /** BPredUnit. */
 339     BPredUnit branchPred;
 340
 341     /** Per-thread fetch PC. */
 342     Addr PC[Impl::MaxThreads];
 343
 344     /** Per-thread next PC. */
 345     Addr nextPC[Impl::MaxThreads];
 346
 347     /** Per-thread next Next PC.
 348      *  This is not a real register but is used for
 349      *  architectures that use a branch-delay slot.
 350      *  (such as MIPS or Sparc)
 351      */
 352     Addr nextNPC[Impl::MaxThreads];
 353
 354     /** Memory request used to access cache. */
 355     RequestPtr memReq[Impl::MaxThreads];
 356
 357     /** Variable that tracks if fetch has written to the time buffer this
 358      * cycle. Used to tell CPU if there is activity this cycle.
 359      */
 360     bool wroteToTimeBuffer;
 361
 362     /** Tracks how many instructions has been fetched this cycle. */
 363     int numInst;
 364
 365     /** Source of possible stalls. */
 366     struct Stalls {
 367         bool decode;
 368         bool rename;
 369         bool iew;
 370         bool commit;
 371     };
 372
 373     /** Tracks which stages are telling fetch to stall. */
 374     Stalls stalls[Impl::MaxThreads];
 375
 376     /** Decode to fetch delay, in ticks. */
 377     unsigned decodeToFetchDelay;
 378
 379     /** Rename to fetch delay, in ticks. */
 380     unsigned renameToFetchDelay;
 381
 382     /** IEW to fetch delay, in ticks. */
 383     unsigned iewToFetchDelay;
 384
 385     /** Commit to fetch delay, in ticks. */
 386     unsigned commitToFetchDelay;
 387
 388     /** The width of fetch in instructions. */
 389     unsigned fetchWidth;
 390
 391     /** Is the cache blocked?  If so no threads can access it. */
 392     bool cacheBlocked;
 393
 394     /** The packet that is waiting to be retried. */
 395     PacketPtr retryPkt;
 396
 397     /** The thread that is waiting on the cache to tell fetch to retry. */
 398     int retryTid;
 399
 400     /** Cache block size. */
 401     int cacheBlkSize;
 402
 403     /** Mask to get a cache block's address. */
 404     Addr cacheBlkMask;
 405
 406     /** The cache line being fetched. */
 407     uint8_t *cacheData[Impl::MaxThreads];
 408
 409     /** The PC of the cacheline that has been loaded. */
 410     Addr cacheDataPC[Impl::MaxThreads];
 411
 412     /** Whether or not the cache data is valid. */
 413     bool cacheDataValid[Impl::MaxThreads];
 414
 415     /** Size of instructions. */
 416     int instSize;
 417
 418     /** Icache stall statistics. */
 419     Counter lastIcacheStall[Impl::MaxThreads];
 420
 421     /** List of Active Threads */
 422     std::list<unsigned> *activeThreads;
 423
 424     /** Number of threads. */
 425     unsigned numThreads;
 426
 427     /** Number of threads that are actively fetching. */
 428     unsigned numFetchingThreads;
 429
 430     /** Thread ID being fetched. */
 431     int threadFetched;
 432
 433     /** Checks if there is an interrupt pending.  If there is, fetch
 434      * must stop once it is not fetching PAL instructions.
 435      */
 436     bool interruptPending;
 437
 438     /** Is there a drain pending. */
 439     bool drainPending;
 440
 441     /** Records if fetch is switched out. */
 442     bool switchedOut;
 443
 444     // @todo: Consider making these vectors and tracking on a per thread basis.
 445     /** Stat for total number of cycles stalled due to an icache miss. */
 446     Stats::Scalar<> icacheStallCycles;
 447     /** Stat for total number of fetched instructions. */
 448     Stats::Scalar<> fetchedInsts;
 449     /** Total number of fetched branches. */
 450     Stats::Scalar<> fetchedBranches;
 451     /** Stat for total number of predicted branches. */
 452     Stats::Scalar<> predictedBranches;
 453     /** Stat for total number of cycles spent fetching. */
 454     Stats::Scalar<> fetchCycles;
 455     /** Stat for total number of cycles spent squashing. */
 456     Stats::Scalar<> fetchSquashCycles;
 457     /** Stat for total number of cycles spent blocked due to other stages in
 458      * the pipeline.
 459      */
 460     Stats::Scalar<> fetchIdleCycles;
 461     /** Total number of cycles spent blocked. */
 462     Stats::Scalar<> fetchBlockedCycles;
 463     /** Total number of cycles spent in any other state. */
 464     Stats::Scalar<> fetchMiscStallCycles;
 465     /** Stat for total number of fetched cache lines. */
 466     Stats::Scalar<> fetchedCacheLines;
 467     /** Total number of outstanding icache accesses that were dropped
 468      * due to a squash.
 469      */
 470     Stats::Scalar<> fetchIcacheSquashes;
 471     /** Distribution of number of instructions fetched each cycle. */
 472     Stats::Distribution<> fetchNisnDist;
 473     /** Rate of how often fetch was idle. */
 474     Stats::Formula idleRate;
 475     /** Number of branch fetches per cycle. */
 476     Stats::Formula branchRate;
 477     /** Number of instruction fetched per cycle. */
 478     Stats::Formula fetchRate;
 479 };
 480
 481 #endif //__CPU_O3_FETCH_HH__