2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #ifndef __CPU_O3_FETCH_HH__
33 #define __CPU_O3_FETCH_HH__
35 #include "arch/utility.hh"
36 #include "base/statistics.hh"
37 #include "base/timebuf.hh"
38 #include "cpu/pc_event.hh"
39 #include "mem/packet_impl.hh"
40 #include "mem/port.hh"
41 #include "sim/eventq.hh"
44 * DefaultFetch class handles both single threaded and SMT fetch. Its
45 * width is specified by the parameters; each cycle it tries to fetch
46 * that many instructions. It supports using a branch predictor to
47 * predict direction and targets.
48 * It supports the idling functionality of the CPU by indicating to
49 * the CPU when it is active and inactive.
55 /** Typedefs from Impl. */
56 typedef typename Impl::CPUPol CPUPol;
57 typedef typename Impl::DynInst DynInst;
58 typedef typename Impl::DynInstPtr DynInstPtr;
59 typedef typename Impl::O3CPU O3CPU;
60 typedef typename Impl::Params Params;
62 /** Typedefs from the CPU policy. */
63 typedef typename CPUPol::BPredUnit BPredUnit;
64 typedef typename CPUPol::FetchStruct FetchStruct;
65 typedef typename CPUPol::TimeStruct TimeStruct;
67 /** Typedefs from ISA. */
68 typedef TheISA::MachInst MachInst;
69 typedef TheISA::ExtMachInst ExtMachInst;
71 /** IcachePort class for DefaultFetch. Handles doing the
72 * communication with the cache/memory.
74 class IcachePort : public Port
77 /** Pointer to fetch. */
78 DefaultFetch<Impl> *fetch;
81 /** Default constructor. */
82 IcachePort(DefaultFetch<Impl> *_fetch)
83 : Port(_fetch->name() + "-iport"), fetch(_fetch)
87 /** Atomic version of receive. Panics. */
88 virtual Tick recvAtomic(PacketPtr pkt);
90 /** Functional version of receive. Panics. */
91 virtual void recvFunctional(PacketPtr pkt);
93 /** Receives status change. Other than range changing, panics. */
94 virtual void recvStatusChange(Status status);
96 /** Returns the address ranges of this device. */
97 virtual void getDeviceAddressRanges(AddrRangeList &resp,
99 { resp.clear(); snoop.clear(); }
101 /** Timing version of receive. Handles setting fetch to the
102 * proper status to start fetching. */
103 virtual bool recvTiming(PacketPtr pkt);
105 /** Handles doing a retry of a failed fetch. */
106 virtual void recvRetry();
110 /** Overall fetch status. Used to determine if the CPU can
111 * deschedule itsef due to a lack of activity.
118 /** Individual thread status. */
133 /** Fetching Policy, Add new policies here.*/
146 /** Per-thread status. */
147 ThreadStatus fetchStatus[Impl::MaxThreads];
150 FetchPriority fetchPolicy;
152 /** List that has the threads organized by priority. */
153 std::list<unsigned> priorityList;
156 /** DefaultFetch constructor. */
157 DefaultFetch(Params *params);
159 /** Returns the name of fetch. */
160 std::string name() const;
162 /** Registers statistics. */
165 /** Returns the icache port. */
166 Port *getIcachePort() { return icachePort; }
168 /** Sets CPU pointer. */
169 void setCPU(O3CPU *cpu_ptr);
171 /** Sets the main backwards communication time buffer pointer. */
172 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
174 /** Sets pointer to list of active threads. */
175 void setActiveThreads(std::list<unsigned> *at_ptr);
177 /** Sets pointer to time buffer used to communicate to the next stage. */
178 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
180 /** Initialize stage. */
183 /** Processes cache completion event. */
184 void processCacheCompletion(PacketPtr pkt);
186 /** Begins the drain of the fetch stage. */
189 /** Resumes execution after a drain. */
192 /** Tells fetch stage to prepare to be switched out. */
195 /** Takes over from another CPU's thread. */
198 /** Checks if the fetch stage is switched out. */
199 bool isSwitchedOut() { return switchedOut; }
201 /** Tells fetch to wake up from a quiesce instruction. */
202 void wakeFromQuiesce();
205 /** Changes the status of this stage to active, and indicates this
208 inline void switchToActive();
210 /** Changes the status of this stage to inactive, and indicates
213 inline void switchToInactive();
216 * Looks up in the branch predictor to see if the next PC should be
217 * either next PC+=MachInst or a branch target.
218 * @param next_PC Next PC variable passed in by reference. It is
219 * expected to be set to the current PC; it will be updated with what
220 * the next PC will be.
221 * @return Whether or not a branch was predicted as taken.
223 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC);
226 * Fetches the cache line that contains fetch_PC. Returns any
227 * fault that happened. Puts the data into the class variable
229 * @param fetch_PC The PC address that is being fetched from.
230 * @param ret_fault The fault reference that will be set to the result of
232 * @param tid Thread id.
233 * @return Any fault that occured.
235 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
237 /** Squashes a specific thread and resets the PC. */
238 inline void doSquash(const Addr &new_PC, unsigned tid);
240 /** Squashes a specific thread and resets the PC. Also tells the CPU to
241 * remove any instructions between fetch and decode that should be sqaushed.
243 void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
246 /** Checks if a thread is stalled. */
247 bool checkStall(unsigned tid) const;
249 /** Updates overall fetch stage status; to be called at the end of each
251 FetchStatus updateFetchStatus();
254 /** Squashes a specific thread and resets the PC. Also tells the CPU to
255 * remove any instructions that are not in the ROB. The source of this
256 * squash should be the commit stage.
258 void squash(const Addr &new_PC, unsigned tid);
260 /** Ticks the fetch stage, processing all inputs signals and fetching
261 * as many instructions as possible.
265 /** Checks all input signals and updates the status as necessary.
266 * @return: Returns if the status has changed due to input signals.
268 bool checkSignalsAndUpdate(unsigned tid);
270 /** Does the actual fetching of instructions and passing them on to the
272 * @param status_change fetch() sets this variable if there was a status
273 * change (ie switching to IcacheMissStall).
275 void fetch(bool &status_change);
277 /** Align a PC to the start of an I-cache block. */
278 Addr icacheBlockAlignPC(Addr addr)
280 addr = TheISA::realPCToFetchPC(addr);
281 return (addr & ~(cacheBlkMask));
285 /** Handles retrying the fetch access. */
288 /** Returns the appropriate thread to fetch, given the fetch policy. */
289 int getFetchingThread(FetchPriority &fetch_priority);
291 /** Returns the appropriate thread to fetch using a round robin policy. */
294 /** Returns the appropriate thread to fetch using the IQ count policy. */
297 /** Returns the appropriate thread to fetch using the LSQ count policy. */
300 /** Returns the appropriate thread to fetch using the branch count policy. */
304 /** Pointer to the O3CPU. */
307 /** Time buffer interface. */
308 TimeBuffer<TimeStruct> *timeBuffer;
310 /** Wire to get decode's information from backwards time buffer. */
311 typename TimeBuffer<TimeStruct>::wire fromDecode;
313 /** Wire to get rename's information from backwards time buffer. */
314 typename TimeBuffer<TimeStruct>::wire fromRename;
316 /** Wire to get iew's information from backwards time buffer. */
317 typename TimeBuffer<TimeStruct>::wire fromIEW;
319 /** Wire to get commit's information from backwards time buffer. */
320 typename TimeBuffer<TimeStruct>::wire fromCommit;
322 /** Internal fetch instruction queue. */
323 TimeBuffer<FetchStruct> *fetchQueue;
325 //Might be annoying how this name is different than the queue.
326 /** Wire used to write any information heading to decode. */
327 typename TimeBuffer<FetchStruct>::wire toDecode;
331 /** Icache interface. */
332 IcachePort *icachePort;
335 BPredUnit branchPred;
337 /** Per-thread fetch PC. */
338 Addr PC[Impl::MaxThreads];
340 /** Per-thread next PC. */
341 Addr nextPC[Impl::MaxThreads];
343 #if THE_ISA != ALPHA_ISA
344 /** Per-thread next Next PC.
345 * This is not a real register but is used for
346 * architectures that use a branch-delay slot.
347 * (such as MIPS or Sparc)
349 Addr nextNPC[Impl::MaxThreads];
352 /** Memory request used to access cache. */
353 RequestPtr memReq[Impl::MaxThreads];
355 /** Variable that tracks if fetch has written to the time buffer this
356 * cycle. Used to tell CPU if there is activity this cycle.
358 bool wroteToTimeBuffer;
360 /** Tracks how many instructions has been fetched this cycle. */
363 /** Source of possible stalls. */
371 /** Tracks which stages are telling fetch to stall. */
372 Stalls stalls[Impl::MaxThreads];
374 /** Decode to fetch delay, in ticks. */
375 unsigned decodeToFetchDelay;
377 /** Rename to fetch delay, in ticks. */
378 unsigned renameToFetchDelay;
380 /** IEW to fetch delay, in ticks. */
381 unsigned iewToFetchDelay;
383 /** Commit to fetch delay, in ticks. */
384 unsigned commitToFetchDelay;
386 /** The width of fetch in instructions. */
389 /** Is the cache blocked? If so no threads can access it. */
392 /** The packet that is waiting to be retried. */
395 /** The thread that is waiting on the cache to tell fetch to retry. */
398 /** Cache block size. */
401 /** Mask to get a cache block's address. */
404 /** The cache line being fetched. */
405 uint8_t *cacheData[Impl::MaxThreads];
407 /** The PC of the cacheline that has been loaded. */
408 Addr cacheDataPC[Impl::MaxThreads];
410 /** Size of instructions. */
413 /** Icache stall statistics. */
414 Counter lastIcacheStall[Impl::MaxThreads];
416 /** List of Active Threads */
417 std::list<unsigned> *activeThreads;
419 /** Number of threads. */
422 /** Number of threads that are actively fetching. */
423 unsigned numFetchingThreads;
425 /** Thread ID being fetched. */
428 /** Checks if there is an interrupt pending. If there is, fetch
429 * must stop once it is not fetching PAL instructions.
431 bool interruptPending;
433 /** Is there a drain pending. */
436 /** Records if fetch is switched out. */
439 // @todo: Consider making these vectors and tracking on a per thread basis.
440 /** Stat for total number of cycles stalled due to an icache miss. */
441 Stats::Scalar<> icacheStallCycles;
442 /** Stat for total number of fetched instructions. */
443 Stats::Scalar<> fetchedInsts;
444 /** Total number of fetched branches. */
445 Stats::Scalar<> fetchedBranches;
446 /** Stat for total number of predicted branches. */
447 Stats::Scalar<> predictedBranches;
448 /** Stat for total number of cycles spent fetching. */
449 Stats::Scalar<> fetchCycles;
450 /** Stat for total number of cycles spent squashing. */
451 Stats::Scalar<> fetchSquashCycles;
452 /** Stat for total number of cycles spent blocked due to other stages in
455 Stats::Scalar<> fetchIdleCycles;
456 /** Total number of cycles spent blocked. */
457 Stats::Scalar<> fetchBlockedCycles;
458 /** Total number of cycles spent in any other state. */
459 Stats::Scalar<> fetchMiscStallCycles;
460 /** Stat for total number of fetched cache lines. */
461 Stats::Scalar<> fetchedCacheLines;
462 /** Total number of outstanding icache accesses that were dropped
465 Stats::Scalar<> fetchIcacheSquashes;
466 /** Distribution of number of instructions fetched each cycle. */
467 Stats::Distribution<> fetchNisnDist;
468 /** Rate of how often fetch was idle. */
469 Stats::Formula idleRate;
470 /** Number of branch fetches per cycle. */
471 Stats::Formula branchRate;
472 /** Number of instruction fetched per cycle. */
473 Stats::Formula fetchRate;
476 #endif //__CPU_O3_FETCH_HH__