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32 #ifndef __CPU_O3_FETCH_HH__
33 #define __CPU_O3_FETCH_HH__
35 #include "arch/utility.hh"
36 #include "base/statistics.hh"
37 #include "base/timebuf.hh"
38 #include "cpu/pc_event.hh"
39 #include "mem/packet.hh"
40 #include "mem/port.hh"
41 #include "sim/eventq.hh"
44 * DefaultFetch class handles both single threaded and SMT fetch. Its
45 * width is specified by the parameters; each cycle it tries to fetch
46 * that many instructions. It supports using a branch predictor to
47 * predict direction and targets.
48 * It supports the idling functionality of the CPU by indicating to
49 * the CPU when it is active and inactive.
55 /** Typedefs from Impl. */
56 typedef typename Impl::CPUPol CPUPol;
57 typedef typename Impl::DynInst DynInst;
58 typedef typename Impl::DynInstPtr DynInstPtr;
59 typedef typename Impl::O3CPU O3CPU;
60 typedef typename Impl::Params Params;
62 /** Typedefs from the CPU policy. */
63 typedef typename CPUPol::BPredUnit BPredUnit;
64 typedef typename CPUPol::FetchStruct FetchStruct;
65 typedef typename CPUPol::TimeStruct TimeStruct;
67 /** Typedefs from ISA. */
68 typedef TheISA::MachInst MachInst;
69 typedef TheISA::ExtMachInst ExtMachInst;
71 /** IcachePort class for DefaultFetch. Handles doing the
72 * communication with the cache/memory.
74 class IcachePort : public Port
77 /** Pointer to fetch. */
78 DefaultFetch<Impl> *fetch;
81 /** Default constructor. */
82 IcachePort(DefaultFetch<Impl> *_fetch)
83 : Port(_fetch->name() + "-iport"), fetch(_fetch)
87 /** Atomic version of receive. Panics. */
88 virtual Tick recvAtomic(PacketPtr pkt);
90 /** Functional version of receive. Panics. */
91 virtual void recvFunctional(PacketPtr pkt);
93 /** Receives status change. Other than range changing, panics. */
94 virtual void recvStatusChange(Status status);
96 /** Returns the address ranges of this device. */
97 virtual void getDeviceAddressRanges(AddrRangeList &resp,
99 { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
101 /** Timing version of receive. Handles setting fetch to the
102 * proper status to start fetching. */
103 virtual bool recvTiming(PacketPtr pkt);
105 /** Handles doing a retry of a failed fetch. */
106 virtual void recvRetry();
111 /** Overall fetch status. Used to determine if the CPU can
112 * deschedule itsef due to a lack of activity.
119 /** Individual thread status. */
134 /** Fetching Policy, Add new policies here.*/
147 /** Per-thread status. */
148 ThreadStatus fetchStatus[Impl::MaxThreads];
151 FetchPriority fetchPolicy;
153 /** List that has the threads organized by priority. */
154 std::list<unsigned> priorityList;
157 /** DefaultFetch constructor. */
158 DefaultFetch(Params *params);
160 /** Returns the name of fetch. */
161 std::string name() const;
163 /** Registers statistics. */
166 /** Returns the icache port. */
167 Port *getIcachePort() { return icachePort; }
169 /** Sets CPU pointer. */
170 void setCPU(O3CPU *cpu_ptr);
172 /** Sets the main backwards communication time buffer pointer. */
173 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
175 /** Sets pointer to list of active threads. */
176 void setActiveThreads(std::list<unsigned> *at_ptr);
178 /** Sets pointer to time buffer used to communicate to the next stage. */
179 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
181 /** Initialize stage. */
184 /** Processes cache completion event. */
185 void processCacheCompletion(PacketPtr pkt);
187 /** Begins the drain of the fetch stage. */
190 /** Resumes execution after a drain. */
193 /** Tells fetch stage to prepare to be switched out. */
196 /** Takes over from another CPU's thread. */
199 /** Checks if the fetch stage is switched out. */
200 bool isSwitchedOut() { return switchedOut; }
202 /** Tells fetch to wake up from a quiesce instruction. */
203 void wakeFromQuiesce();
206 /** Changes the status of this stage to active, and indicates this
209 inline void switchToActive();
211 /** Changes the status of this stage to inactive, and indicates
214 inline void switchToInactive();
217 * Looks up in the branch predictor to see if the next PC should be
218 * either next PC+=MachInst or a branch target.
219 * @param next_PC Next PC variable passed in by reference. It is
220 * expected to be set to the current PC; it will be updated with what
221 * the next PC will be.
222 * @param next_NPC Used for ISAs which use delay slots.
223 * @return Whether or not a branch was predicted as taken.
225 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC);
228 * Fetches the cache line that contains fetch_PC. Returns any
229 * fault that happened. Puts the data into the class variable
231 * @param fetch_PC The PC address that is being fetched from.
232 * @param ret_fault The fault reference that will be set to the result of
234 * @param tid Thread id.
235 * @return Any fault that occured.
237 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
239 /** Squashes a specific thread and resets the PC. */
240 inline void doSquash(const Addr &new_PC, unsigned tid);
242 /** Squashes a specific thread and resets the PC. Also tells the CPU to
243 * remove any instructions between fetch and decode that should be sqaushed.
245 void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
248 /** Checks if a thread is stalled. */
249 bool checkStall(unsigned tid) const;
251 /** Updates overall fetch stage status; to be called at the end of each
253 FetchStatus updateFetchStatus();
256 /** Squashes a specific thread and resets the PC. Also tells the CPU to
257 * remove any instructions that are not in the ROB. The source of this
258 * squash should be the commit stage.
260 void squash(const Addr &new_PC, const InstSeqNum &seq_num,
261 bool squash_delay_slot, unsigned tid);
263 /** Ticks the fetch stage, processing all inputs signals and fetching
264 * as many instructions as possible.
268 /** Checks all input signals and updates the status as necessary.
269 * @return: Returns if the status has changed due to input signals.
271 bool checkSignalsAndUpdate(unsigned tid);
273 /** Does the actual fetching of instructions and passing them on to the
275 * @param status_change fetch() sets this variable if there was a status
276 * change (ie switching to IcacheMissStall).
278 void fetch(bool &status_change);
280 /** Align a PC to the start of an I-cache block. */
281 Addr icacheBlockAlignPC(Addr addr)
283 addr = TheISA::realPCToFetchPC(addr);
284 return (addr & ~(cacheBlkMask));
288 /** Handles retrying the fetch access. */
291 /** Returns the appropriate thread to fetch, given the fetch policy. */
292 int getFetchingThread(FetchPriority &fetch_priority);
294 /** Returns the appropriate thread to fetch using a round robin policy. */
297 /** Returns the appropriate thread to fetch using the IQ count policy. */
300 /** Returns the appropriate thread to fetch using the LSQ count policy. */
303 /** Returns the appropriate thread to fetch using the branch count policy. */
307 /** Pointer to the O3CPU. */
310 /** Time buffer interface. */
311 TimeBuffer<TimeStruct> *timeBuffer;
313 /** Wire to get decode's information from backwards time buffer. */
314 typename TimeBuffer<TimeStruct>::wire fromDecode;
316 /** Wire to get rename's information from backwards time buffer. */
317 typename TimeBuffer<TimeStruct>::wire fromRename;
319 /** Wire to get iew's information from backwards time buffer. */
320 typename TimeBuffer<TimeStruct>::wire fromIEW;
322 /** Wire to get commit's information from backwards time buffer. */
323 typename TimeBuffer<TimeStruct>::wire fromCommit;
325 /** Internal fetch instruction queue. */
326 TimeBuffer<FetchStruct> *fetchQueue;
328 //Might be annoying how this name is different than the queue.
329 /** Wire used to write any information heading to decode. */
330 typename TimeBuffer<FetchStruct>::wire toDecode;
334 /** Icache interface. */
335 IcachePort *icachePort;
338 BPredUnit branchPred;
340 /** Per-thread fetch PC. */
341 Addr PC[Impl::MaxThreads];
343 /** Per-thread next PC. */
344 Addr nextPC[Impl::MaxThreads];
346 /** Per-thread next Next PC.
347 * This is not a real register but is used for
348 * architectures that use a branch-delay slot.
349 * (such as MIPS or Sparc)
351 Addr nextNPC[Impl::MaxThreads];
353 /** Memory request used to access cache. */
354 RequestPtr memReq[Impl::MaxThreads];
356 /** Variable that tracks if fetch has written to the time buffer this
357 * cycle. Used to tell CPU if there is activity this cycle.
359 bool wroteToTimeBuffer;
361 /** Tracks how many instructions has been fetched this cycle. */
364 /** Tracks delay slot information for threads in ISAs which use
367 struct DelaySlotInfo {
368 InstSeqNum delaySlotSeqNum;
369 InstSeqNum branchSeqNum;
375 DelaySlotInfo delaySlotInfo[Impl::MaxThreads];
377 /** Source of possible stalls. */
385 /** Tracks which stages are telling fetch to stall. */
386 Stalls stalls[Impl::MaxThreads];
388 /** Decode to fetch delay, in ticks. */
389 unsigned decodeToFetchDelay;
391 /** Rename to fetch delay, in ticks. */
392 unsigned renameToFetchDelay;
394 /** IEW to fetch delay, in ticks. */
395 unsigned iewToFetchDelay;
397 /** Commit to fetch delay, in ticks. */
398 unsigned commitToFetchDelay;
400 /** The width of fetch in instructions. */
403 /** Is the cache blocked? If so no threads can access it. */
406 /** The packet that is waiting to be retried. */
409 /** The thread that is waiting on the cache to tell fetch to retry. */
412 /** Cache block size. */
415 /** Mask to get a cache block's address. */
418 /** The cache line being fetched. */
419 uint8_t *cacheData[Impl::MaxThreads];
421 /** The PC of the cacheline that has been loaded. */
422 Addr cacheDataPC[Impl::MaxThreads];
424 /** Whether or not the cache data is valid. */
425 bool cacheDataValid[Impl::MaxThreads];
427 /** Size of instructions. */
430 /** Icache stall statistics. */
431 Counter lastIcacheStall[Impl::MaxThreads];
433 /** List of Active Threads */
434 std::list<unsigned> *activeThreads;
436 /** Number of threads. */
439 /** Number of threads that are actively fetching. */
440 unsigned numFetchingThreads;
442 /** Thread ID being fetched. */
445 /** Checks if there is an interrupt pending. If there is, fetch
446 * must stop once it is not fetching PAL instructions.
448 bool interruptPending;
450 /** Is there a drain pending. */
453 /** Records if fetch is switched out. */
456 // @todo: Consider making these vectors and tracking on a per thread basis.
457 /** Stat for total number of cycles stalled due to an icache miss. */
458 Stats::Scalar<> icacheStallCycles;
459 /** Stat for total number of fetched instructions. */
460 Stats::Scalar<> fetchedInsts;
461 /** Total number of fetched branches. */
462 Stats::Scalar<> fetchedBranches;
463 /** Stat for total number of predicted branches. */
464 Stats::Scalar<> predictedBranches;
465 /** Stat for total number of cycles spent fetching. */
466 Stats::Scalar<> fetchCycles;
467 /** Stat for total number of cycles spent squashing. */
468 Stats::Scalar<> fetchSquashCycles;
469 /** Stat for total number of cycles spent blocked due to other stages in
472 Stats::Scalar<> fetchIdleCycles;
473 /** Total number of cycles spent blocked. */
474 Stats::Scalar<> fetchBlockedCycles;
475 /** Total number of cycles spent in any other state. */
476 Stats::Scalar<> fetchMiscStallCycles;
477 /** Stat for total number of fetched cache lines. */
478 Stats::Scalar<> fetchedCacheLines;
479 /** Total number of outstanding icache accesses that were dropped
482 Stats::Scalar<> fetchIcacheSquashes;
483 /** Distribution of number of instructions fetched each cycle. */
484 Stats::Distribution<> fetchNisnDist;
485 /** Rate of how often fetch was idle. */
486 Stats::Formula idleRate;
487 /** Number of branch fetches per cycle. */
488 Stats::Formula branchRate;
489 /** Number of instruction fetched per cycle. */
490 Stats::Formula fetchRate;
493 #endif //__CPU_O3_FETCH_HH__