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32 #ifndef __CPU_O3_FETCH_HH__
33 #define __CPU_O3_FETCH_HH__
35 #include "arch/utility.hh"
36 #include "base/statistics.hh"
37 #include "base/timebuf.hh"
38 #include "cpu/pc_event.hh"
39 #include "mem/packet_impl.hh"
40 #include "mem/port.hh"
41 #include "sim/eventq.hh"
44 * DefaultFetch class handles both single threaded and SMT fetch. Its
45 * width is specified by the parameters; each cycle it tries to fetch
46 * that many instructions. It supports using a branch predictor to
47 * predict direction and targets.
48 * It supports the idling functionality of the CPU by indicating to
49 * the CPU when it is active and inactive.
55 /** Typedefs from Impl. */
56 typedef typename Impl::CPUPol CPUPol;
57 typedef typename Impl::DynInst DynInst;
58 typedef typename Impl::DynInstPtr DynInstPtr;
59 typedef typename Impl::O3CPU O3CPU;
60 typedef typename Impl::Params Params;
62 /** Typedefs from the CPU policy. */
63 typedef typename CPUPol::BPredUnit BPredUnit;
64 typedef typename CPUPol::FetchStruct FetchStruct;
65 typedef typename CPUPol::TimeStruct TimeStruct;
67 /** Typedefs from ISA. */
68 typedef TheISA::MachInst MachInst;
69 typedef TheISA::ExtMachInst ExtMachInst;
71 /** IcachePort class for DefaultFetch. Handles doing the
72 * communication with the cache/memory.
74 class IcachePort : public Port
77 /** Pointer to fetch. */
78 DefaultFetch<Impl> *fetch;
81 /** Default constructor. */
82 IcachePort(DefaultFetch<Impl> *_fetch)
83 : Port(_fetch->name() + "-iport"), fetch(_fetch)
87 /** Atomic version of receive. Panics. */
88 virtual Tick recvAtomic(PacketPtr pkt);
90 /** Functional version of receive. Panics. */
91 virtual void recvFunctional(PacketPtr pkt);
93 /** Receives status change. Other than range changing, panics. */
94 virtual void recvStatusChange(Status status);
96 /** Returns the address ranges of this device. */
97 virtual void getDeviceAddressRanges(AddrRangeList &resp,
99 { resp.clear(); snoop.clear(); }
101 /** Timing version of receive. Handles setting fetch to the
102 * proper status to start fetching. */
103 virtual bool recvTiming(PacketPtr pkt);
105 /** Handles doing a retry of a failed fetch. */
106 virtual void recvRetry();
110 /** Overall fetch status. Used to determine if the CPU can
111 * deschedule itsef due to a lack of activity.
118 /** Individual thread status. */
133 /** Fetching Policy, Add new policies here.*/
146 /** Per-thread status. */
147 ThreadStatus fetchStatus[Impl::MaxThreads];
150 FetchPriority fetchPolicy;
152 /** List that has the threads organized by priority. */
153 std::list<unsigned> priorityList;
156 /** DefaultFetch constructor. */
157 DefaultFetch(Params *params);
159 /** Returns the name of fetch. */
160 std::string name() const;
162 /** Registers statistics. */
165 /** Sets CPU pointer. */
166 void setCPU(O3CPU *cpu_ptr);
168 /** Sets the main backwards communication time buffer pointer. */
169 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
171 /** Sets pointer to list of active threads. */
172 void setActiveThreads(std::list<unsigned> *at_ptr);
174 /** Sets pointer to time buffer used to communicate to the next stage. */
175 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
177 /** Initialize stage. */
180 /** Processes cache completion event. */
181 void processCacheCompletion(PacketPtr pkt);
183 /** Begins the drain of the fetch stage. */
186 /** Resumes execution after a drain. */
189 /** Tells fetch stage to prepare to be switched out. */
192 /** Takes over from another CPU's thread. */
195 /** Checks if the fetch stage is switched out. */
196 bool isSwitchedOut() { return switchedOut; }
198 /** Tells fetch to wake up from a quiesce instruction. */
199 void wakeFromQuiesce();
202 /** Changes the status of this stage to active, and indicates this
205 inline void switchToActive();
207 /** Changes the status of this stage to inactive, and indicates
210 inline void switchToInactive();
213 * Looks up in the branch predictor to see if the next PC should be
214 * either next PC+=MachInst or a branch target.
215 * @param next_PC Next PC variable passed in by reference. It is
216 * expected to be set to the current PC; it will be updated with what
217 * the next PC will be.
218 * @return Whether or not a branch was predicted as taken.
220 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC);
223 * Fetches the cache line that contains fetch_PC. Returns any
224 * fault that happened. Puts the data into the class variable
226 * @param fetch_PC The PC address that is being fetched from.
227 * @param ret_fault The fault reference that will be set to the result of
229 * @param tid Thread id.
230 * @return Any fault that occured.
232 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
234 /** Squashes a specific thread and resets the PC. */
235 inline void doSquash(const Addr &new_PC, unsigned tid);
237 /** Squashes a specific thread and resets the PC. Also tells the CPU to
238 * remove any instructions between fetch and decode that should be sqaushed.
240 void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
243 /** Checks if a thread is stalled. */
244 bool checkStall(unsigned tid) const;
246 /** Updates overall fetch stage status; to be called at the end of each
248 FetchStatus updateFetchStatus();
251 /** Squashes a specific thread and resets the PC. Also tells the CPU to
252 * remove any instructions that are not in the ROB. The source of this
253 * squash should be the commit stage.
255 void squash(const Addr &new_PC, unsigned tid);
257 /** Ticks the fetch stage, processing all inputs signals and fetching
258 * as many instructions as possible.
262 /** Checks all input signals and updates the status as necessary.
263 * @return: Returns if the status has changed due to input signals.
265 bool checkSignalsAndUpdate(unsigned tid);
267 /** Does the actual fetching of instructions and passing them on to the
269 * @param status_change fetch() sets this variable if there was a status
270 * change (ie switching to IcacheMissStall).
272 void fetch(bool &status_change);
274 /** Align a PC to the start of an I-cache block. */
275 Addr icacheBlockAlignPC(Addr addr)
277 addr = TheISA::realPCToFetchPC(addr);
278 return (addr & ~(cacheBlkMask));
282 /** Handles retrying the fetch access. */
285 /** Returns the appropriate thread to fetch, given the fetch policy. */
286 int getFetchingThread(FetchPriority &fetch_priority);
288 /** Returns the appropriate thread to fetch using a round robin policy. */
291 /** Returns the appropriate thread to fetch using the IQ count policy. */
294 /** Returns the appropriate thread to fetch using the LSQ count policy. */
297 /** Returns the appropriate thread to fetch using the branch count policy. */
301 /** Pointer to the O3CPU. */
304 /** Time buffer interface. */
305 TimeBuffer<TimeStruct> *timeBuffer;
307 /** Wire to get decode's information from backwards time buffer. */
308 typename TimeBuffer<TimeStruct>::wire fromDecode;
310 /** Wire to get rename's information from backwards time buffer. */
311 typename TimeBuffer<TimeStruct>::wire fromRename;
313 /** Wire to get iew's information from backwards time buffer. */
314 typename TimeBuffer<TimeStruct>::wire fromIEW;
316 /** Wire to get commit's information from backwards time buffer. */
317 typename TimeBuffer<TimeStruct>::wire fromCommit;
319 /** Internal fetch instruction queue. */
320 TimeBuffer<FetchStruct> *fetchQueue;
322 //Might be annoying how this name is different than the queue.
323 /** Wire used to write any information heading to decode. */
324 typename TimeBuffer<FetchStruct>::wire toDecode;
328 /** Icache interface. */
329 IcachePort *icachePort;
332 BPredUnit branchPred;
334 /** Per-thread fetch PC. */
335 Addr PC[Impl::MaxThreads];
337 /** Per-thread next PC. */
338 Addr nextPC[Impl::MaxThreads];
340 #if THE_ISA != ALPHA_ISA
341 /** Per-thread next Next PC.
342 * This is not a real register but is used for
343 * architectures that use a branch-delay slot.
344 * (such as MIPS or Sparc)
346 Addr nextNPC[Impl::MaxThreads];
349 /** Memory request used to access cache. */
350 RequestPtr memReq[Impl::MaxThreads];
352 /** Variable that tracks if fetch has written to the time buffer this
353 * cycle. Used to tell CPU if there is activity this cycle.
355 bool wroteToTimeBuffer;
357 /** Tracks how many instructions has been fetched this cycle. */
360 /** Source of possible stalls. */
368 /** Tracks which stages are telling fetch to stall. */
369 Stalls stalls[Impl::MaxThreads];
371 /** Decode to fetch delay, in ticks. */
372 unsigned decodeToFetchDelay;
374 /** Rename to fetch delay, in ticks. */
375 unsigned renameToFetchDelay;
377 /** IEW to fetch delay, in ticks. */
378 unsigned iewToFetchDelay;
380 /** Commit to fetch delay, in ticks. */
381 unsigned commitToFetchDelay;
383 /** The width of fetch in instructions. */
386 /** Is the cache blocked? If so no threads can access it. */
389 /** The packet that is waiting to be retried. */
392 /** The thread that is waiting on the cache to tell fetch to retry. */
395 /** Cache block size. */
398 /** Mask to get a cache block's address. */
401 /** The cache line being fetched. */
402 uint8_t *cacheData[Impl::MaxThreads];
404 /** Size of instructions. */
407 /** Icache stall statistics. */
408 Counter lastIcacheStall[Impl::MaxThreads];
410 /** List of Active Threads */
411 std::list<unsigned> *activeThreads;
413 /** Number of threads. */
416 /** Number of threads that are actively fetching. */
417 unsigned numFetchingThreads;
419 /** Thread ID being fetched. */
422 /** Checks if there is an interrupt pending. If there is, fetch
423 * must stop once it is not fetching PAL instructions.
425 bool interruptPending;
427 /** Is there a drain pending. */
430 /** Records if fetch is switched out. */
433 // @todo: Consider making these vectors and tracking on a per thread basis.
434 /** Stat for total number of cycles stalled due to an icache miss. */
435 Stats::Scalar<> icacheStallCycles;
436 /** Stat for total number of fetched instructions. */
437 Stats::Scalar<> fetchedInsts;
438 /** Total number of fetched branches. */
439 Stats::Scalar<> fetchedBranches;
440 /** Stat for total number of predicted branches. */
441 Stats::Scalar<> predictedBranches;
442 /** Stat for total number of cycles spent fetching. */
443 Stats::Scalar<> fetchCycles;
444 /** Stat for total number of cycles spent squashing. */
445 Stats::Scalar<> fetchSquashCycles;
446 /** Stat for total number of cycles spent blocked due to other stages in
449 Stats::Scalar<> fetchIdleCycles;
450 /** Total number of cycles spent blocked. */
451 Stats::Scalar<> fetchBlockedCycles;
452 /** Total number of cycles spent in any other state. */
453 Stats::Scalar<> fetchMiscStallCycles;
454 /** Stat for total number of fetched cache lines. */
455 Stats::Scalar<> fetchedCacheLines;
456 /** Total number of outstanding icache accesses that were dropped
459 Stats::Scalar<> fetchIcacheSquashes;
460 /** Distribution of number of instructions fetched each cycle. */
461 Stats::Distribution<> fetchNisnDist;
462 /** Rate of how often fetch was idle. */
463 Stats::Formula idleRate;
464 /** Number of branch fetches per cycle. */
465 Stats::Formula branchRate;
466 /** Number of instruction fetched per cycle. */
467 Stats::Formula fetchRate;
470 #endif //__CPU_O3_FETCH_HH__