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32 #ifndef __CPU_O3_FETCH_HH__
33 #define __CPU_O3_FETCH_HH__
35 #include "arch/utility.hh"
36 #include "arch/predecoder.hh"
37 #include "base/statistics.hh"
38 #include "base/timebuf.hh"
39 #include "cpu/pc_event.hh"
40 #include "mem/packet.hh"
41 #include "mem/port.hh"
42 #include "sim/eventq.hh"
45 * DefaultFetch class handles both single threaded and SMT fetch. Its
46 * width is specified by the parameters; each cycle it tries to fetch
47 * that many instructions. It supports using a branch predictor to
48 * predict direction and targets.
49 * It supports the idling functionality of the CPU by indicating to
50 * the CPU when it is active and inactive.
56 /** Typedefs from Impl. */
57 typedef typename Impl::CPUPol CPUPol;
58 typedef typename Impl::DynInst DynInst;
59 typedef typename Impl::DynInstPtr DynInstPtr;
60 typedef typename Impl::O3CPU O3CPU;
61 typedef typename Impl::Params Params;
63 /** Typedefs from the CPU policy. */
64 typedef typename CPUPol::BPredUnit BPredUnit;
65 typedef typename CPUPol::FetchStruct FetchStruct;
66 typedef typename CPUPol::TimeStruct TimeStruct;
68 /** Typedefs from ISA. */
69 typedef TheISA::MachInst MachInst;
70 typedef TheISA::ExtMachInst ExtMachInst;
72 /** IcachePort class for DefaultFetch. Handles doing the
73 * communication with the cache/memory.
75 class IcachePort : public Port
78 /** Pointer to fetch. */
79 DefaultFetch<Impl> *fetch;
82 /** Default constructor. */
83 IcachePort(DefaultFetch<Impl> *_fetch)
84 : Port(_fetch->name() + "-iport"), fetch(_fetch)
89 virtual void setPeer(Port *port);
92 /** Atomic version of receive. Panics. */
93 virtual Tick recvAtomic(PacketPtr pkt);
95 /** Functional version of receive. Panics. */
96 virtual void recvFunctional(PacketPtr pkt);
98 /** Receives status change. Other than range changing, panics. */
99 virtual void recvStatusChange(Status status);
101 /** Returns the address ranges of this device. */
102 virtual void getDeviceAddressRanges(AddrRangeList &resp,
103 AddrRangeList &snoop)
104 { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
106 /** Timing version of receive. Handles setting fetch to the
107 * proper status to start fetching. */
108 virtual bool recvTiming(PacketPtr pkt);
110 /** Handles doing a retry of a failed fetch. */
111 virtual void recvRetry();
116 /** Overall fetch status. Used to determine if the CPU can
117 * deschedule itsef due to a lack of activity.
124 /** Individual thread status. */
139 /** Fetching Policy, Add new policies here.*/
152 /** Per-thread status. */
153 ThreadStatus fetchStatus[Impl::MaxThreads];
156 FetchPriority fetchPolicy;
158 /** List that has the threads organized by priority. */
159 std::list<unsigned> priorityList;
162 /** DefaultFetch constructor. */
163 DefaultFetch(O3CPU *_cpu, Params *params);
165 /** Returns the name of fetch. */
166 std::string name() const;
168 /** Registers statistics. */
171 /** Returns the icache port. */
172 Port *getIcachePort() { return icachePort; }
174 /** Sets the main backwards communication time buffer pointer. */
175 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
177 /** Sets pointer to list of active threads. */
178 void setActiveThreads(std::list<unsigned> *at_ptr);
180 /** Sets pointer to time buffer used to communicate to the next stage. */
181 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
183 /** Initialize stage. */
186 /** Tells the fetch stage that the Icache is set. */
189 /** Processes cache completion event. */
190 void processCacheCompletion(PacketPtr pkt);
192 /** Begins the drain of the fetch stage. */
195 /** Resumes execution after a drain. */
198 /** Tells fetch stage to prepare to be switched out. */
201 /** Takes over from another CPU's thread. */
204 /** Checks if the fetch stage is switched out. */
205 bool isSwitchedOut() { return switchedOut; }
207 /** Tells fetch to wake up from a quiesce instruction. */
208 void wakeFromQuiesce();
211 /** Changes the status of this stage to active, and indicates this
214 inline void switchToActive();
216 /** Changes the status of this stage to inactive, and indicates
219 inline void switchToInactive();
222 * Looks up in the branch predictor to see if the next PC should be
223 * either next PC+=MachInst or a branch target.
224 * @param next_PC Next PC variable passed in by reference. It is
225 * expected to be set to the current PC; it will be updated with what
226 * the next PC will be.
227 * @param next_NPC Used for ISAs which use delay slots.
228 * @return Whether or not a branch was predicted as taken.
230 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC);
233 * Fetches the cache line that contains fetch_PC. Returns any
234 * fault that happened. Puts the data into the class variable
236 * @param fetch_PC The PC address that is being fetched from.
237 * @param ret_fault The fault reference that will be set to the result of
239 * @param tid Thread id.
240 * @return Any fault that occured.
242 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
244 /** Squashes a specific thread and resets the PC. */
245 inline void doSquash(const Addr &new_PC, const Addr &new_NPC, unsigned tid);
247 /** Squashes a specific thread and resets the PC. Also tells the CPU to
248 * remove any instructions between fetch and decode that should be sqaushed.
250 void squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
251 const InstSeqNum &seq_num, unsigned tid);
253 /** Checks if a thread is stalled. */
254 bool checkStall(unsigned tid) const;
256 /** Updates overall fetch stage status; to be called at the end of each
258 FetchStatus updateFetchStatus();
261 /** Squashes a specific thread and resets the PC. Also tells the CPU to
262 * remove any instructions that are not in the ROB. The source of this
263 * squash should be the commit stage.
265 void squash(const Addr &new_PC, const Addr &new_NPC,
266 const InstSeqNum &seq_num,
267 bool squash_delay_slot, unsigned tid);
269 /** Ticks the fetch stage, processing all inputs signals and fetching
270 * as many instructions as possible.
274 /** Checks all input signals and updates the status as necessary.
275 * @return: Returns if the status has changed due to input signals.
277 bool checkSignalsAndUpdate(unsigned tid);
279 /** Does the actual fetching of instructions and passing them on to the
281 * @param status_change fetch() sets this variable if there was a status
282 * change (ie switching to IcacheMissStall).
284 void fetch(bool &status_change);
286 /** Align a PC to the start of an I-cache block. */
287 Addr icacheBlockAlignPC(Addr addr)
289 addr = TheISA::realPCToFetchPC(addr);
290 return (addr & ~(cacheBlkMask));
294 /** Handles retrying the fetch access. */
297 /** Returns the appropriate thread to fetch, given the fetch policy. */
298 int getFetchingThread(FetchPriority &fetch_priority);
300 /** Returns the appropriate thread to fetch using a round robin policy. */
303 /** Returns the appropriate thread to fetch using the IQ count policy. */
306 /** Returns the appropriate thread to fetch using the LSQ count policy. */
309 /** Returns the appropriate thread to fetch using the branch count policy. */
313 /** Pointer to the O3CPU. */
316 /** Time buffer interface. */
317 TimeBuffer<TimeStruct> *timeBuffer;
319 /** Wire to get decode's information from backwards time buffer. */
320 typename TimeBuffer<TimeStruct>::wire fromDecode;
322 /** Wire to get rename's information from backwards time buffer. */
323 typename TimeBuffer<TimeStruct>::wire fromRename;
325 /** Wire to get iew's information from backwards time buffer. */
326 typename TimeBuffer<TimeStruct>::wire fromIEW;
328 /** Wire to get commit's information from backwards time buffer. */
329 typename TimeBuffer<TimeStruct>::wire fromCommit;
331 /** Internal fetch instruction queue. */
332 TimeBuffer<FetchStruct> *fetchQueue;
334 //Might be annoying how this name is different than the queue.
335 /** Wire used to write any information heading to decode. */
336 typename TimeBuffer<FetchStruct>::wire toDecode;
338 /** Icache interface. */
339 IcachePort *icachePort;
342 BPredUnit branchPred;
345 TheISA::Predecoder predecoder;
347 /** Per-thread fetch PC. */
348 Addr PC[Impl::MaxThreads];
350 /** Per-thread next PC. */
351 Addr nextPC[Impl::MaxThreads];
353 /** Per-thread next Next PC.
354 * This is not a real register but is used for
355 * architectures that use a branch-delay slot.
356 * (such as MIPS or Sparc)
358 Addr nextNPC[Impl::MaxThreads];
360 /** Memory request used to access cache. */
361 RequestPtr memReq[Impl::MaxThreads];
363 /** Variable that tracks if fetch has written to the time buffer this
364 * cycle. Used to tell CPU if there is activity this cycle.
366 bool wroteToTimeBuffer;
368 /** Tracks how many instructions has been fetched this cycle. */
371 /** Source of possible stalls. */
379 /** Tracks which stages are telling fetch to stall. */
380 Stalls stalls[Impl::MaxThreads];
382 /** Decode to fetch delay, in ticks. */
383 unsigned decodeToFetchDelay;
385 /** Rename to fetch delay, in ticks. */
386 unsigned renameToFetchDelay;
388 /** IEW to fetch delay, in ticks. */
389 unsigned iewToFetchDelay;
391 /** Commit to fetch delay, in ticks. */
392 unsigned commitToFetchDelay;
394 /** The width of fetch in instructions. */
397 /** Is the cache blocked? If so no threads can access it. */
400 /** The packet that is waiting to be retried. */
403 /** The thread that is waiting on the cache to tell fetch to retry. */
406 /** Cache block size. */
409 /** Mask to get a cache block's address. */
412 /** The cache line being fetched. */
413 uint8_t *cacheData[Impl::MaxThreads];
415 /** The PC of the cacheline that has been loaded. */
416 Addr cacheDataPC[Impl::MaxThreads];
418 /** Whether or not the cache data is valid. */
419 bool cacheDataValid[Impl::MaxThreads];
421 /** Size of instructions. */
424 /** Icache stall statistics. */
425 Counter lastIcacheStall[Impl::MaxThreads];
427 /** List of Active Threads */
428 std::list<unsigned> *activeThreads;
430 /** Number of threads. */
433 /** Number of threads that are actively fetching. */
434 unsigned numFetchingThreads;
436 /** Thread ID being fetched. */
439 /** Checks if there is an interrupt pending. If there is, fetch
440 * must stop once it is not fetching PAL instructions.
442 bool interruptPending;
444 /** Is there a drain pending. */
447 /** Records if fetch is switched out. */
450 // @todo: Consider making these vectors and tracking on a per thread basis.
451 /** Stat for total number of cycles stalled due to an icache miss. */
452 Stats::Scalar<> icacheStallCycles;
453 /** Stat for total number of fetched instructions. */
454 Stats::Scalar<> fetchedInsts;
455 /** Total number of fetched branches. */
456 Stats::Scalar<> fetchedBranches;
457 /** Stat for total number of predicted branches. */
458 Stats::Scalar<> predictedBranches;
459 /** Stat for total number of cycles spent fetching. */
460 Stats::Scalar<> fetchCycles;
461 /** Stat for total number of cycles spent squashing. */
462 Stats::Scalar<> fetchSquashCycles;
463 /** Stat for total number of cycles spent blocked due to other stages in
466 Stats::Scalar<> fetchIdleCycles;
467 /** Total number of cycles spent blocked. */
468 Stats::Scalar<> fetchBlockedCycles;
469 /** Total number of cycles spent in any other state. */
470 Stats::Scalar<> fetchMiscStallCycles;
471 /** Stat for total number of fetched cache lines. */
472 Stats::Scalar<> fetchedCacheLines;
473 /** Total number of outstanding icache accesses that were dropped
476 Stats::Scalar<> fetchIcacheSquashes;
477 /** Distribution of number of instructions fetched each cycle. */
478 Stats::Distribution<> fetchNisnDist;
479 /** Rate of how often fetch was idle. */
480 Stats::Formula idleRate;
481 /** Number of branch fetches per cycle. */
482 Stats::Formula branchRate;
483 /** Number of instruction fetched per cycle. */
484 Stats::Formula fetchRate;
487 #endif //__CPU_O3_FETCH_HH__