2 * Copyright (c) 2010-2011 ARM Limited
5 * The license below extends only to copyright in the software and shall
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50 #include "arch/isa_traits.hh"
51 #include "arch/tlb.hh"
52 #include "arch/utility.hh"
53 #include "arch/vtophys.hh"
54 #include "base/types.hh"
55 #include "config/the_isa.hh"
56 #include "cpu/base.hh"
57 //#include "cpu/checker/cpu.hh"
58 #include "cpu/o3/fetch.hh"
59 #include "cpu/exetrace.hh"
60 #include "debug/Activity.hh"
61 #include "debug/Fetch.hh"
62 #include "mem/packet.hh"
63 #include "params/DerivO3CPU.hh"
64 #include "sim/byteswap.hh"
65 #include "sim/core.hh"
66 #include "sim/eventq.hh"
67 #include "sim/full_system.hh"
68 #include "sim/system.hh"
73 DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
77 decodeToFetchDelay(params->decodeToFetchDelay),
78 renameToFetchDelay(params->renameToFetchDelay),
79 iewToFetchDelay(params->iewToFetchDelay),
80 commitToFetchDelay(params->commitToFetchDelay),
81 fetchWidth(params->fetchWidth),
84 retryTid(InvalidThreadID),
85 numThreads(params->numThreads),
86 numFetchingThreads(params->smtNumFetchingThreads),
87 interruptPending(false),
90 finishTranslationEvent(this)
92 if (numThreads > Impl::MaxThreads)
93 fatal("numThreads (%d) is larger than compiled limit (%d),\n"
94 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n",
95 numThreads, static_cast<int>(Impl::MaxThreads));
96 if (fetchWidth > Impl::MaxWidth)
97 fatal("fetchWidth (%d) is larger than compiled limit (%d),\n"
98 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
99 fetchWidth, static_cast<int>(Impl::MaxWidth));
101 // Set fetch stage's status to inactive.
104 std::string policy = params->smtFetchPolicy;
106 // Convert string to lowercase
107 std::transform(policy.begin(), policy.end(), policy.begin(),
108 (int(*)(int)) tolower);
110 // Figure out fetch policy
111 if (policy == "singlethread") {
112 fetchPolicy = SingleThread;
114 panic("Invalid Fetch Policy for a SMT workload.");
115 } else if (policy == "roundrobin") {
116 fetchPolicy = RoundRobin;
117 DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
118 } else if (policy == "branch") {
119 fetchPolicy = Branch;
120 DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
121 } else if (policy == "iqcount") {
123 DPRINTF(Fetch, "Fetch policy set to IQ count\n");
124 } else if (policy == "lsqcount") {
126 DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
128 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
129 " RoundRobin,LSQcount,IQcount}\n");
132 // Get the size of an instruction.
133 instSize = sizeof(TheISA::MachInst);
135 for (int i = 0; i < Impl::MaxThreads; i++) {
137 decoder[i] = new TheISA::Decoder(NULL);
141 template <class Impl>
143 DefaultFetch<Impl>::name() const
145 return cpu->name() + ".fetch";
148 template <class Impl>
150 DefaultFetch<Impl>::regStats()
153 .name(name() + ".icacheStallCycles")
154 .desc("Number of cycles fetch is stalled on an Icache miss")
155 .prereq(icacheStallCycles);
158 .name(name() + ".Insts")
159 .desc("Number of instructions fetch has processed")
160 .prereq(fetchedInsts);
163 .name(name() + ".Branches")
164 .desc("Number of branches that fetch encountered")
165 .prereq(fetchedBranches);
168 .name(name() + ".predictedBranches")
169 .desc("Number of branches that fetch has predicted taken")
170 .prereq(predictedBranches);
173 .name(name() + ".Cycles")
174 .desc("Number of cycles fetch has run and was not squashing or"
176 .prereq(fetchCycles);
179 .name(name() + ".SquashCycles")
180 .desc("Number of cycles fetch has spent squashing")
181 .prereq(fetchSquashCycles);
184 .name(name() + ".TlbCycles")
185 .desc("Number of cycles fetch has spent waiting for tlb")
186 .prereq(fetchTlbCycles);
189 .name(name() + ".IdleCycles")
190 .desc("Number of cycles fetch was idle")
191 .prereq(fetchIdleCycles);
194 .name(name() + ".BlockedCycles")
195 .desc("Number of cycles fetch has spent blocked")
196 .prereq(fetchBlockedCycles);
199 .name(name() + ".CacheLines")
200 .desc("Number of cache lines fetched")
201 .prereq(fetchedCacheLines);
204 .name(name() + ".MiscStallCycles")
205 .desc("Number of cycles fetch has spent waiting on interrupts, or "
206 "bad addresses, or out of MSHRs")
207 .prereq(fetchMiscStallCycles);
209 fetchPendingDrainCycles
210 .name(name() + ".PendingDrainCycles")
211 .desc("Number of cycles fetch has spent waiting on pipes to drain")
212 .prereq(fetchPendingDrainCycles);
214 fetchNoActiveThreadStallCycles
215 .name(name() + ".NoActiveThreadStallCycles")
216 .desc("Number of stall cycles due to no active thread to fetch from")
217 .prereq(fetchNoActiveThreadStallCycles);
219 fetchPendingTrapStallCycles
220 .name(name() + ".PendingTrapStallCycles")
221 .desc("Number of stall cycles due to pending traps")
222 .prereq(fetchPendingTrapStallCycles);
224 fetchPendingQuiesceStallCycles
225 .name(name() + ".PendingQuiesceStallCycles")
226 .desc("Number of stall cycles due to pending quiesce instructions")
227 .prereq(fetchPendingQuiesceStallCycles);
229 fetchIcacheWaitRetryStallCycles
230 .name(name() + ".IcacheWaitRetryStallCycles")
231 .desc("Number of stall cycles due to full MSHR")
232 .prereq(fetchIcacheWaitRetryStallCycles);
235 .name(name() + ".IcacheSquashes")
236 .desc("Number of outstanding Icache misses that were squashed")
237 .prereq(fetchIcacheSquashes);
240 .name(name() + ".ItlbSquashes")
241 .desc("Number of outstanding ITLB misses that were squashed")
242 .prereq(fetchTlbSquashes);
245 .init(/* base value */ 0,
246 /* last value */ fetchWidth,
248 .name(name() + ".rateDist")
249 .desc("Number of instructions fetched each cycle (Total)")
253 .name(name() + ".idleRate")
254 .desc("Percent of cycles fetch was idle")
256 idleRate = fetchIdleCycles * 100 / cpu->numCycles;
259 .name(name() + ".branchRate")
260 .desc("Number of branch fetches per cycle")
261 .flags(Stats::total);
262 branchRate = fetchedBranches / cpu->numCycles;
265 .name(name() + ".rate")
266 .desc("Number of inst fetches per cycle")
267 .flags(Stats::total);
268 fetchRate = fetchedInsts / cpu->numCycles;
270 branchPred.regStats();
275 DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
277 timeBuffer = time_buffer;
279 // Create wires to get information from proper places in time buffer.
280 fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
281 fromRename = timeBuffer->getWire(-renameToFetchDelay);
282 fromIEW = timeBuffer->getWire(-iewToFetchDelay);
283 fromCommit = timeBuffer->getWire(-commitToFetchDelay);
288 DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
290 activeThreads = at_ptr;
295 DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
299 // Create wire to write information to proper place in fetch queue.
300 toDecode = fetchQueue->getWire(0);
305 DefaultFetch<Impl>::initStage()
307 // Setup PC and nextPC with initial state.
308 for (ThreadID tid = 0; tid < numThreads; tid++) {
309 pc[tid] = cpu->pcState(tid);
310 fetchOffset[tid] = 0;
312 delayedCommit[tid] = false;
315 for (ThreadID tid = 0; tid < numThreads; tid++) {
317 fetchStatus[tid] = Running;
319 priorityList.push_back(tid);
323 stalls[tid].decode = false;
324 stalls[tid].rename = false;
325 stalls[tid].iew = false;
326 stalls[tid].commit = false;
329 // Schedule fetch to get the correct PC from the CPU
330 // scheduleFetchStartupEvent(1);
332 // Fetch needs to start fetching instructions at the very beginning,
333 // so it must start up in active state.
339 DefaultFetch<Impl>::setIcache()
341 assert(cpu->getInstPort().isConnected());
343 // Size of cache block.
344 cacheBlkSize = cpu->getInstPort().peerBlockSize();
346 // Create mask to get rid of offset bits.
347 cacheBlkMask = (cacheBlkSize - 1);
349 for (ThreadID tid = 0; tid < numThreads; tid++) {
350 // Create space to store a cache line.
352 cacheData[tid] = new uint8_t[cacheBlkSize];
353 cacheDataPC[tid] = 0;
354 cacheDataValid[tid] = false;
360 DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
362 ThreadID tid = pkt->req->threadId();
364 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid);
366 // Only change the status if it's still waiting on the icache access
368 if (fetchStatus[tid] != IcacheWaitResponse ||
369 pkt->req != memReq[tid] ||
371 ++fetchIcacheSquashes;
377 memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
378 cacheDataValid[tid] = true;
381 // Wake up the CPU (if it went to sleep and was waiting on
382 // this completion event).
385 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
391 // Only switch to IcacheAccessComplete if we're not stalled as well.
392 if (checkStall(tid)) {
393 fetchStatus[tid] = Blocked;
395 fetchStatus[tid] = IcacheAccessComplete;
398 // Reset the mem req to NULL.
404 template <class Impl>
406 DefaultFetch<Impl>::drain()
408 // Fetch is ready to drain at any time.
409 cpu->signalDrained();
414 template <class Impl>
416 DefaultFetch<Impl>::resume()
418 drainPending = false;
421 template <class Impl>
423 DefaultFetch<Impl>::switchOut()
426 // Branch predictor needs to have its state cleared.
427 branchPred.switchOut();
430 template <class Impl>
432 DefaultFetch<Impl>::takeOverFrom()
434 // the instruction port is now connected so we can get the block
439 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
440 stalls[i].decode = 0;
441 stalls[i].rename = 0;
443 stalls[i].commit = 0;
444 pc[i] = cpu->pcState(i);
445 fetchStatus[i] = Running;
448 wroteToTimeBuffer = false;
451 interruptPending = false;
452 branchPred.takeOverFrom();
455 template <class Impl>
457 DefaultFetch<Impl>::wakeFromQuiesce()
459 DPRINTF(Fetch, "Waking up from quiesce\n");
460 // Hopefully this is safe
461 // @todo: Allow other threads to wake from quiesce.
462 fetchStatus[0] = Running;
465 template <class Impl>
467 DefaultFetch<Impl>::switchToActive()
469 if (_status == Inactive) {
470 DPRINTF(Activity, "Activating stage.\n");
472 cpu->activateStage(O3CPU::FetchIdx);
478 template <class Impl>
480 DefaultFetch<Impl>::switchToInactive()
482 if (_status == Active) {
483 DPRINTF(Activity, "Deactivating stage.\n");
485 cpu->deactivateStage(O3CPU::FetchIdx);
491 template <class Impl>
493 DefaultFetch<Impl>::lookupAndUpdateNextPC(
494 DynInstPtr &inst, TheISA::PCState &nextPC)
496 // Do branch prediction check here.
497 // A bit of a misnomer...next_PC is actually the current PC until
498 // this function updates it.
501 if (!inst->isControl()) {
502 TheISA::advancePC(nextPC, inst->staticInst);
503 inst->setPredTarg(nextPC);
504 inst->setPredTaken(false);
508 ThreadID tid = inst->threadNumber;
509 predict_taken = branchPred.predict(inst, nextPC, tid);
512 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n",
513 tid, inst->seqNum, nextPC);
515 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
519 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n",
520 tid, inst->seqNum, nextPC);
521 inst->setPredTarg(nextPC);
522 inst->setPredTaken(predict_taken);
530 return predict_taken;
533 template <class Impl>
535 DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
537 Fault fault = NoFault;
539 // @todo: not sure if these should block translation.
542 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
545 } else if (isSwitchedOut()) {
546 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
549 } else if (checkInterrupt(pc) && !delayedCommit[tid]) {
550 // Hold off fetch from getting new instructions when:
551 // Cache is blocked, or
552 // while an interrupt is pending and we're not in PAL mode, or
553 // fetch is switched out.
554 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
559 // Align the fetch address so it's at the start of a cache block.
560 Addr block_PC = icacheBlockAlignPC(vaddr);
562 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n",
563 tid, block_PC, vaddr);
565 // Setup the memReq to do a read of the first instruction's address.
566 // Set the appropriate read size and flags as well.
567 // Build request here.
569 new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
570 cpu->instMasterId(), pc, cpu->thread[tid]->contextId(), tid);
572 memReq[tid] = mem_req;
574 // Initiate translation of the icache block
575 fetchStatus[tid] = ItlbWait;
576 FetchTranslation *trans = new FetchTranslation(this);
577 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(),
578 trans, BaseTLB::Execute);
582 template <class Impl>
584 DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
586 ThreadID tid = mem_req->threadId();
587 Addr block_PC = mem_req->getVaddr();
589 // Wake up CPU if it was idle
592 if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] ||
593 mem_req->getVaddr() != memReq[tid]->getVaddr() || isSwitchedOut()) {
594 DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n",
602 // If translation was successful, attempt to read the icache block.
603 if (fault == NoFault) {
604 // Check that we're not going off into random memory
605 // If we have, just wait around for commit to squash something and put
606 // us on the right track
607 if (!cpu->system->isMemAddr(mem_req->getPaddr())) {
608 warn("Address %#x is outside of physical memory, stopping fetch\n",
609 mem_req->getPaddr());
610 fetchStatus[tid] = NoGoodAddr;
616 // Build packet here.
617 PacketPtr data_pkt = new Packet(mem_req, MemCmd::ReadReq);
618 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
620 cacheDataPC[tid] = block_PC;
621 cacheDataValid[tid] = false;
622 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
627 if (!cpu->getInstPort().sendTimingReq(data_pkt)) {
628 assert(retryPkt == NULL);
629 assert(retryTid == InvalidThreadID);
630 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
632 fetchStatus[tid] = IcacheWaitRetry;
637 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
638 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
641 lastIcacheStall[tid] = curTick();
642 fetchStatus[tid] = IcacheWaitResponse;
645 if (!(numInst < fetchWidth)) {
646 assert(!finishTranslationEvent.scheduled());
647 finishTranslationEvent.setFault(fault);
648 finishTranslationEvent.setReq(mem_req);
649 cpu->schedule(finishTranslationEvent,
650 cpu->clockEdge(Cycles(1)));
653 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n",
654 tid, mem_req->getVaddr(), memReq[tid]->getVaddr());
655 // Translation faulted, icache request won't be sent.
659 // Send the fault to commit. This thread will not do anything
660 // until commit handles the fault. The only other way it can
661 // wake up is if a squash comes along and changes the PC.
662 TheISA::PCState fetchPC = pc[tid];
664 DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid);
665 // We will use a nop in ordier to carry the fault.
666 DynInstPtr instruction = buildInst(tid,
667 decoder[tid]->decode(TheISA::NoopMachInst, fetchPC.instAddr()),
668 NULL, fetchPC, fetchPC, false);
670 instruction->setPredTarg(fetchPC);
671 instruction->fault = fault;
672 wroteToTimeBuffer = true;
674 DPRINTF(Activity, "Activity this cycle.\n");
675 cpu->activityThisCycle();
677 fetchStatus[tid] = TrapPending;
679 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid);
680 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n",
681 tid, fault->name(), pc[tid]);
683 _status = updateFetchStatus();
686 template <class Impl>
688 DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC,
689 const DynInstPtr squashInst, ThreadID tid)
691 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
695 fetchOffset[tid] = 0;
696 if (squashInst && squashInst->pcState().instAddr() == newPC.instAddr())
697 macroop[tid] = squashInst->macroop;
700 decoder[tid]->reset();
702 // Clear the icache miss if it's outstanding.
703 if (fetchStatus[tid] == IcacheWaitResponse) {
704 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
707 } else if (fetchStatus[tid] == ItlbWait) {
708 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n",
713 // Get rid of the retrying packet if it was from this thread.
714 if (retryTid == tid) {
715 assert(cacheBlocked);
717 delete retryPkt->req;
721 retryTid = InvalidThreadID;
724 fetchStatus[tid] = Squashing;
726 // microops are being squashed, it is not known wheather the
727 // youngest non-squashed microop was marked delayed commit
728 // or not. Setting the flag to true ensures that the
729 // interrupts are not handled when they cannot be, though
730 // some opportunities to handle interrupts may be missed.
731 delayedCommit[tid] = true;
738 DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
739 const DynInstPtr squashInst,
740 const InstSeqNum seq_num, ThreadID tid)
742 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
744 doSquash(newPC, squashInst, tid);
746 // Tell the CPU to remove any instructions that are in flight between
748 cpu->removeInstsUntil(seq_num, tid);
753 DefaultFetch<Impl>::checkStall(ThreadID tid) const
755 bool ret_val = false;
757 if (cpu->contextSwitch) {
758 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
760 } else if (stalls[tid].decode) {
761 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
763 } else if (stalls[tid].rename) {
764 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
766 } else if (stalls[tid].iew) {
767 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
769 } else if (stalls[tid].commit) {
770 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
778 typename DefaultFetch<Impl>::FetchStatus
779 DefaultFetch<Impl>::updateFetchStatus()
782 list<ThreadID>::iterator threads = activeThreads->begin();
783 list<ThreadID>::iterator end = activeThreads->end();
785 while (threads != end) {
786 ThreadID tid = *threads++;
788 if (fetchStatus[tid] == Running ||
789 fetchStatus[tid] == Squashing ||
790 fetchStatus[tid] == IcacheAccessComplete) {
792 if (_status == Inactive) {
793 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
795 if (fetchStatus[tid] == IcacheAccessComplete) {
796 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
800 cpu->activateStage(O3CPU::FetchIdx);
807 // Stage is switching from active to inactive, notify CPU of it.
808 if (_status == Active) {
809 DPRINTF(Activity, "Deactivating stage.\n");
811 cpu->deactivateStage(O3CPU::FetchIdx);
817 template <class Impl>
819 DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
820 const InstSeqNum seq_num, DynInstPtr squashInst,
823 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
825 doSquash(newPC, squashInst, tid);
827 // Tell the CPU to remove any instructions that are not in the ROB.
828 cpu->removeInstsNotInROB(tid);
831 template <class Impl>
833 DefaultFetch<Impl>::tick()
835 list<ThreadID>::iterator threads = activeThreads->begin();
836 list<ThreadID>::iterator end = activeThreads->end();
837 bool status_change = false;
839 wroteToTimeBuffer = false;
841 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
842 issuePipelinedIfetch[i] = false;
845 while (threads != end) {
846 ThreadID tid = *threads++;
848 // Check the signals for each thread to determine the proper status
850 bool updated_status = checkSignalsAndUpdate(tid);
851 status_change = status_change || updated_status;
854 DPRINTF(Fetch, "Running stage.\n");
857 if (fromCommit->commitInfo[0].interruptPending) {
858 interruptPending = true;
861 if (fromCommit->commitInfo[0].clearInterrupt) {
862 interruptPending = false;
866 for (threadFetched = 0; threadFetched < numFetchingThreads;
868 // Fetch each of the actively fetching threads.
869 fetch(status_change);
872 // Record number of instructions fetched this cycle for distribution.
873 fetchNisnDist.sample(numInst);
876 // Change the fetch stage status if there was a status change.
877 _status = updateFetchStatus();
880 // If there was activity this cycle, inform the CPU of it.
881 if (wroteToTimeBuffer || cpu->contextSwitch) {
882 DPRINTF(Activity, "Activity this cycle.\n");
884 cpu->activityThisCycle();
887 // Issue the next I-cache request if possible.
888 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
889 if (issuePipelinedIfetch[i]) {
890 pipelineIcacheAccesses(i);
894 // Reset the number of the instruction we've fetched.
898 template <class Impl>
900 DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
902 // Update the per thread stall statuses.
903 if (fromDecode->decodeBlock[tid]) {
904 stalls[tid].decode = true;
907 if (fromDecode->decodeUnblock[tid]) {
908 assert(stalls[tid].decode);
909 assert(!fromDecode->decodeBlock[tid]);
910 stalls[tid].decode = false;
913 if (fromRename->renameBlock[tid]) {
914 stalls[tid].rename = true;
917 if (fromRename->renameUnblock[tid]) {
918 assert(stalls[tid].rename);
919 assert(!fromRename->renameBlock[tid]);
920 stalls[tid].rename = false;
923 if (fromIEW->iewBlock[tid]) {
924 stalls[tid].iew = true;
927 if (fromIEW->iewUnblock[tid]) {
928 assert(stalls[tid].iew);
929 assert(!fromIEW->iewBlock[tid]);
930 stalls[tid].iew = false;
933 if (fromCommit->commitBlock[tid]) {
934 stalls[tid].commit = true;
937 if (fromCommit->commitUnblock[tid]) {
938 assert(stalls[tid].commit);
939 assert(!fromCommit->commitBlock[tid]);
940 stalls[tid].commit = false;
943 // Check squash signals from commit.
944 if (fromCommit->commitInfo[tid].squash) {
946 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
947 "from commit.\n",tid);
948 // In any case, squash.
949 squash(fromCommit->commitInfo[tid].pc,
950 fromCommit->commitInfo[tid].doneSeqNum,
951 fromCommit->commitInfo[tid].squashInst, tid);
953 // If it was a branch mispredict on a control instruction, update the
954 // branch predictor with that instruction, otherwise just kill the
955 // invalid state we generated in after sequence number
956 if (fromCommit->commitInfo[tid].mispredictInst &&
957 fromCommit->commitInfo[tid].mispredictInst->isControl()) {
958 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
959 fromCommit->commitInfo[tid].pc,
960 fromCommit->commitInfo[tid].branchTaken,
963 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
968 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
969 // Update the branch predictor if it wasn't a squashed instruction
970 // that was broadcasted.
971 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
974 // Check ROB squash signals from commit.
975 if (fromCommit->commitInfo[tid].robSquashing) {
976 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
978 // Continue to squash.
979 fetchStatus[tid] = Squashing;
984 // Check squash signals from decode.
985 if (fromDecode->decodeInfo[tid].squash) {
986 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
987 "from decode.\n",tid);
989 // Update the branch predictor.
990 if (fromDecode->decodeInfo[tid].branchMispredict) {
991 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
992 fromDecode->decodeInfo[tid].nextPC,
993 fromDecode->decodeInfo[tid].branchTaken,
996 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
1000 if (fetchStatus[tid] != Squashing) {
1002 DPRINTF(Fetch, "Squashing from decode with PC = %s\n",
1003 fromDecode->decodeInfo[tid].nextPC);
1004 // Squash unless we're already squashing
1005 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
1006 fromDecode->decodeInfo[tid].squashInst,
1007 fromDecode->decodeInfo[tid].doneSeqNum,
1014 if (checkStall(tid) &&
1015 fetchStatus[tid] != IcacheWaitResponse &&
1016 fetchStatus[tid] != IcacheWaitRetry) {
1017 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
1019 fetchStatus[tid] = Blocked;
1024 if (fetchStatus[tid] == Blocked ||
1025 fetchStatus[tid] == Squashing) {
1026 // Switch status to running if fetch isn't being told to block or
1027 // squash this cycle.
1028 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
1031 fetchStatus[tid] = Running;
1036 // If we've reached this point, we have not gotten any signals that
1037 // cause fetch to change its status. Fetch remains the same as before.
1041 template<class Impl>
1042 typename Impl::DynInstPtr
1043 DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst,
1044 StaticInstPtr curMacroop, TheISA::PCState thisPC,
1045 TheISA::PCState nextPC, bool trace)
1047 // Get a sequence number.
1048 InstSeqNum seq = cpu->getAndIncrementInstSeq();
1050 // Create a new DynInst from the instruction fetched.
1051 DynInstPtr instruction =
1052 new DynInst(staticInst, curMacroop, thisPC, nextPC, seq, cpu);
1053 instruction->setTid(tid);
1055 instruction->setASID(tid);
1057 instruction->setThreadState(cpu->thread[tid]);
1059 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
1060 "[sn:%lli].\n", tid, thisPC.instAddr(),
1061 thisPC.microPC(), seq);
1063 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid,
1064 instruction->staticInst->
1065 disassemble(thisPC.instAddr()));
1069 instruction->traceData =
1070 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid),
1071 instruction->staticInst, thisPC, curMacroop);
1074 instruction->traceData = NULL;
1077 // Add instruction to the CPU's list of instructions.
1078 instruction->setInstListIt(cpu->addInst(instruction));
1080 // Write the instruction to the first slot in the queue
1081 // that heads to decode.
1082 assert(numInst < fetchWidth);
1083 toDecode->insts[toDecode->size++] = instruction;
1085 // Keep track of if we can take an interrupt at this boundary
1086 delayedCommit[tid] = instruction->isDelayedCommit();
1091 template<class Impl>
1093 DefaultFetch<Impl>::fetch(bool &status_change)
1095 //////////////////////////////////////////
1096 // Start actual fetch
1097 //////////////////////////////////////////
1098 ThreadID tid = getFetchingThread(fetchPolicy);
1100 if (tid == InvalidThreadID || drainPending) {
1101 // Breaks looping condition in tick()
1102 threadFetched = numFetchingThreads;
1104 if (numThreads == 1) { // @todo Per-thread stats
1111 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1114 TheISA::PCState thisPC = pc[tid];
1116 Addr pcOffset = fetchOffset[tid];
1117 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1119 bool inRom = isRomMicroPC(thisPC.microPC());
1121 // If returning from the delay of a cache miss, then update the status
1122 // to running, otherwise do the cache access. Possibly move this up
1123 // to tick() function.
1124 if (fetchStatus[tid] == IcacheAccessComplete) {
1125 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid);
1127 fetchStatus[tid] = Running;
1128 status_change = true;
1129 } else if (fetchStatus[tid] == Running) {
1130 // Align the fetch PC so its at the start of a cache block.
1131 Addr block_PC = icacheBlockAlignPC(fetchAddr);
1133 // If buffer is no longer valid or fetchAddr has moved to point
1134 // to the next cache block, AND we have no remaining ucode
1135 // from a macro-op, then start fetch from icache.
1136 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid])
1137 && !inRom && !macroop[tid]) {
1138 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1139 "instruction, starting at PC %s.\n", tid, thisPC);
1141 fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1143 if (fetchStatus[tid] == IcacheWaitResponse)
1144 ++icacheStallCycles;
1145 else if (fetchStatus[tid] == ItlbWait)
1148 ++fetchMiscStallCycles;
1150 } else if ((checkInterrupt(thisPC.instAddr()) && !delayedCommit[tid])
1151 || isSwitchedOut()) {
1152 // Stall CPU if an interrupt is posted and we're not issuing
1153 // an delayed commit micro-op currently (delayed commit instructions
1154 // are not interruptable by interrupts, only faults)
1155 ++fetchMiscStallCycles;
1156 DPRINTF(Fetch, "[tid:%i]: Fetch is stalled!\n", tid);
1160 if (fetchStatus[tid] == Idle) {
1162 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1165 // Status is Idle, so fetch should do nothing.
1171 TheISA::PCState nextPC = thisPC;
1173 StaticInstPtr staticInst = NULL;
1174 StaticInstPtr curMacroop = macroop[tid];
1176 // If the read of the first instruction was successful, then grab the
1177 // instructions from the rest of the cache line and put them into the
1178 // queue heading to decode.
1180 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1183 // Need to keep track of whether or not a predicted branch
1184 // ended this fetch block.
1185 bool predictedBranch = false;
1187 TheISA::MachInst *cacheInsts =
1188 reinterpret_cast<TheISA::MachInst *>(cacheData[tid]);
1190 const unsigned numInsts = cacheBlkSize / instSize;
1191 unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
1193 // Loop through instruction memory from the cache.
1194 // Keep issuing while fetchWidth is available and branch is not
1196 while (numInst < fetchWidth && !predictedBranch) {
1198 // We need to process more memory if we aren't going to get a
1199 // StaticInst from the rom, the current macroop, or what's already
1201 bool needMem = !inRom && !curMacroop &&
1202 !decoder[tid]->instReady();
1203 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1204 Addr block_PC = icacheBlockAlignPC(fetchAddr);
1207 // If buffer is no longer valid or fetchAddr has moved to point
1208 // to the next cache block then start fetch from icache.
1209 if (!cacheDataValid[tid] || block_PC != cacheDataPC[tid])
1212 if (blkOffset >= numInsts) {
1213 // We need to process more memory, but we've run out of the
1218 if (ISA_HAS_DELAY_SLOT && pcOffset == 0) {
1219 // Walk past any annulled delay slot instructions.
1220 Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask;
1221 while (fetchAddr != pcAddr && blkOffset < numInsts) {
1223 fetchAddr += instSize;
1225 if (blkOffset >= numInsts)
1228 MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
1230 decoder[tid]->setTC(cpu->thread[tid]->getTC());
1231 decoder[tid]->moreBytes(thisPC, fetchAddr, inst);
1233 if (decoder[tid]->needMoreBytes()) {
1235 fetchAddr += instSize;
1236 pcOffset += instSize;
1240 // Extract as many instructions and/or microops as we can from
1241 // the memory we've processed so far.
1243 if (!(curMacroop || inRom)) {
1244 if (decoder[tid]->instReady()) {
1245 staticInst = decoder[tid]->decode(thisPC);
1247 // Increment stat of fetched instructions.
1250 if (staticInst->isMacroop()) {
1251 curMacroop = staticInst;
1256 // We need more bytes for this instruction so blkOffset and
1257 // pcOffset will be updated
1261 // Whether we're moving to a new macroop because we're at the
1262 // end of the current one, or the branch predictor incorrectly
1264 bool newMacro = false;
1265 if (curMacroop || inRom) {
1267 staticInst = cpu->microcodeRom.fetchMicroop(
1268 thisPC.microPC(), curMacroop);
1270 staticInst = curMacroop->fetchMicroop(thisPC.microPC());
1272 newMacro |= staticInst->isLastMicroop();
1275 DynInstPtr instruction =
1276 buildInst(tid, staticInst, curMacroop,
1277 thisPC, nextPC, true);
1282 instruction->fetchTick = curTick();
1287 // If we're branching after this instruction, quite fetching
1288 // from the same block then.
1289 predictedBranch |= thisPC.branching();
1291 lookupAndUpdateNextPC(instruction, nextPC);
1292 if (predictedBranch) {
1293 DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC);
1296 newMacro |= thisPC.instAddr() != nextPC.instAddr();
1298 // Move to the next instruction, unless we have a branch.
1300 inRom = isRomMicroPC(thisPC.microPC());
1303 fetchAddr = thisPC.instAddr() & BaseCPU::PCMask;
1304 blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
1309 if (instruction->isQuiesce()) {
1311 "Quiesce instruction encountered, halting fetch!");
1312 fetchStatus[tid] = QuiescePending;
1313 status_change = true;
1316 } while ((curMacroop || decoder[tid]->instReady()) &&
1317 numInst < fetchWidth);
1320 if (predictedBranch) {
1321 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1322 "instruction encountered.\n", tid);
1323 } else if (numInst >= fetchWidth) {
1324 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1325 "for this cycle.\n", tid);
1326 } else if (blkOffset >= cacheBlkSize) {
1327 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1331 macroop[tid] = curMacroop;
1332 fetchOffset[tid] = pcOffset;
1335 wroteToTimeBuffer = true;
1340 // pipeline a fetch if we're crossing a cache boundary and not in
1341 // a state that would preclude fetching
1342 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1343 Addr block_PC = icacheBlockAlignPC(fetchAddr);
1344 issuePipelinedIfetch[tid] = block_PC != cacheDataPC[tid] &&
1345 fetchStatus[tid] != IcacheWaitResponse &&
1346 fetchStatus[tid] != ItlbWait &&
1347 fetchStatus[tid] != IcacheWaitRetry &&
1348 fetchStatus[tid] != QuiescePending &&
1352 template<class Impl>
1354 DefaultFetch<Impl>::recvRetry()
1356 if (retryPkt != NULL) {
1357 assert(cacheBlocked);
1358 assert(retryTid != InvalidThreadID);
1359 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1361 if (cpu->getInstPort().sendTimingReq(retryPkt)) {
1362 fetchStatus[retryTid] = IcacheWaitResponse;
1364 retryTid = InvalidThreadID;
1365 cacheBlocked = false;
1368 assert(retryTid == InvalidThreadID);
1369 // Access has been squashed since it was sent out. Just clear
1370 // the cache being blocked.
1371 cacheBlocked = false;
1375 ///////////////////////////////////////
1377 // SMT FETCH POLICY MAINTAINED HERE //
1379 ///////////////////////////////////////
1380 template<class Impl>
1382 DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1384 if (numThreads > 1) {
1385 switch (fetch_priority) {
1391 return roundRobin();
1400 return branchCount();
1403 return InvalidThreadID;
1406 list<ThreadID>::iterator thread = activeThreads->begin();
1407 if (thread == activeThreads->end()) {
1408 return InvalidThreadID;
1411 ThreadID tid = *thread;
1413 if (fetchStatus[tid] == Running ||
1414 fetchStatus[tid] == IcacheAccessComplete ||
1415 fetchStatus[tid] == Idle) {
1418 return InvalidThreadID;
1424 template<class Impl>
1426 DefaultFetch<Impl>::roundRobin()
1428 list<ThreadID>::iterator pri_iter = priorityList.begin();
1429 list<ThreadID>::iterator end = priorityList.end();
1433 while (pri_iter != end) {
1434 high_pri = *pri_iter;
1436 assert(high_pri <= numThreads);
1438 if (fetchStatus[high_pri] == Running ||
1439 fetchStatus[high_pri] == IcacheAccessComplete ||
1440 fetchStatus[high_pri] == Idle) {
1442 priorityList.erase(pri_iter);
1443 priorityList.push_back(high_pri);
1451 return InvalidThreadID;
1454 template<class Impl>
1456 DefaultFetch<Impl>::iqCount()
1458 std::priority_queue<unsigned> PQ;
1459 std::map<unsigned, ThreadID> threadMap;
1461 list<ThreadID>::iterator threads = activeThreads->begin();
1462 list<ThreadID>::iterator end = activeThreads->end();
1464 while (threads != end) {
1465 ThreadID tid = *threads++;
1466 unsigned iqCount = fromIEW->iewInfo[tid].iqCount;
1469 threadMap[iqCount] = tid;
1472 while (!PQ.empty()) {
1473 ThreadID high_pri = threadMap[PQ.top()];
1475 if (fetchStatus[high_pri] == Running ||
1476 fetchStatus[high_pri] == IcacheAccessComplete ||
1477 fetchStatus[high_pri] == Idle)
1484 return InvalidThreadID;
1487 template<class Impl>
1489 DefaultFetch<Impl>::lsqCount()
1491 std::priority_queue<unsigned> PQ;
1492 std::map<unsigned, ThreadID> threadMap;
1494 list<ThreadID>::iterator threads = activeThreads->begin();
1495 list<ThreadID>::iterator end = activeThreads->end();
1497 while (threads != end) {
1498 ThreadID tid = *threads++;
1499 unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount;
1501 PQ.push(ldstqCount);
1502 threadMap[ldstqCount] = tid;
1505 while (!PQ.empty()) {
1506 ThreadID high_pri = threadMap[PQ.top()];
1508 if (fetchStatus[high_pri] == Running ||
1509 fetchStatus[high_pri] == IcacheAccessComplete ||
1510 fetchStatus[high_pri] == Idle)
1516 return InvalidThreadID;
1519 template<class Impl>
1521 DefaultFetch<Impl>::branchCount()
1524 list<ThreadID>::iterator thread = activeThreads->begin();
1525 assert(thread != activeThreads->end());
1526 ThreadID tid = *thread;
1529 panic("Branch Count Fetch policy unimplemented\n");
1530 return InvalidThreadID;
1533 template<class Impl>
1535 DefaultFetch<Impl>::pipelineIcacheAccesses(ThreadID tid)
1537 if (!issuePipelinedIfetch[tid]) {
1541 // The next PC to access.
1542 TheISA::PCState thisPC = pc[tid];
1544 if (isRomMicroPC(thisPC.microPC())) {
1548 Addr pcOffset = fetchOffset[tid];
1549 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1551 // Align the fetch PC so its at the start of a cache block.
1552 Addr block_PC = icacheBlockAlignPC(fetchAddr);
1554 // Unless buffer already got the block, fetch it from icache.
1555 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid])) {
1556 DPRINTF(Fetch, "[tid:%i]: Issuing a pipelined I-cache access, "
1557 "starting at PC %s.\n", tid, thisPC);
1559 fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1563 template<class Impl>
1565 DefaultFetch<Impl>::profileStall(ThreadID tid) {
1566 DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1568 // @todo Per-thread stats
1571 ++fetchPendingDrainCycles;
1572 DPRINTF(Fetch, "Fetch is waiting for a drain!\n");
1573 } else if (activeThreads->empty()) {
1574 ++fetchNoActiveThreadStallCycles;
1575 DPRINTF(Fetch, "Fetch has no active thread!\n");
1576 } else if (fetchStatus[tid] == Blocked) {
1577 ++fetchBlockedCycles;
1578 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1579 } else if (fetchStatus[tid] == Squashing) {
1580 ++fetchSquashCycles;
1581 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1582 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1583 ++icacheStallCycles;
1584 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n",
1586 } else if (fetchStatus[tid] == ItlbWait) {
1588 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to "
1590 } else if (fetchStatus[tid] == TrapPending) {
1591 ++fetchPendingTrapStallCycles;
1592 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap!\n",
1594 } else if (fetchStatus[tid] == QuiescePending) {
1595 ++fetchPendingQuiesceStallCycles;
1596 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending quiesce "
1597 "instruction!\n", tid);
1598 } else if (fetchStatus[tid] == IcacheWaitRetry) {
1599 ++fetchIcacheWaitRetryStallCycles;
1600 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for an I-cache retry!\n",
1602 } else if (fetchStatus[tid] == NoGoodAddr) {
1603 DPRINTF(Fetch, "[tid:%i]: Fetch predicted non-executable address\n",
1606 DPRINTF(Fetch, "[tid:%i]: Unexpected fetch stall reason (Status: %i).\n",
1607 tid, fetchStatus[tid]);