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32 #include "config/use_checker.hh"
34 #include "arch/isa_traits.hh"
35 #include "arch/utility.hh"
36 #include "cpu/checker/cpu.hh"
37 #include "cpu/exetrace.hh"
38 #include "cpu/o3/fetch.hh"
39 #include "mem/packet.hh"
40 #include "mem/request.hh"
41 #include "sim/byteswap.hh"
42 #include "sim/host.hh"
43 #include "sim/root.hh"
46 #include "arch/tlb.hh"
47 #include "arch/vtophys.hh"
48 #include "sim/system.hh"
55 DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
57 panic("DefaultFetch doesn't expect recvAtomic callback!");
63 DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
65 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
71 DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
73 if (status == RangeChange) {
74 if (!snoopRangeSent) {
75 snoopRangeSent = true;
76 sendStatusChange(Port::RangeChange);
81 panic("DefaultFetch doesn't expect recvStatusChange callback!");
86 DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
88 DPRINTF(Fetch, "Received timing\n");
89 if (pkt->isResponse()) {
90 fetch->processCacheCompletion(pkt);
92 //else Snooped a coherence request, just return
98 DefaultFetch<Impl>::IcachePort::recvRetry()
104 DefaultFetch<Impl>::DefaultFetch(Params *params)
105 : branchPred(params),
106 decodeToFetchDelay(params->decodeToFetchDelay),
107 renameToFetchDelay(params->renameToFetchDelay),
108 iewToFetchDelay(params->iewToFetchDelay),
109 commitToFetchDelay(params->commitToFetchDelay),
110 fetchWidth(params->fetchWidth),
114 numThreads(params->numberOfThreads),
115 numFetchingThreads(params->smtNumFetchingThreads),
116 interruptPending(false),
120 if (numThreads > Impl::MaxThreads)
121 fatal("numThreads is not a valid value\n");
123 // Set fetch stage's status to inactive.
126 std::string policy = params->smtFetchPolicy;
128 // Convert string to lowercase
129 std::transform(policy.begin(), policy.end(), policy.begin(),
130 (int(*)(int)) tolower);
132 // Figure out fetch policy
133 if (policy == "singlethread") {
134 fetchPolicy = SingleThread;
136 panic("Invalid Fetch Policy for a SMT workload.");
137 } else if (policy == "roundrobin") {
138 fetchPolicy = RoundRobin;
139 DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
140 } else if (policy == "branch") {
141 fetchPolicy = Branch;
142 DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
143 } else if (policy == "iqcount") {
145 DPRINTF(Fetch, "Fetch policy set to IQ count\n");
146 } else if (policy == "lsqcount") {
148 DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
150 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
151 " RoundRobin,LSQcount,IQcount}\n");
154 // Size of cache block.
157 // Create mask to get rid of offset bits.
158 cacheBlkMask = (cacheBlkSize - 1);
160 for (int tid=0; tid < numThreads; tid++) {
162 fetchStatus[tid] = Running;
164 priorityList.push_back(tid);
168 // Create space to store a cache line.
169 cacheData[tid] = new uint8_t[cacheBlkSize];
170 cacheDataPC[tid] = 0;
171 cacheDataValid[tid] = false;
173 delaySlotInfo[tid].branchSeqNum = -1;
174 delaySlotInfo[tid].numInsts = 0;
175 delaySlotInfo[tid].targetAddr = 0;
176 delaySlotInfo[tid].targetReady = false;
178 stalls[tid].decode = false;
179 stalls[tid].rename = false;
180 stalls[tid].iew = false;
181 stalls[tid].commit = false;
184 // Get the size of an instruction.
185 instSize = sizeof(TheISA::MachInst);
188 template <class Impl>
190 DefaultFetch<Impl>::name() const
192 return cpu->name() + ".fetch";
195 template <class Impl>
197 DefaultFetch<Impl>::regStats()
200 .name(name() + ".icacheStallCycles")
201 .desc("Number of cycles fetch is stalled on an Icache miss")
202 .prereq(icacheStallCycles);
205 .name(name() + ".Insts")
206 .desc("Number of instructions fetch has processed")
207 .prereq(fetchedInsts);
210 .name(name() + ".Branches")
211 .desc("Number of branches that fetch encountered")
212 .prereq(fetchedBranches);
215 .name(name() + ".predictedBranches")
216 .desc("Number of branches that fetch has predicted taken")
217 .prereq(predictedBranches);
220 .name(name() + ".Cycles")
221 .desc("Number of cycles fetch has run and was not squashing or"
223 .prereq(fetchCycles);
226 .name(name() + ".SquashCycles")
227 .desc("Number of cycles fetch has spent squashing")
228 .prereq(fetchSquashCycles);
231 .name(name() + ".IdleCycles")
232 .desc("Number of cycles fetch was idle")
233 .prereq(fetchIdleCycles);
236 .name(name() + ".BlockedCycles")
237 .desc("Number of cycles fetch has spent blocked")
238 .prereq(fetchBlockedCycles);
241 .name(name() + ".CacheLines")
242 .desc("Number of cache lines fetched")
243 .prereq(fetchedCacheLines);
246 .name(name() + ".MiscStallCycles")
247 .desc("Number of cycles fetch has spent waiting on interrupts, or "
248 "bad addresses, or out of MSHRs")
249 .prereq(fetchMiscStallCycles);
252 .name(name() + ".IcacheSquashes")
253 .desc("Number of outstanding Icache misses that were squashed")
254 .prereq(fetchIcacheSquashes);
257 .init(/* base value */ 0,
258 /* last value */ fetchWidth,
260 .name(name() + ".rateDist")
261 .desc("Number of instructions fetched each cycle (Total)")
265 .name(name() + ".idleRate")
266 .desc("Percent of cycles fetch was idle")
268 idleRate = fetchIdleCycles * 100 / cpu->numCycles;
271 .name(name() + ".branchRate")
272 .desc("Number of branch fetches per cycle")
273 .flags(Stats::total);
274 branchRate = fetchedBranches / cpu->numCycles;
277 .name(name() + ".rate")
278 .desc("Number of inst fetches per cycle")
279 .flags(Stats::total);
280 fetchRate = fetchedInsts / cpu->numCycles;
282 branchPred.regStats();
287 DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
289 DPRINTF(Fetch, "Setting the CPU pointer.\n");
292 // Name is finally available, so create the port.
293 icachePort = new IcachePort(this);
295 icachePort->snoopRangeSent = false;
299 cpu->checker->setIcachePort(icachePort);
303 // Schedule fetch to get the correct PC from the CPU
304 // scheduleFetchStartupEvent(1);
306 // Fetch needs to start fetching instructions at the very beginning,
307 // so it must start up in active state.
313 DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
315 DPRINTF(Fetch, "Setting the time buffer pointer.\n");
316 timeBuffer = time_buffer;
318 // Create wires to get information from proper places in time buffer.
319 fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
320 fromRename = timeBuffer->getWire(-renameToFetchDelay);
321 fromIEW = timeBuffer->getWire(-iewToFetchDelay);
322 fromCommit = timeBuffer->getWire(-commitToFetchDelay);
327 DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
329 DPRINTF(Fetch, "Setting active threads list pointer.\n");
330 activeThreads = at_ptr;
335 DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
337 DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
340 // Create wire to write information to proper place in fetch queue.
341 toDecode = fetchQueue->getWire(0);
346 DefaultFetch<Impl>::initStage()
348 // Setup PC and nextPC with initial state.
349 for (int tid = 0; tid < numThreads; tid++) {
350 PC[tid] = cpu->readPC(tid);
351 nextPC[tid] = cpu->readNextPC(tid);
352 #if ISA_HAS_DELAY_SLOT
353 nextNPC[tid] = cpu->readNextNPC(tid);
360 DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
362 unsigned tid = pkt->req->getThreadNum();
364 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
366 // Only change the status if it's still waiting on the icache access
368 if (fetchStatus[tid] != IcacheWaitResponse ||
369 pkt->req != memReq[tid] ||
371 ++fetchIcacheSquashes;
377 memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
378 cacheDataValid[tid] = true;
381 // Wake up the CPU (if it went to sleep and was waiting on
382 // this completion event).
385 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
391 // Only switch to IcacheAccessComplete if we're not stalled as well.
392 if (checkStall(tid)) {
393 fetchStatus[tid] = Blocked;
395 fetchStatus[tid] = IcacheAccessComplete;
398 // Reset the mem req to NULL.
404 template <class Impl>
406 DefaultFetch<Impl>::drain()
408 // Fetch is ready to drain at any time.
409 cpu->signalDrained();
414 template <class Impl>
416 DefaultFetch<Impl>::resume()
418 drainPending = false;
421 template <class Impl>
423 DefaultFetch<Impl>::switchOut()
426 // Branch predictor needs to have its state cleared.
427 branchPred.switchOut();
430 template <class Impl>
432 DefaultFetch<Impl>::takeOverFrom()
435 for (int i = 0; i < Impl::MaxThreads; ++i) {
436 stalls[i].decode = 0;
437 stalls[i].rename = 0;
439 stalls[i].commit = 0;
440 PC[i] = cpu->readPC(i);
441 nextPC[i] = cpu->readNextPC(i);
442 #if ISA_HAS_DELAY_SLOT
443 nextNPC[i] = cpu->readNextNPC(i);
444 delaySlotInfo[i].branchSeqNum = -1;
445 delaySlotInfo[i].numInsts = 0;
446 delaySlotInfo[i].targetAddr = 0;
447 delaySlotInfo[i].targetReady = false;
449 fetchStatus[i] = Running;
452 wroteToTimeBuffer = false;
455 interruptPending = false;
456 branchPred.takeOverFrom();
459 template <class Impl>
461 DefaultFetch<Impl>::wakeFromQuiesce()
463 DPRINTF(Fetch, "Waking up from quiesce\n");
464 // Hopefully this is safe
465 // @todo: Allow other threads to wake from quiesce.
466 fetchStatus[0] = Running;
469 template <class Impl>
471 DefaultFetch<Impl>::switchToActive()
473 if (_status == Inactive) {
474 DPRINTF(Activity, "Activating stage.\n");
476 cpu->activateStage(O3CPU::FetchIdx);
482 template <class Impl>
484 DefaultFetch<Impl>::switchToInactive()
486 if (_status == Active) {
487 DPRINTF(Activity, "Deactivating stage.\n");
489 cpu->deactivateStage(O3CPU::FetchIdx);
495 template <class Impl>
497 DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
500 // Do branch prediction check here.
501 // A bit of a misnomer...next_PC is actually the current PC until
502 // this function updates it.
505 if (!inst->isControl()) {
506 #if ISA_HAS_DELAY_SLOT
507 Addr cur_PC = next_PC;
508 next_PC = cur_PC + instSize; //next_NPC;
509 next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
510 inst->setPredTarg(next_NPC);
512 next_PC = next_PC + instSize;
513 inst->setPredTarg(next_PC);
518 int tid = inst->threadNumber;
519 #if ISA_HAS_DELAY_SLOT
520 Addr pred_PC = next_PC;
521 predict_taken = branchPred.predict(inst, pred_PC, tid);
524 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be true.\n", tid);
526 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be false.\n", tid);
533 // Update delay slot info
534 ++delaySlotInfo[tid].numInsts;
535 delaySlotInfo[tid].targetAddr = pred_PC;
536 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid,
537 delaySlotInfo[tid].numInsts);
538 } else { // !predict_taken
539 if (inst->isCondDelaySlot()) {
541 // The delay slot is skipped here if there is on
545 // No need to declare a delay slot here since
546 // there is no for the pred. target to jump
549 next_NPC = next_NPC + instSize;
552 predict_taken = branchPred.predict(inst, next_PC, tid);
561 return predict_taken;
564 template <class Impl>
566 DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
568 Fault fault = NoFault;
572 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
575 } else if (isSwitchedOut()) {
576 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
579 } else if (interruptPending && !(fetch_PC & 0x3)) {
580 // Hold off fetch from getting new instructions when:
581 // Cache is blocked, or
582 // while an interrupt is pending and we're not in PAL mode, or
583 // fetch is switched out.
584 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
589 // Align the fetch PC so it's at the start of a cache block.
590 Addr block_PC = icacheBlockAlignPC(fetch_PC);
592 // If we've already got the block, no need to try to fetch it again.
593 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
597 // Setup the memReq to do a read of the first instruction's address.
598 // Set the appropriate read size and flags as well.
599 // Build request here.
600 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
601 fetch_PC, cpu->readCpuId(), tid);
603 memReq[tid] = mem_req;
605 // Translate the instruction request.
606 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
608 // In the case of faults, the fetch stage may need to stall and wait
609 // for the ITB miss to be handled.
611 // If translation was successful, attempt to read the first
613 if (fault == NoFault) {
615 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
616 memReq[tid]->isUncacheable()) {
617 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
618 "misspeculating path)!",
620 ret_fault = TheISA::genMachineCheckFault();
625 // Build packet here.
626 PacketPtr data_pkt = new Packet(mem_req,
627 Packet::ReadReq, Packet::Broadcast);
628 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
630 cacheDataPC[tid] = block_PC;
631 cacheDataValid[tid] = false;
633 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
637 // Now do the timing access to see whether or not the instruction
638 // exists within the cache.
639 if (!icachePort->sendTiming(data_pkt)) {
640 if (data_pkt->result == Packet::BadAddress) {
641 fault = TheISA::genMachineCheckFault();
645 assert(retryPkt == NULL);
646 assert(retryTid == -1);
647 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
648 fetchStatus[tid] = IcacheWaitRetry;
655 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
657 lastIcacheStall[tid] = curTick;
659 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
662 fetchStatus[tid] = IcacheWaitResponse;
672 template <class Impl>
674 DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
676 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
680 nextPC[tid] = new_PC + instSize;
681 nextNPC[tid] = new_PC + (2 * instSize);
683 // Clear the icache miss if it's outstanding.
684 if (fetchStatus[tid] == IcacheWaitResponse) {
685 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
690 // Get rid of the retrying packet if it was from this thread.
691 if (retryTid == tid) {
692 assert(cacheBlocked);
693 cacheBlocked = false;
695 delete retryPkt->req;
700 fetchStatus[tid] = Squashing;
707 DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
708 const InstSeqNum &seq_num,
711 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
713 doSquash(new_PC, tid);
715 #if ISA_HAS_DELAY_SLOT
716 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
717 delaySlotInfo[tid].numInsts = 0;
718 delaySlotInfo[tid].targetAddr = 0;
719 delaySlotInfo[tid].targetReady = false;
723 // Tell the CPU to remove any instructions that are in flight between
725 cpu->removeInstsUntil(seq_num, tid);
730 DefaultFetch<Impl>::checkStall(unsigned tid) const
732 bool ret_val = false;
734 if (cpu->contextSwitch) {
735 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
737 } else if (stalls[tid].decode) {
738 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
740 } else if (stalls[tid].rename) {
741 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
743 } else if (stalls[tid].iew) {
744 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
746 } else if (stalls[tid].commit) {
747 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
755 typename DefaultFetch<Impl>::FetchStatus
756 DefaultFetch<Impl>::updateFetchStatus()
759 std::list<unsigned>::iterator threads = (*activeThreads).begin();
761 while (threads != (*activeThreads).end()) {
763 unsigned tid = *threads++;
765 if (fetchStatus[tid] == Running ||
766 fetchStatus[tid] == Squashing ||
767 fetchStatus[tid] == IcacheAccessComplete) {
769 if (_status == Inactive) {
770 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
772 if (fetchStatus[tid] == IcacheAccessComplete) {
773 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
777 cpu->activateStage(O3CPU::FetchIdx);
784 // Stage is switching from active to inactive, notify CPU of it.
785 if (_status == Active) {
786 DPRINTF(Activity, "Deactivating stage.\n");
788 cpu->deactivateStage(O3CPU::FetchIdx);
794 template <class Impl>
796 DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
797 bool squash_delay_slot, unsigned tid)
799 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
801 doSquash(new_PC, tid);
803 #if ISA_HAS_DELAY_SLOT
804 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
805 delaySlotInfo[tid].numInsts = 0;
806 delaySlotInfo[tid].targetAddr = 0;
807 delaySlotInfo[tid].targetReady = false;
810 // Tell the CPU to remove any instructions that are not in the ROB.
811 cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
813 // Tell the CPU to remove any instructions that are not in the ROB.
814 cpu->removeInstsNotInROB(tid, true, 0);
818 template <class Impl>
820 DefaultFetch<Impl>::tick()
822 std::list<unsigned>::iterator threads = (*activeThreads).begin();
823 bool status_change = false;
825 wroteToTimeBuffer = false;
827 while (threads != (*activeThreads).end()) {
828 unsigned tid = *threads++;
830 // Check the signals for each thread to determine the proper status
832 bool updated_status = checkSignalsAndUpdate(tid);
833 status_change = status_change || updated_status;
836 DPRINTF(Fetch, "Running stage.\n");
838 // Reset the number of the instruction we're fetching.
842 if (fromCommit->commitInfo[0].interruptPending) {
843 interruptPending = true;
846 if (fromCommit->commitInfo[0].clearInterrupt) {
847 interruptPending = false;
851 for (threadFetched = 0; threadFetched < numFetchingThreads;
853 // Fetch each of the actively fetching threads.
854 fetch(status_change);
857 // Record number of instructions fetched this cycle for distribution.
858 fetchNisnDist.sample(numInst);
861 // Change the fetch stage status if there was a status change.
862 _status = updateFetchStatus();
865 // If there was activity this cycle, inform the CPU of it.
866 if (wroteToTimeBuffer || cpu->contextSwitch) {
867 DPRINTF(Activity, "Activity this cycle.\n");
869 cpu->activityThisCycle();
873 template <class Impl>
875 DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
877 // Update the per thread stall statuses.
878 if (fromDecode->decodeBlock[tid]) {
879 stalls[tid].decode = true;
882 if (fromDecode->decodeUnblock[tid]) {
883 assert(stalls[tid].decode);
884 assert(!fromDecode->decodeBlock[tid]);
885 stalls[tid].decode = false;
888 if (fromRename->renameBlock[tid]) {
889 stalls[tid].rename = true;
892 if (fromRename->renameUnblock[tid]) {
893 assert(stalls[tid].rename);
894 assert(!fromRename->renameBlock[tid]);
895 stalls[tid].rename = false;
898 if (fromIEW->iewBlock[tid]) {
899 stalls[tid].iew = true;
902 if (fromIEW->iewUnblock[tid]) {
903 assert(stalls[tid].iew);
904 assert(!fromIEW->iewBlock[tid]);
905 stalls[tid].iew = false;
908 if (fromCommit->commitBlock[tid]) {
909 stalls[tid].commit = true;
912 if (fromCommit->commitUnblock[tid]) {
913 assert(stalls[tid].commit);
914 assert(!fromCommit->commitBlock[tid]);
915 stalls[tid].commit = false;
918 // Check squash signals from commit.
919 if (fromCommit->commitInfo[tid].squash) {
921 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
922 "from commit.\n",tid);
924 #if ISA_HAS_DELAY_SLOT
925 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
927 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
929 // In any case, squash.
930 squash(fromCommit->commitInfo[tid].nextPC,
932 fromCommit->commitInfo[tid].squashDelaySlot,
935 // Also check if there's a mispredict that happened.
936 if (fromCommit->commitInfo[tid].branchMispredict) {
937 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
938 fromCommit->commitInfo[tid].nextPC,
939 fromCommit->commitInfo[tid].branchTaken,
942 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
947 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
948 // Update the branch predictor if it wasn't a squashed instruction
949 // that was broadcasted.
950 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
953 // Check ROB squash signals from commit.
954 if (fromCommit->commitInfo[tid].robSquashing) {
955 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
957 // Continue to squash.
958 fetchStatus[tid] = Squashing;
963 // Check squash signals from decode.
964 if (fromDecode->decodeInfo[tid].squash) {
965 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
966 "from decode.\n",tid);
968 // Update the branch predictor.
969 if (fromDecode->decodeInfo[tid].branchMispredict) {
970 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
971 fromDecode->decodeInfo[tid].nextPC,
972 fromDecode->decodeInfo[tid].branchTaken,
975 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
979 if (fetchStatus[tid] != Squashing) {
981 #if ISA_HAS_DELAY_SLOT
982 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
984 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
986 // Squash unless we're already squashing
987 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
995 if (checkStall(tid) &&
996 fetchStatus[tid] != IcacheWaitResponse &&
997 fetchStatus[tid] != IcacheWaitRetry) {
998 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
1000 fetchStatus[tid] = Blocked;
1005 if (fetchStatus[tid] == Blocked ||
1006 fetchStatus[tid] == Squashing) {
1007 // Switch status to running if fetch isn't being told to block or
1008 // squash this cycle.
1009 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
1012 fetchStatus[tid] = Running;
1017 // If we've reached this point, we have not gotten any signals that
1018 // cause fetch to change its status. Fetch remains the same as before.
1022 template<class Impl>
1024 DefaultFetch<Impl>::fetch(bool &status_change)
1026 //////////////////////////////////////////
1027 // Start actual fetch
1028 //////////////////////////////////////////
1029 int tid = getFetchingThread(fetchPolicy);
1031 if (tid == -1 || drainPending) {
1032 DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1034 // Breaks looping condition in tick()
1035 threadFetched = numFetchingThreads;
1039 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1042 Addr &fetch_PC = PC[tid];
1044 // Fault code for memory access.
1045 Fault fault = NoFault;
1047 // If returning from the delay of a cache miss, then update the status
1048 // to running, otherwise do the cache access. Possibly move this up
1049 // to tick() function.
1050 if (fetchStatus[tid] == IcacheAccessComplete) {
1051 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1054 fetchStatus[tid] = Running;
1055 status_change = true;
1056 } else if (fetchStatus[tid] == Running) {
1057 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1058 "instruction, starting at PC %08p.\n",
1061 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1062 if (!fetch_success) {
1064 ++icacheStallCycles;
1066 ++fetchMiscStallCycles;
1071 if (fetchStatus[tid] == Idle) {
1073 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1074 } else if (fetchStatus[tid] == Blocked) {
1075 ++fetchBlockedCycles;
1076 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1077 } else if (fetchStatus[tid] == Squashing) {
1078 ++fetchSquashCycles;
1079 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1080 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1081 ++icacheStallCycles;
1082 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid);
1085 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1086 // fetch should do nothing.
1092 // If we had a stall due to an icache miss, then return.
1093 if (fetchStatus[tid] == IcacheWaitResponse) {
1094 ++icacheStallCycles;
1095 status_change = true;
1099 Addr next_PC = fetch_PC;
1100 Addr next_NPC = next_PC + instSize;
1101 InstSeqNum inst_seq;
1103 ExtMachInst ext_inst;
1104 // @todo: Fix this hack.
1105 unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1107 if (fault == NoFault) {
1108 // If the read of the first instruction was successful, then grab the
1109 // instructions from the rest of the cache line and put them into the
1110 // queue heading to decode.
1112 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1115 // Need to keep track of whether or not a predicted branch
1116 // ended this fetch block.
1117 bool predicted_branch = false;
1119 // Need to keep track of whether or not a delay slot
1120 // instruction has been fetched
1123 offset < cacheBlkSize &&
1124 numInst < fetchWidth &&
1125 (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
1128 // Get a sequence number.
1129 inst_seq = cpu->getAndIncrementInstSeq();
1131 // Make sure this is a valid index.
1132 assert(offset <= cacheBlkSize - instSize);
1134 // Get the instruction from the array of the cache line.
1135 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1136 (&cacheData[tid][offset]));
1138 #if THE_ISA == ALPHA_ISA
1139 ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1140 #elif THE_ISA == SPARC_ISA
1141 ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
1142 #elif THE_ISA == MIPS_ISA
1143 ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
1146 // Create a new DynInst from the instruction fetched.
1147 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1150 instruction->setTid(tid);
1152 instruction->setASID(tid);
1154 instruction->setThreadState(cpu->thread[tid]);
1156 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1158 tid, instruction->readPC(), inst_seq);
1160 DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
1162 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1163 tid, instruction->staticInst->disassemble(fetch_PC));
1165 instruction->traceData =
1166 Trace::getInstRecord(curTick, cpu->tcBase(tid),
1167 instruction->staticInst,
1168 instruction->readPC());
1170 predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
1173 // Add instruction to the CPU's list of instructions.
1174 instruction->setInstListIt(cpu->addInst(instruction));
1176 // Write the instruction to the first slot in the queue
1177 // that heads to decode.
1178 toDecode->insts[numInst] = instruction;
1182 // Increment stat of fetched instructions.
1185 // Move to the next instruction, unless we have a branch.
1188 if (instruction->isQuiesce()) {
1189 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1191 fetchStatus[tid] = QuiescePending;
1193 status_change = true;
1199 #if ISA_HAS_DELAY_SLOT
1200 if (predicted_branch) {
1201 delaySlotInfo[tid].branchSeqNum = inst_seq;
1203 DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
1206 } else if (delaySlotInfo[tid].numInsts > 0) {
1207 --delaySlotInfo[tid].numInsts;
1209 // It's OK to set PC to target of branch
1210 if (delaySlotInfo[tid].numInsts == 0) {
1211 delaySlotInfo[tid].targetReady = true;
1213 // Break the looping condition
1214 predicted_branch = true;
1217 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
1218 " process.\n", tid, delaySlotInfo[tid].numInsts);
1223 if (offset >= cacheBlkSize) {
1224 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1226 } else if (numInst >= fetchWidth) {
1227 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1228 "for this cycle.\n", tid);
1229 } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
1230 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1231 "instruction encountered.\n", tid);
1236 wroteToTimeBuffer = true;
1239 // Now that fetching is completed, update the PC to signify what the next
1241 if (fault == NoFault) {
1242 #if ISA_HAS_DELAY_SLOT
1243 if (delaySlotInfo[tid].targetReady &&
1244 delaySlotInfo[tid].numInsts == 0) {
1246 PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
1247 nextPC[tid] = next_PC + instSize; //next_NPC
1248 nextNPC[tid] = next_PC + (2 * instSize);
1250 delaySlotInfo[tid].targetReady = false;
1253 nextPC[tid] = next_NPC;
1254 nextNPC[tid] = next_NPC + instSize;
1257 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
1259 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1261 nextPC[tid] = next_PC + instSize;
1264 // We shouldn't be in an icache miss and also have a fault (an ITB
1266 if (fetchStatus[tid] == IcacheWaitResponse) {
1267 panic("Fetch should have exited prior to this!");
1270 // Send the fault to commit. This thread will not do anything
1271 // until commit handles the fault. The only other way it can
1272 // wake up is if a squash comes along and changes the PC.
1274 assert(numInst != fetchWidth);
1275 // Get a sequence number.
1276 inst_seq = cpu->getAndIncrementInstSeq();
1277 // We will use a nop in order to carry the fault.
1278 ext_inst = TheISA::NoopMachInst;
1280 // Create a new DynInst from the dummy nop.
1281 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1284 instruction->setPredTarg(next_PC + instSize);
1285 instruction->setTid(tid);
1287 instruction->setASID(tid);
1289 instruction->setThreadState(cpu->thread[tid]);
1291 instruction->traceData = NULL;
1293 instruction->setInstListIt(cpu->addInst(instruction));
1295 instruction->fault = fault;
1297 toDecode->insts[numInst] = instruction;
1300 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1302 fetchStatus[tid] = TrapPending;
1303 status_change = true;
1304 #else // !FULL_SYSTEM
1305 fetchStatus[tid] = TrapPending;
1306 status_change = true;
1308 #endif // FULL_SYSTEM
1309 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
1310 tid, fault->name(), PC[tid]);
1314 template<class Impl>
1316 DefaultFetch<Impl>::recvRetry()
1318 if (retryPkt != NULL) {
1319 assert(cacheBlocked);
1320 assert(retryTid != -1);
1321 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1323 if (icachePort->sendTiming(retryPkt)) {
1324 fetchStatus[retryTid] = IcacheWaitResponse;
1327 cacheBlocked = false;
1330 assert(retryTid == -1);
1331 // Access has been squashed since it was sent out. Just clear
1332 // the cache being blocked.
1333 cacheBlocked = false;
1337 ///////////////////////////////////////
1339 // SMT FETCH POLICY MAINTAINED HERE //
1341 ///////////////////////////////////////
1342 template<class Impl>
1344 DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1346 if (numThreads > 1) {
1347 switch (fetch_priority) {
1353 return roundRobin();
1362 return branchCount();
1368 int tid = *((*activeThreads).begin());
1370 if (fetchStatus[tid] == Running ||
1371 fetchStatus[tid] == IcacheAccessComplete ||
1372 fetchStatus[tid] == Idle) {
1382 template<class Impl>
1384 DefaultFetch<Impl>::roundRobin()
1386 std::list<unsigned>::iterator pri_iter = priorityList.begin();
1387 std::list<unsigned>::iterator end = priorityList.end();
1391 while (pri_iter != end) {
1392 high_pri = *pri_iter;
1394 assert(high_pri <= numThreads);
1396 if (fetchStatus[high_pri] == Running ||
1397 fetchStatus[high_pri] == IcacheAccessComplete ||
1398 fetchStatus[high_pri] == Idle) {
1400 priorityList.erase(pri_iter);
1401 priorityList.push_back(high_pri);
1412 template<class Impl>
1414 DefaultFetch<Impl>::iqCount()
1416 std::priority_queue<unsigned> PQ;
1418 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1420 while (threads != (*activeThreads).end()) {
1421 unsigned tid = *threads++;
1423 PQ.push(fromIEW->iewInfo[tid].iqCount);
1426 while (!PQ.empty()) {
1428 unsigned high_pri = PQ.top();
1430 if (fetchStatus[high_pri] == Running ||
1431 fetchStatus[high_pri] == IcacheAccessComplete ||
1432 fetchStatus[high_pri] == Idle)
1442 template<class Impl>
1444 DefaultFetch<Impl>::lsqCount()
1446 std::priority_queue<unsigned> PQ;
1449 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1451 while (threads != (*activeThreads).end()) {
1452 unsigned tid = *threads++;
1454 PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1457 while (!PQ.empty()) {
1459 unsigned high_pri = PQ.top();
1461 if (fetchStatus[high_pri] == Running ||
1462 fetchStatus[high_pri] == IcacheAccessComplete ||
1463 fetchStatus[high_pri] == Idle)
1473 template<class Impl>
1475 DefaultFetch<Impl>::branchCount()
1477 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1478 panic("Branch Count Fetch policy unimplemented\n");