src/cpu/o3/fetch_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Korey Sewell
  30  */
  31
  32 #include "config/use_checker.hh"
  33
  34 #include "arch/isa_traits.hh"
  35 #include "arch/utility.hh"
  36 #include "cpu/checker/cpu.hh"
  37 #include "cpu/exetrace.hh"
  38 #include "cpu/o3/fetch.hh"
  39 #include "mem/packet.hh"
  40 #include "mem/request.hh"
  41 #include "sim/byteswap.hh"
  42 #include "sim/host.hh"
  43 #include "sim/root.hh"
  44
  45 #if FULL_SYSTEM
  46 #include "arch/tlb.hh"
  47 #include "arch/vtophys.hh"
  48 #include "sim/system.hh"
  49 #endif // FULL_SYSTEM
  50
  51 #include <algorithm>
  52
  53 template<class Impl>
  54 Tick
  55 DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
  56 {
  57     panic("DefaultFetch doesn't expect recvAtomic callback!");
  58     return curTick;
  59 }
  60
  61 template<class Impl>
  62 void
  63 DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
  64 {
  65     DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
  66             "functional call.");
  67 }
  68
  69 template<class Impl>
  70 void
  71 DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
  72 {
  73     if (status == RangeChange) {
  74         if (!snoopRangeSent) {
  75             snoopRangeSent = true;
  76             sendStatusChange(Port::RangeChange);
  77         }
  78         return;
  79     }
  80
  81     panic("DefaultFetch doesn't expect recvStatusChange callback!");
  82 }
  83
  84 template<class Impl>
  85 bool
  86 DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
  87 {
  88     DPRINTF(Fetch, "Received timing\n");
  89     if (pkt->isResponse()) {
  90         fetch->processCacheCompletion(pkt);
  91     }
  92     //else Snooped a coherence request, just return
  93     return true;
  94 }
  95
  96 template<class Impl>
  97 void
  98 DefaultFetch<Impl>::IcachePort::recvRetry()
  99 {
 100     fetch->recvRetry();
 101 }
 102
 103 template<class Impl>
 104 DefaultFetch<Impl>::DefaultFetch(Params *params)
 105     : branchPred(params),
 106       decodeToFetchDelay(params->decodeToFetchDelay),
 107       renameToFetchDelay(params->renameToFetchDelay),
 108       iewToFetchDelay(params->iewToFetchDelay),
 109       commitToFetchDelay(params->commitToFetchDelay),
 110       fetchWidth(params->fetchWidth),
 111       cacheBlocked(false),
 112       retryPkt(NULL),
 113       retryTid(-1),
 114       numThreads(params->numberOfThreads),
 115       numFetchingThreads(params->smtNumFetchingThreads),
 116       interruptPending(false),
 117       drainPending(false),
 118       switchedOut(false)
 119 {
 120     if (numThreads > Impl::MaxThreads)
 121         fatal("numThreads is not a valid value\n");
 122
 123     // Set fetch stage's status to inactive.
 124     _status = Inactive;
 125
 126     std::string policy = params->smtFetchPolicy;
 127
 128     // Convert string to lowercase
 129     std::transform(policy.begin(), policy.end(), policy.begin(),
 130                    (int(*)(int)) tolower);
 131
 132     // Figure out fetch policy
 133     if (policy == "singlethread") {
 134         fetchPolicy = SingleThread;
 135         if (numThreads > 1)
 136             panic("Invalid Fetch Policy for a SMT workload.");
 137     } else if (policy == "roundrobin") {
 138         fetchPolicy = RoundRobin;
 139         DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
 140     } else if (policy == "branch") {
 141         fetchPolicy = Branch;
 142         DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
 143     } else if (policy == "iqcount") {
 144         fetchPolicy = IQ;
 145         DPRINTF(Fetch, "Fetch policy set to IQ count\n");
 146     } else if (policy == "lsqcount") {
 147         fetchPolicy = LSQ;
 148         DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
 149     } else {
 150         fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
 151               " RoundRobin,LSQcount,IQcount}\n");
 152     }
 153
 154     // Size of cache block.
 155     cacheBlkSize = 64;
 156
 157     // Create mask to get rid of offset bits.
 158     cacheBlkMask = (cacheBlkSize - 1);
 159
 160     for (int tid=0; tid < numThreads; tid++) {
 161
 162         fetchStatus[tid] = Running;
 163
 164         priorityList.push_back(tid);
 165
 166         memReq[tid] = NULL;
 167
 168         // Create space to store a cache line.
 169         cacheData[tid] = new uint8_t[cacheBlkSize];
 170         cacheDataPC[tid] = 0;
 171         cacheDataValid[tid] = false;
 172
 173         delaySlotInfo[tid].branchSeqNum = -1;
 174         delaySlotInfo[tid].numInsts = 0;
 175         delaySlotInfo[tid].targetAddr = 0;
 176         delaySlotInfo[tid].targetReady = false;
 177
 178         stalls[tid].decode = false;
 179         stalls[tid].rename = false;
 180         stalls[tid].iew = false;
 181         stalls[tid].commit = false;
 182     }
 183
 184     // Get the size of an instruction.
 185     instSize = sizeof(TheISA::MachInst);
 186 }
 187
 188 template <class Impl>
 189 std::string
 190 DefaultFetch<Impl>::name() const
 191 {
 192     return cpu->name() + ".fetch";
 193 }
 194
 195 template <class Impl>
 196 void
 197 DefaultFetch<Impl>::regStats()
 198 {
 199     icacheStallCycles
 200         .name(name() + ".icacheStallCycles")
 201         .desc("Number of cycles fetch is stalled on an Icache miss")
 202         .prereq(icacheStallCycles);
 203
 204     fetchedInsts
 205         .name(name() + ".Insts")
 206         .desc("Number of instructions fetch has processed")
 207         .prereq(fetchedInsts);
 208
 209     fetchedBranches
 210         .name(name() + ".Branches")
 211         .desc("Number of branches that fetch encountered")
 212         .prereq(fetchedBranches);
 213
 214     predictedBranches
 215         .name(name() + ".predictedBranches")
 216         .desc("Number of branches that fetch has predicted taken")
 217         .prereq(predictedBranches);
 218
 219     fetchCycles
 220         .name(name() + ".Cycles")
 221         .desc("Number of cycles fetch has run and was not squashing or"
 222               " blocked")
 223         .prereq(fetchCycles);
 224
 225     fetchSquashCycles
 226         .name(name() + ".SquashCycles")
 227         .desc("Number of cycles fetch has spent squashing")
 228         .prereq(fetchSquashCycles);
 229
 230     fetchIdleCycles
 231         .name(name() + ".IdleCycles")
 232         .desc("Number of cycles fetch was idle")
 233         .prereq(fetchIdleCycles);
 234
 235     fetchBlockedCycles
 236         .name(name() + ".BlockedCycles")
 237         .desc("Number of cycles fetch has spent blocked")
 238         .prereq(fetchBlockedCycles);
 239
 240     fetchedCacheLines
 241         .name(name() + ".CacheLines")
 242         .desc("Number of cache lines fetched")
 243         .prereq(fetchedCacheLines);
 244
 245     fetchMiscStallCycles
 246         .name(name() + ".MiscStallCycles")
 247         .desc("Number of cycles fetch has spent waiting on interrupts, or "
 248               "bad addresses, or out of MSHRs")
 249         .prereq(fetchMiscStallCycles);
 250
 251     fetchIcacheSquashes
 252         .name(name() + ".IcacheSquashes")
 253         .desc("Number of outstanding Icache misses that were squashed")
 254         .prereq(fetchIcacheSquashes);
 255
 256     fetchNisnDist
 257         .init(/* base value */ 0,
 258               /* last value */ fetchWidth,
 259               /* bucket size */ 1)
 260         .name(name() + ".rateDist")
 261         .desc("Number of instructions fetched each cycle (Total)")
 262         .flags(Stats::pdf);
 263
 264     idleRate
 265         .name(name() + ".idleRate")
 266         .desc("Percent of cycles fetch was idle")
 267         .prereq(idleRate);
 268     idleRate = fetchIdleCycles * 100 / cpu->numCycles;
 269
 270     branchRate
 271         .name(name() + ".branchRate")
 272         .desc("Number of branch fetches per cycle")
 273         .flags(Stats::total);
 274     branchRate = fetchedBranches / cpu->numCycles;
 275
 276     fetchRate
 277         .name(name() + ".rate")
 278         .desc("Number of inst fetches per cycle")
 279         .flags(Stats::total);
 280     fetchRate = fetchedInsts / cpu->numCycles;
 281
 282     branchPred.regStats();
 283 }
 284
 285 template<class Impl>
 286 void
 287 DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
 288 {
 289     DPRINTF(Fetch, "Setting the CPU pointer.\n");
 290     cpu = cpu_ptr;
 291
 292     // Name is finally available, so create the port.
 293     icachePort = new IcachePort(this);
 294
 295     icachePort->snoopRangeSent = false;
 296
 297 #if USE_CHECKER
 298     if (cpu->checker) {
 299         cpu->checker->setIcachePort(icachePort);
 300     }
 301 #endif
 302
 303     // Schedule fetch to get the correct PC from the CPU
 304     // scheduleFetchStartupEvent(1);
 305
 306     // Fetch needs to start fetching instructions at the very beginning,
 307     // so it must start up in active state.
 308     switchToActive();
 309 }
 310
 311 template<class Impl>
 312 void
 313 DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
 314 {
 315     DPRINTF(Fetch, "Setting the time buffer pointer.\n");
 316     timeBuffer = time_buffer;
 317
 318     // Create wires to get information from proper places in time buffer.
 319     fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
 320     fromRename = timeBuffer->getWire(-renameToFetchDelay);
 321     fromIEW = timeBuffer->getWire(-iewToFetchDelay);
 322     fromCommit = timeBuffer->getWire(-commitToFetchDelay);
 323 }
 324
 325 template<class Impl>
 326 void
 327 DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
 328 {
 329     DPRINTF(Fetch, "Setting active threads list pointer.\n");
 330     activeThreads = at_ptr;
 331 }
 332
 333 template<class Impl>
 334 void
 335 DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
 336 {
 337     DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
 338     fetchQueue = fq_ptr;
 339
 340     // Create wire to write information to proper place in fetch queue.
 341     toDecode = fetchQueue->getWire(0);
 342 }
 343
 344 template<class Impl>
 345 void
 346 DefaultFetch<Impl>::initStage()
 347 {
 348     // Setup PC and nextPC with initial state.
 349     for (int tid = 0; tid < numThreads; tid++) {
 350         PC[tid] = cpu->readPC(tid);
 351         nextPC[tid] = cpu->readNextPC(tid);
 352 #if ISA_HAS_DELAY_SLOT
 353         nextNPC[tid] = cpu->readNextNPC(tid);
 354 #endif
 355     }
 356 }
 357
 358 template<class Impl>
 359 void
 360 DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
 361 {
 362     unsigned tid = pkt->req->getThreadNum();
 363
 364     DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
 365
 366     // Only change the status if it's still waiting on the icache access
 367     // to return.
 368     if (fetchStatus[tid] != IcacheWaitResponse ||
 369         pkt->req != memReq[tid] ||
 370         isSwitchedOut()) {
 371         ++fetchIcacheSquashes;
 372         delete pkt->req;
 373         delete pkt;
 374         return;
 375     }
 376
 377     memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
 378     cacheDataValid[tid] = true;
 379
 380     if (!drainPending) {
 381         // Wake up the CPU (if it went to sleep and was waiting on
 382         // this completion event).
 383         cpu->wakeCPU();
 384
 385         DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
 386                 tid);
 387
 388         switchToActive();
 389     }
 390
 391     // Only switch to IcacheAccessComplete if we're not stalled as well.
 392     if (checkStall(tid)) {
 393         fetchStatus[tid] = Blocked;
 394     } else {
 395         fetchStatus[tid] = IcacheAccessComplete;
 396     }
 397
 398     // Reset the mem req to NULL.
 399     delete pkt->req;
 400     delete pkt;
 401     memReq[tid] = NULL;
 402 }
 403
 404 template <class Impl>
 405 bool
 406 DefaultFetch<Impl>::drain()
 407 {
 408     // Fetch is ready to drain at any time.
 409     cpu->signalDrained();
 410     drainPending = true;
 411     return true;
 412 }
 413
 414 template <class Impl>
 415 void
 416 DefaultFetch<Impl>::resume()
 417 {
 418     drainPending = false;
 419 }
 420
 421 template <class Impl>
 422 void
 423 DefaultFetch<Impl>::switchOut()
 424 {
 425     switchedOut = true;
 426     // Branch predictor needs to have its state cleared.
 427     branchPred.switchOut();
 428 }
 429
 430 template <class Impl>
 431 void
 432 DefaultFetch<Impl>::takeOverFrom()
 433 {
 434     // Reset all state
 435     for (int i = 0; i < Impl::MaxThreads; ++i) {
 436         stalls[i].decode = 0;
 437         stalls[i].rename = 0;
 438         stalls[i].iew = 0;
 439         stalls[i].commit = 0;
 440         PC[i] = cpu->readPC(i);
 441         nextPC[i] = cpu->readNextPC(i);
 442 #if ISA_HAS_DELAY_SLOT
 443         nextNPC[i] = cpu->readNextNPC(i);
 444         delaySlotInfo[i].branchSeqNum = -1;
 445         delaySlotInfo[i].numInsts = 0;
 446         delaySlotInfo[i].targetAddr = 0;
 447         delaySlotInfo[i].targetReady = false;
 448 #endif
 449         fetchStatus[i] = Running;
 450     }
 451     numInst = 0;
 452     wroteToTimeBuffer = false;
 453     _status = Inactive;
 454     switchedOut = false;
 455     interruptPending = false;
 456     branchPred.takeOverFrom();
 457 }
 458
 459 template <class Impl>
 460 void
 461 DefaultFetch<Impl>::wakeFromQuiesce()
 462 {
 463     DPRINTF(Fetch, "Waking up from quiesce\n");
 464     // Hopefully this is safe
 465     // @todo: Allow other threads to wake from quiesce.
 466     fetchStatus[0] = Running;
 467 }
 468
 469 template <class Impl>
 470 inline void
 471 DefaultFetch<Impl>::switchToActive()
 472 {
 473     if (_status == Inactive) {
 474         DPRINTF(Activity, "Activating stage.\n");
 475
 476         cpu->activateStage(O3CPU::FetchIdx);
 477
 478         _status = Active;
 479     }
 480 }
 481
 482 template <class Impl>
 483 inline void
 484 DefaultFetch<Impl>::switchToInactive()
 485 {
 486     if (_status == Active) {
 487         DPRINTF(Activity, "Deactivating stage.\n");
 488
 489         cpu->deactivateStage(O3CPU::FetchIdx);
 490
 491         _status = Inactive;
 492     }
 493 }
 494
 495 template <class Impl>
 496 bool
 497 DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
 498                                           Addr &next_NPC)
 499 {
 500     // Do branch prediction check here.
 501     // A bit of a misnomer...next_PC is actually the current PC until
 502     // this function updates it.
 503     bool predict_taken;
 504
 505     if (!inst->isControl()) {
 506 #if ISA_HAS_DELAY_SLOT
 507         Addr cur_PC = next_PC;
 508         next_PC  = cur_PC + instSize;      //next_NPC;
 509         next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
 510         inst->setPredTarg(next_NPC);
 511 #else
 512         next_PC = next_PC + instSize;
 513         inst->setPredTarg(next_PC);
 514 #endif
 515         return false;
 516     }
 517
 518     int tid = inst->threadNumber;
 519 #if ISA_HAS_DELAY_SLOT
 520     Addr pred_PC = next_PC;
 521     predict_taken = branchPred.predict(inst, pred_PC, tid);
 522
 523     if (predict_taken) {
 524         DPRINTF(Fetch, "[tid:%i]: Branch predicted to be true.\n", tid);
 525     } else {
 526         DPRINTF(Fetch, "[tid:%i]: Branch predicted to be false.\n", tid);
 527     }
 528
 529     if (predict_taken) {
 530         next_PC = next_NPC;
 531         next_NPC = pred_PC;
 532
 533         // Update delay slot info
 534         ++delaySlotInfo[tid].numInsts;
 535         delaySlotInfo[tid].targetAddr = pred_PC;
 536         DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid,
 537                 delaySlotInfo[tid].numInsts);
 538     } else { // !predict_taken
 539         if (inst->isCondDelaySlot()) {
 540             next_PC = pred_PC;
 541             // The delay slot is skipped here if there is on
 542             // prediction
 543         } else {
 544             next_PC = next_NPC;
 545             // No need to declare a delay slot here since
 546             // there is no for the pred. target to jump
 547         }
 548
 549         next_NPC = next_NPC + instSize;
 550     }
 551 #else
 552     predict_taken = branchPred.predict(inst, next_PC, tid);
 553 #endif
 554
 555     ++fetchedBranches;
 556
 557     if (predict_taken) {
 558         ++predictedBranches;
 559     }
 560
 561     return predict_taken;
 562 }
 563
 564 template <class Impl>
 565 bool
 566 DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
 567 {
 568     Fault fault = NoFault;
 569
 570     //AlphaDep
 571     if (cacheBlocked) {
 572         DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
 573                 tid);
 574         return false;
 575     } else if (isSwitchedOut()) {
 576         DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
 577                 tid);
 578         return false;
 579     } else if (interruptPending && !(fetch_PC & 0x3)) {
 580         // Hold off fetch from getting new instructions when:
 581         // Cache is blocked, or
 582         // while an interrupt is pending and we're not in PAL mode, or
 583         // fetch is switched out.
 584         DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
 585                 tid);
 586         return false;
 587     }
 588
 589     // Align the fetch PC so it's at the start of a cache block.
 590     Addr block_PC = icacheBlockAlignPC(fetch_PC);
 591
 592     // If we've already got the block, no need to try to fetch it again.
 593     if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
 594         return true;
 595     }
 596
 597     // Setup the memReq to do a read of the first instruction's address.
 598     // Set the appropriate read size and flags as well.
 599     // Build request here.
 600     RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
 601                                      fetch_PC, cpu->readCpuId(), tid);
 602
 603     memReq[tid] = mem_req;
 604
 605     // Translate the instruction request.
 606     fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
 607
 608     // In the case of faults, the fetch stage may need to stall and wait
 609     // for the ITB miss to be handled.
 610
 611     // If translation was successful, attempt to read the first
 612     // instruction.
 613     if (fault == NoFault) {
 614 #if 0
 615         if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
 616             memReq[tid]->isUncacheable()) {
 617             DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
 618                     "misspeculating path)!",
 619                     memReq[tid]->paddr);
 620             ret_fault = TheISA::genMachineCheckFault();
 621             return false;
 622         }
 623 #endif
 624
 625         // Build packet here.
 626         PacketPtr data_pkt = new Packet(mem_req,
 627                                         Packet::ReadReq, Packet::Broadcast);
 628         data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
 629
 630         cacheDataPC[tid] = block_PC;
 631         cacheDataValid[tid] = false;
 632
 633         DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
 634
 635         fetchedCacheLines++;
 636
 637         // Now do the timing access to see whether or not the instruction
 638         // exists within the cache.
 639         if (!icachePort->sendTiming(data_pkt)) {
 640             if (data_pkt->result == Packet::BadAddress) {
 641                 fault = TheISA::genMachineCheckFault();
 642                 delete mem_req;
 643                 memReq[tid] = NULL;
 644             }
 645             assert(retryPkt == NULL);
 646             assert(retryTid == -1);
 647             DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
 648             fetchStatus[tid] = IcacheWaitRetry;
 649             retryPkt = data_pkt;
 650             retryTid = tid;
 651             cacheBlocked = true;
 652             return false;
 653         }
 654
 655         DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
 656
 657         lastIcacheStall[tid] = curTick;
 658
 659         DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
 660                 "response.\n", tid);
 661
 662         fetchStatus[tid] = IcacheWaitResponse;
 663     } else {
 664         delete mem_req;
 665         memReq[tid] = NULL;
 666     }
 667
 668     ret_fault = fault;
 669     return true;
 670 }
 671
 672 template <class Impl>
 673 inline void
 674 DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
 675 {
 676     DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
 677             tid, new_PC);
 678
 679     PC[tid] = new_PC;
 680     nextPC[tid] = new_PC + instSize;
 681     nextNPC[tid] = new_PC + (2 * instSize);
 682
 683     // Clear the icache miss if it's outstanding.
 684     if (fetchStatus[tid] == IcacheWaitResponse) {
 685         DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
 686                 tid);
 687         memReq[tid] = NULL;
 688     }
 689
 690     // Get rid of the retrying packet if it was from this thread.
 691     if (retryTid == tid) {
 692         assert(cacheBlocked);
 693         cacheBlocked = false;
 694         retryTid = -1;
 695         delete retryPkt->req;
 696         delete retryPkt;
 697         retryPkt = NULL;
 698     }
 699
 700     fetchStatus[tid] = Squashing;
 701
 702     ++fetchSquashCycles;
 703 }
 704
 705 template<class Impl>
 706 void
 707 DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
 708                                      const InstSeqNum &seq_num,
 709                                      unsigned tid)
 710 {
 711     DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
 712
 713     doSquash(new_PC, tid);
 714
 715 #if ISA_HAS_DELAY_SLOT
 716     if (seq_num <=  delaySlotInfo[tid].branchSeqNum) {
 717         delaySlotInfo[tid].numInsts = 0;
 718         delaySlotInfo[tid].targetAddr = 0;
 719         delaySlotInfo[tid].targetReady = false;
 720     }
 721 #endif
 722
 723     // Tell the CPU to remove any instructions that are in flight between
 724     // fetch and decode.
 725     cpu->removeInstsUntil(seq_num, tid);
 726 }
 727
 728 template<class Impl>
 729 bool
 730 DefaultFetch<Impl>::checkStall(unsigned tid) const
 731 {
 732     bool ret_val = false;
 733
 734     if (cpu->contextSwitch) {
 735         DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
 736         ret_val = true;
 737     } else if (stalls[tid].decode) {
 738         DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
 739         ret_val = true;
 740     } else if (stalls[tid].rename) {
 741         DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
 742         ret_val = true;
 743     } else if (stalls[tid].iew) {
 744         DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
 745         ret_val = true;
 746     } else if (stalls[tid].commit) {
 747         DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
 748         ret_val = true;
 749     }
 750
 751     return ret_val;
 752 }
 753
 754 template<class Impl>
 755 typename DefaultFetch<Impl>::FetchStatus
 756 DefaultFetch<Impl>::updateFetchStatus()
 757 {
 758     //Check Running
 759     std::list<unsigned>::iterator threads = (*activeThreads).begin();
 760
 761     while (threads != (*activeThreads).end()) {
 762
 763         unsigned tid = *threads++;
 764
 765         if (fetchStatus[tid] == Running ||
 766             fetchStatus[tid] == Squashing ||
 767             fetchStatus[tid] == IcacheAccessComplete) {
 768
 769             if (_status == Inactive) {
 770                 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
 771
 772                 if (fetchStatus[tid] == IcacheAccessComplete) {
 773                     DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
 774                             "completion\n",tid);
 775                 }
 776
 777                 cpu->activateStage(O3CPU::FetchIdx);
 778             }
 779
 780             return Active;
 781         }
 782     }
 783
 784     // Stage is switching from active to inactive, notify CPU of it.
 785     if (_status == Active) {
 786         DPRINTF(Activity, "Deactivating stage.\n");
 787
 788         cpu->deactivateStage(O3CPU::FetchIdx);
 789     }
 790
 791     return Inactive;
 792 }
 793
 794 template <class Impl>
 795 void
 796 DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
 797                            bool squash_delay_slot, unsigned tid)
 798 {
 799     DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
 800
 801     doSquash(new_PC, tid);
 802
 803 #if ISA_HAS_DELAY_SLOT
 804     if (seq_num <=  delaySlotInfo[tid].branchSeqNum) {
 805         delaySlotInfo[tid].numInsts = 0;
 806         delaySlotInfo[tid].targetAddr = 0;
 807         delaySlotInfo[tid].targetReady = false;
 808     }
 809
 810     // Tell the CPU to remove any instructions that are not in the ROB.
 811     cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
 812 #else
 813     // Tell the CPU to remove any instructions that are not in the ROB.
 814     cpu->removeInstsNotInROB(tid, true, 0);
 815 #endif
 816 }
 817
 818 template <class Impl>
 819 void
 820 DefaultFetch<Impl>::tick()
 821 {
 822     std::list<unsigned>::iterator threads = (*activeThreads).begin();
 823     bool status_change = false;
 824
 825     wroteToTimeBuffer = false;
 826
 827     while (threads != (*activeThreads).end()) {
 828         unsigned tid = *threads++;
 829
 830         // Check the signals for each thread to determine the proper status
 831         // for each thread.
 832         bool updated_status = checkSignalsAndUpdate(tid);
 833         status_change =  status_change || updated_status;
 834     }
 835
 836     DPRINTF(Fetch, "Running stage.\n");
 837
 838     // Reset the number of the instruction we're fetching.
 839     numInst = 0;
 840
 841 #if FULL_SYSTEM
 842     if (fromCommit->commitInfo[0].interruptPending) {
 843         interruptPending = true;
 844     }
 845
 846     if (fromCommit->commitInfo[0].clearInterrupt) {
 847         interruptPending = false;
 848     }
 849 #endif
 850
 851     for (threadFetched = 0; threadFetched < numFetchingThreads;
 852          threadFetched++) {
 853         // Fetch each of the actively fetching threads.
 854         fetch(status_change);
 855     }
 856
 857     // Record number of instructions fetched this cycle for distribution.
 858     fetchNisnDist.sample(numInst);
 859
 860     if (status_change) {
 861         // Change the fetch stage status if there was a status change.
 862         _status = updateFetchStatus();
 863     }
 864
 865     // If there was activity this cycle, inform the CPU of it.
 866     if (wroteToTimeBuffer || cpu->contextSwitch) {
 867         DPRINTF(Activity, "Activity this cycle.\n");
 868
 869         cpu->activityThisCycle();
 870     }
 871 }
 872
 873 template <class Impl>
 874 bool
 875 DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
 876 {
 877     // Update the per thread stall statuses.
 878     if (fromDecode->decodeBlock[tid]) {
 879         stalls[tid].decode = true;
 880     }
 881
 882     if (fromDecode->decodeUnblock[tid]) {
 883         assert(stalls[tid].decode);
 884         assert(!fromDecode->decodeBlock[tid]);
 885         stalls[tid].decode = false;
 886     }
 887
 888     if (fromRename->renameBlock[tid]) {
 889         stalls[tid].rename = true;
 890     }
 891
 892     if (fromRename->renameUnblock[tid]) {
 893         assert(stalls[tid].rename);
 894         assert(!fromRename->renameBlock[tid]);
 895         stalls[tid].rename = false;
 896     }
 897
 898     if (fromIEW->iewBlock[tid]) {
 899         stalls[tid].iew = true;
 900     }
 901
 902     if (fromIEW->iewUnblock[tid]) {
 903         assert(stalls[tid].iew);
 904         assert(!fromIEW->iewBlock[tid]);
 905         stalls[tid].iew = false;
 906     }
 907
 908     if (fromCommit->commitBlock[tid]) {
 909         stalls[tid].commit = true;
 910     }
 911
 912     if (fromCommit->commitUnblock[tid]) {
 913         assert(stalls[tid].commit);
 914         assert(!fromCommit->commitBlock[tid]);
 915         stalls[tid].commit = false;
 916     }
 917
 918     // Check squash signals from commit.
 919     if (fromCommit->commitInfo[tid].squash) {
 920
 921         DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
 922                 "from commit.\n",tid);
 923
 924 #if ISA_HAS_DELAY_SLOT
 925     InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
 926 #else
 927     InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
 928 #endif
 929         // In any case, squash.
 930         squash(fromCommit->commitInfo[tid].nextPC,
 931                doneSeqNum,
 932                fromCommit->commitInfo[tid].squashDelaySlot,
 933                tid);
 934
 935         // Also check if there's a mispredict that happened.
 936         if (fromCommit->commitInfo[tid].branchMispredict) {
 937             branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
 938                               fromCommit->commitInfo[tid].nextPC,
 939                               fromCommit->commitInfo[tid].branchTaken,
 940                               tid);
 941         } else {
 942             branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
 943                               tid);
 944         }
 945
 946         return true;
 947     } else if (fromCommit->commitInfo[tid].doneSeqNum) {
 948         // Update the branch predictor if it wasn't a squashed instruction
 949         // that was broadcasted.
 950         branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
 951     }
 952
 953     // Check ROB squash signals from commit.
 954     if (fromCommit->commitInfo[tid].robSquashing) {
 955         DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
 956
 957         // Continue to squash.
 958         fetchStatus[tid] = Squashing;
 959
 960         return true;
 961     }
 962
 963     // Check squash signals from decode.
 964     if (fromDecode->decodeInfo[tid].squash) {
 965         DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
 966                 "from decode.\n",tid);
 967
 968         // Update the branch predictor.
 969         if (fromDecode->decodeInfo[tid].branchMispredict) {
 970             branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
 971                               fromDecode->decodeInfo[tid].nextPC,
 972                               fromDecode->decodeInfo[tid].branchTaken,
 973                               tid);
 974         } else {
 975             branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
 976                               tid);
 977         }
 978
 979         if (fetchStatus[tid] != Squashing) {
 980
 981 #if ISA_HAS_DELAY_SLOT
 982             InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
 983 #else
 984             InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
 985 #endif
 986             // Squash unless we're already squashing
 987             squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
 988                              doneSeqNum,
 989                              tid);
 990
 991             return true;
 992         }
 993     }
 994
 995     if (checkStall(tid) &&
 996         fetchStatus[tid] != IcacheWaitResponse &&
 997         fetchStatus[tid] != IcacheWaitRetry) {
 998         DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
 999
1000         fetchStatus[tid] = Blocked;
1001
1002         return true;
1003     }
1004
1005     if (fetchStatus[tid] == Blocked ||
1006         fetchStatus[tid] == Squashing) {
1007         // Switch status to running if fetch isn't being told to block or
1008         // squash this cycle.
1009         DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
1010                 tid);
1011
1012         fetchStatus[tid] = Running;
1013
1014         return true;
1015     }
1016
1017     // If we've reached this point, we have not gotten any signals that
1018     // cause fetch to change its status.  Fetch remains the same as before.
1019     return false;
1020 }
1021
1022 template<class Impl>
1023 void
1024 DefaultFetch<Impl>::fetch(bool &status_change)
1025 {
1026     //////////////////////////////////////////
1027     // Start actual fetch
1028     //////////////////////////////////////////
1029     int tid = getFetchingThread(fetchPolicy);
1030
1031     if (tid == -1 || drainPending) {
1032         DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1033
1034         // Breaks looping condition in tick()
1035         threadFetched = numFetchingThreads;
1036         return;
1037     }
1038
1039     DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1040
1041     // The current PC.
1042     Addr &fetch_PC = PC[tid];
1043
1044     // Fault code for memory access.
1045     Fault fault = NoFault;
1046
1047     // If returning from the delay of a cache miss, then update the status
1048     // to running, otherwise do the cache access.  Possibly move this up
1049     // to tick() function.
1050     if (fetchStatus[tid] == IcacheAccessComplete) {
1051         DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1052                 tid);
1053
1054         fetchStatus[tid] = Running;
1055         status_change = true;
1056     } else if (fetchStatus[tid] == Running) {
1057         DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1058                 "instruction, starting at PC %08p.\n",
1059                 tid, fetch_PC);
1060
1061         bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1062         if (!fetch_success) {
1063             if (cacheBlocked) {
1064                 ++icacheStallCycles;
1065             } else {
1066                 ++fetchMiscStallCycles;
1067             }
1068             return;
1069         }
1070     } else {
1071         if (fetchStatus[tid] == Idle) {
1072             ++fetchIdleCycles;
1073             DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1074         } else if (fetchStatus[tid] == Blocked) {
1075             ++fetchBlockedCycles;
1076             DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1077         } else if (fetchStatus[tid] == Squashing) {
1078             ++fetchSquashCycles;
1079             DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1080         } else if (fetchStatus[tid] == IcacheWaitResponse) {
1081             ++icacheStallCycles;
1082             DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid);
1083         }
1084
1085         // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1086         // fetch should do nothing.
1087         return;
1088     }
1089
1090     ++fetchCycles;
1091
1092     // If we had a stall due to an icache miss, then return.
1093     if (fetchStatus[tid] == IcacheWaitResponse) {
1094         ++icacheStallCycles;
1095         status_change = true;
1096         return;
1097     }
1098
1099     Addr next_PC = fetch_PC;
1100     Addr next_NPC = next_PC + instSize;
1101     InstSeqNum inst_seq;
1102     MachInst inst;
1103     ExtMachInst ext_inst;
1104     // @todo: Fix this hack.
1105     unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1106
1107     if (fault == NoFault) {
1108         // If the read of the first instruction was successful, then grab the
1109         // instructions from the rest of the cache line and put them into the
1110         // queue heading to decode.
1111
1112         DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1113                 "decode.\n",tid);
1114
1115         // Need to keep track of whether or not a predicted branch
1116         // ended this fetch block.
1117         bool predicted_branch = false;
1118
1119         // Need to keep track of whether or not a delay slot
1120         // instruction has been fetched
1121
1122         for (;
1123              offset < cacheBlkSize &&
1124                  numInst < fetchWidth &&
1125                  (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
1126              ++numInst) {
1127
1128             // Get a sequence number.
1129             inst_seq = cpu->getAndIncrementInstSeq();
1130
1131             // Make sure this is a valid index.
1132             assert(offset <= cacheBlkSize - instSize);
1133
1134             // Get the instruction from the array of the cache line.
1135             inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1136                         (&cacheData[tid][offset]));
1137
1138 #if THE_ISA == ALPHA_ISA
1139             ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1140 #elif THE_ISA == SPARC_ISA
1141             ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
1142 #endif
1143
1144             // Create a new DynInst from the instruction fetched.
1145             DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1146                                                  next_PC,
1147                                                  inst_seq, cpu);
1148             instruction->setTid(tid);
1149
1150             instruction->setASID(tid);
1151
1152             instruction->setThreadState(cpu->thread[tid]);
1153
1154             DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1155                     "[sn:%lli]\n",
1156                     tid, instruction->readPC(), inst_seq);
1157
1158             DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1159                     tid, instruction->staticInst->disassemble(fetch_PC));
1160
1161             instruction->traceData =
1162                 Trace::getInstRecord(curTick, cpu->tcBase(tid),
1163                                      instruction->staticInst,
1164                                      instruction->readPC());
1165
1166             predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
1167                                                      next_NPC);
1168
1169             // Add instruction to the CPU's list of instructions.
1170             instruction->setInstListIt(cpu->addInst(instruction));
1171
1172             // Write the instruction to the first slot in the queue
1173             // that heads to decode.
1174             toDecode->insts[numInst] = instruction;
1175
1176             toDecode->size++;
1177
1178             // Increment stat of fetched instructions.
1179             ++fetchedInsts;
1180
1181             // Move to the next instruction, unless we have a branch.
1182             fetch_PC = next_PC;
1183
1184             if (instruction->isQuiesce()) {
1185                 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1186                         curTick);
1187                 fetchStatus[tid] = QuiescePending;
1188                 ++numInst;
1189                 status_change = true;
1190                 break;
1191             }
1192
1193             offset += instSize;
1194
1195 #if ISA_HAS_DELAY_SLOT
1196             if (predicted_branch) {
1197                 delaySlotInfo[tid].branchSeqNum = inst_seq;
1198
1199                 DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
1200                         tid, inst_seq);
1201                 continue;
1202             } else if (delaySlotInfo[tid].numInsts > 0) {
1203                 --delaySlotInfo[tid].numInsts;
1204
1205                 // It's OK to set PC to target of branch
1206                 if (delaySlotInfo[tid].numInsts == 0) {
1207                     delaySlotInfo[tid].targetReady = true;
1208
1209                     // Break the looping condition
1210                     predicted_branch = true;
1211                 }
1212
1213                 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
1214                         " process.\n", tid, delaySlotInfo[tid].numInsts);
1215             }
1216 #endif
1217         }
1218
1219         if (offset >= cacheBlkSize) {
1220             DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1221                     "block.\n", tid);
1222         } else if (numInst >= fetchWidth) {
1223             DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1224                     "for this cycle.\n", tid);
1225         } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
1226             DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1227                     "instruction encountered.\n", tid);
1228         }
1229     }
1230
1231     if (numInst > 0) {
1232         wroteToTimeBuffer = true;
1233     }
1234
1235     // Now that fetching is completed, update the PC to signify what the next
1236     // cycle will be.
1237     if (fault == NoFault) {
1238 #if ISA_HAS_DELAY_SLOT
1239         if (delaySlotInfo[tid].targetReady &&
1240             delaySlotInfo[tid].numInsts == 0) {
1241             // Set PC to target
1242             PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
1243             nextPC[tid] = next_PC + instSize;        //next_NPC
1244             nextNPC[tid] = next_PC + (2 * instSize);
1245
1246             delaySlotInfo[tid].targetReady = false;
1247         } else {
1248             PC[tid] = next_PC;
1249             nextPC[tid] = next_NPC;
1250             nextNPC[tid] = next_NPC + instSize;
1251         }
1252
1253         DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
1254 #else
1255         DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1256         PC[tid] = next_PC;
1257         nextPC[tid] = next_PC + instSize;
1258 #endif
1259     } else {
1260         // We shouldn't be in an icache miss and also have a fault (an ITB
1261         // miss)
1262         if (fetchStatus[tid] == IcacheWaitResponse) {
1263             panic("Fetch should have exited prior to this!");
1264         }
1265
1266         // Send the fault to commit.  This thread will not do anything
1267         // until commit handles the fault.  The only other way it can
1268         // wake up is if a squash comes along and changes the PC.
1269 #if FULL_SYSTEM
1270         assert(numInst != fetchWidth);
1271         // Get a sequence number.
1272         inst_seq = cpu->getAndIncrementInstSeq();
1273         // We will use a nop in order to carry the fault.
1274         ext_inst = TheISA::NoopMachInst;
1275
1276         // Create a new DynInst from the dummy nop.
1277         DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1278                                              next_PC,
1279                                              inst_seq, cpu);
1280         instruction->setPredTarg(next_PC + instSize);
1281         instruction->setTid(tid);
1282
1283         instruction->setASID(tid);
1284
1285         instruction->setThreadState(cpu->thread[tid]);
1286
1287         instruction->traceData = NULL;
1288
1289         instruction->setInstListIt(cpu->addInst(instruction));
1290
1291         instruction->fault = fault;
1292
1293         toDecode->insts[numInst] = instruction;
1294         toDecode->size++;
1295
1296         DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1297
1298         fetchStatus[tid] = TrapPending;
1299         status_change = true;
1300 #else // !FULL_SYSTEM
1301         fetchStatus[tid] = TrapPending;
1302         status_change = true;
1303
1304 #endif // FULL_SYSTEM
1305         DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
1306                 tid, fault->name(), PC[tid]);
1307     }
1308 }
1309
1310 template<class Impl>
1311 void
1312 DefaultFetch<Impl>::recvRetry()
1313 {
1314     if (retryPkt != NULL) {
1315         assert(cacheBlocked);
1316         assert(retryTid != -1);
1317         assert(fetchStatus[retryTid] == IcacheWaitRetry);
1318
1319         if (icachePort->sendTiming(retryPkt)) {
1320             fetchStatus[retryTid] = IcacheWaitResponse;
1321             retryPkt = NULL;
1322             retryTid = -1;
1323             cacheBlocked = false;
1324         }
1325     } else {
1326         assert(retryTid == -1);
1327         // Access has been squashed since it was sent out.  Just clear
1328         // the cache being blocked.
1329         cacheBlocked = false;
1330     }
1331 }
1332
1333 ///////////////////////////////////////
1334 //                                   //
1335 //  SMT FETCH POLICY MAINTAINED HERE //
1336 //                                   //
1337 ///////////////////////////////////////
1338 template<class Impl>
1339 int
1340 DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1341 {
1342     if (numThreads > 1) {
1343         switch (fetch_priority) {
1344
1345           case SingleThread:
1346             return 0;
1347
1348           case RoundRobin:
1349             return roundRobin();
1350
1351           case IQ:
1352             return iqCount();
1353
1354           case LSQ:
1355             return lsqCount();
1356
1357           case Branch:
1358             return branchCount();
1359
1360           default:
1361             return -1;
1362         }
1363     } else {
1364         int tid = *((*activeThreads).begin());
1365
1366         if (fetchStatus[tid] == Running ||
1367             fetchStatus[tid] == IcacheAccessComplete ||
1368             fetchStatus[tid] == Idle) {
1369             return tid;
1370         } else {
1371             return -1;
1372         }
1373     }
1374
1375 }
1376
1377
1378 template<class Impl>
1379 int
1380 DefaultFetch<Impl>::roundRobin()
1381 {
1382     std::list<unsigned>::iterator pri_iter = priorityList.begin();
1383     std::list<unsigned>::iterator end      = priorityList.end();
1384
1385     int high_pri;
1386
1387     while (pri_iter != end) {
1388         high_pri = *pri_iter;
1389
1390         assert(high_pri <= numThreads);
1391
1392         if (fetchStatus[high_pri] == Running ||
1393             fetchStatus[high_pri] == IcacheAccessComplete ||
1394             fetchStatus[high_pri] == Idle) {
1395
1396             priorityList.erase(pri_iter);
1397             priorityList.push_back(high_pri);
1398
1399             return high_pri;
1400         }
1401
1402         pri_iter++;
1403     }
1404
1405     return -1;
1406 }
1407
1408 template<class Impl>
1409 int
1410 DefaultFetch<Impl>::iqCount()
1411 {
1412     std::priority_queue<unsigned> PQ;
1413
1414     std::list<unsigned>::iterator threads = (*activeThreads).begin();
1415
1416     while (threads != (*activeThreads).end()) {
1417         unsigned tid = *threads++;
1418
1419         PQ.push(fromIEW->iewInfo[tid].iqCount);
1420     }
1421
1422     while (!PQ.empty()) {
1423
1424         unsigned high_pri = PQ.top();
1425
1426         if (fetchStatus[high_pri] == Running ||
1427             fetchStatus[high_pri] == IcacheAccessComplete ||
1428             fetchStatus[high_pri] == Idle)
1429             return high_pri;
1430         else
1431             PQ.pop();
1432
1433     }
1434
1435     return -1;
1436 }
1437
1438 template<class Impl>
1439 int
1440 DefaultFetch<Impl>::lsqCount()
1441 {
1442     std::priority_queue<unsigned> PQ;
1443
1444
1445     std::list<unsigned>::iterator threads = (*activeThreads).begin();
1446
1447     while (threads != (*activeThreads).end()) {
1448         unsigned tid = *threads++;
1449
1450         PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1451     }
1452
1453     while (!PQ.empty()) {
1454
1455         unsigned high_pri = PQ.top();
1456
1457         if (fetchStatus[high_pri] == Running ||
1458             fetchStatus[high_pri] == IcacheAccessComplete ||
1459             fetchStatus[high_pri] == Idle)
1460             return high_pri;
1461         else
1462             PQ.pop();
1463
1464     }
1465
1466     return -1;
1467 }
1468
1469 template<class Impl>
1470 int
1471 DefaultFetch<Impl>::branchCount()
1472 {
1473     std::list<unsigned>::iterator threads = (*activeThreads).begin();
1474     panic("Branch Count Fetch policy unimplemented\n");
1475     return *threads;
1476 }