2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include "arch/isa_traits.hh"
36 #include "arch/utility.hh"
37 #include "base/types.hh"
38 #include "config/use_checker.hh"
39 #include "cpu/checker/cpu.hh"
40 #include "cpu/exetrace.hh"
41 #include "cpu/o3/fetch.hh"
42 #include "mem/packet.hh"
43 #include "mem/request.hh"
44 #include "params/DerivO3CPU.hh"
45 #include "sim/byteswap.hh"
46 #include "sim/core.hh"
49 #include "arch/tlb.hh"
50 #include "arch/vtophys.hh"
51 #include "sim/system.hh"
56 DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
65 DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
67 panic("DefaultFetch doesn't expect recvAtomic callback!");
73 DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
75 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
81 DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
83 if (status == RangeChange) {
84 if (!snoopRangeSent) {
85 snoopRangeSent = true;
86 sendStatusChange(Port::RangeChange);
91 panic("DefaultFetch doesn't expect recvStatusChange callback!");
96 DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
98 DPRINTF(Fetch, "Received timing\n");
99 if (pkt->isResponse()) {
100 fetch->processCacheCompletion(pkt);
102 //else Snooped a coherence request, just return
108 DefaultFetch<Impl>::IcachePort::recvRetry()
114 DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
118 decodeToFetchDelay(params->decodeToFetchDelay),
119 renameToFetchDelay(params->renameToFetchDelay),
120 iewToFetchDelay(params->iewToFetchDelay),
121 commitToFetchDelay(params->commitToFetchDelay),
122 fetchWidth(params->fetchWidth),
126 numThreads(params->numThreads),
127 numFetchingThreads(params->smtNumFetchingThreads),
128 interruptPending(false),
132 if (numThreads > Impl::MaxThreads)
133 fatal("numThreads (%d) is larger than compiled limit (%d),\n"
134 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n",
135 numThreads, static_cast<int>(Impl::MaxThreads));
137 // Set fetch stage's status to inactive.
140 std::string policy = params->smtFetchPolicy;
142 // Convert string to lowercase
143 std::transform(policy.begin(), policy.end(), policy.begin(),
144 (int(*)(int)) tolower);
146 // Figure out fetch policy
147 if (policy == "singlethread") {
148 fetchPolicy = SingleThread;
150 panic("Invalid Fetch Policy for a SMT workload.");
151 } else if (policy == "roundrobin") {
152 fetchPolicy = RoundRobin;
153 DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
154 } else if (policy == "branch") {
155 fetchPolicy = Branch;
156 DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
157 } else if (policy == "iqcount") {
159 DPRINTF(Fetch, "Fetch policy set to IQ count\n");
160 } else if (policy == "lsqcount") {
162 DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
164 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
165 " RoundRobin,LSQcount,IQcount}\n");
168 // Get the size of an instruction.
169 instSize = sizeof(TheISA::MachInst);
171 // Name is finally available, so create the port.
172 icachePort = new IcachePort(this);
174 icachePort->snoopRangeSent = false;
178 cpu->checker->setIcachePort(icachePort);
183 template <class Impl>
185 DefaultFetch<Impl>::name() const
187 return cpu->name() + ".fetch";
190 template <class Impl>
192 DefaultFetch<Impl>::regStats()
195 .name(name() + ".icacheStallCycles")
196 .desc("Number of cycles fetch is stalled on an Icache miss")
197 .prereq(icacheStallCycles);
200 .name(name() + ".Insts")
201 .desc("Number of instructions fetch has processed")
202 .prereq(fetchedInsts);
205 .name(name() + ".Branches")
206 .desc("Number of branches that fetch encountered")
207 .prereq(fetchedBranches);
210 .name(name() + ".predictedBranches")
211 .desc("Number of branches that fetch has predicted taken")
212 .prereq(predictedBranches);
215 .name(name() + ".Cycles")
216 .desc("Number of cycles fetch has run and was not squashing or"
218 .prereq(fetchCycles);
221 .name(name() + ".SquashCycles")
222 .desc("Number of cycles fetch has spent squashing")
223 .prereq(fetchSquashCycles);
226 .name(name() + ".IdleCycles")
227 .desc("Number of cycles fetch was idle")
228 .prereq(fetchIdleCycles);
231 .name(name() + ".BlockedCycles")
232 .desc("Number of cycles fetch has spent blocked")
233 .prereq(fetchBlockedCycles);
236 .name(name() + ".CacheLines")
237 .desc("Number of cache lines fetched")
238 .prereq(fetchedCacheLines);
241 .name(name() + ".MiscStallCycles")
242 .desc("Number of cycles fetch has spent waiting on interrupts, or "
243 "bad addresses, or out of MSHRs")
244 .prereq(fetchMiscStallCycles);
247 .name(name() + ".IcacheSquashes")
248 .desc("Number of outstanding Icache misses that were squashed")
249 .prereq(fetchIcacheSquashes);
252 .init(/* base value */ 0,
253 /* last value */ fetchWidth,
255 .name(name() + ".rateDist")
256 .desc("Number of instructions fetched each cycle (Total)")
260 .name(name() + ".idleRate")
261 .desc("Percent of cycles fetch was idle")
263 idleRate = fetchIdleCycles * 100 / cpu->numCycles;
266 .name(name() + ".branchRate")
267 .desc("Number of branch fetches per cycle")
268 .flags(Stats::total);
269 branchRate = fetchedBranches / cpu->numCycles;
272 .name(name() + ".rate")
273 .desc("Number of inst fetches per cycle")
274 .flags(Stats::total);
275 fetchRate = fetchedInsts / cpu->numCycles;
277 branchPred.regStats();
282 DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
284 timeBuffer = time_buffer;
286 // Create wires to get information from proper places in time buffer.
287 fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
288 fromRename = timeBuffer->getWire(-renameToFetchDelay);
289 fromIEW = timeBuffer->getWire(-iewToFetchDelay);
290 fromCommit = timeBuffer->getWire(-commitToFetchDelay);
295 DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
297 activeThreads = at_ptr;
302 DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
306 // Create wire to write information to proper place in fetch queue.
307 toDecode = fetchQueue->getWire(0);
312 DefaultFetch<Impl>::initStage()
314 // Setup PC and nextPC with initial state.
315 for (int tid = 0; tid < numThreads; tid++) {
316 PC[tid] = cpu->readPC(tid);
317 nextPC[tid] = cpu->readNextPC(tid);
318 microPC[tid] = cpu->readMicroPC(tid);
321 for (int tid=0; tid < numThreads; tid++) {
323 fetchStatus[tid] = Running;
325 priorityList.push_back(tid);
329 stalls[tid].decode = false;
330 stalls[tid].rename = false;
331 stalls[tid].iew = false;
332 stalls[tid].commit = false;
335 // Schedule fetch to get the correct PC from the CPU
336 // scheduleFetchStartupEvent(1);
338 // Fetch needs to start fetching instructions at the very beginning,
339 // so it must start up in active state.
345 DefaultFetch<Impl>::setIcache()
347 // Size of cache block.
348 cacheBlkSize = icachePort->peerBlockSize();
350 // Create mask to get rid of offset bits.
351 cacheBlkMask = (cacheBlkSize - 1);
353 for (int tid=0; tid < numThreads; tid++) {
354 // Create space to store a cache line.
355 cacheData[tid] = new uint8_t[cacheBlkSize];
356 cacheDataPC[tid] = 0;
357 cacheDataValid[tid] = false;
363 DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
365 unsigned tid = pkt->req->threadId();
367 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
369 assert(!pkt->wasNacked());
371 // Only change the status if it's still waiting on the icache access
373 if (fetchStatus[tid] != IcacheWaitResponse ||
374 pkt->req != memReq[tid] ||
376 ++fetchIcacheSquashes;
382 memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
383 cacheDataValid[tid] = true;
386 // Wake up the CPU (if it went to sleep and was waiting on
387 // this completion event).
390 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
396 // Only switch to IcacheAccessComplete if we're not stalled as well.
397 if (checkStall(tid)) {
398 fetchStatus[tid] = Blocked;
400 fetchStatus[tid] = IcacheAccessComplete;
403 // Reset the mem req to NULL.
409 template <class Impl>
411 DefaultFetch<Impl>::drain()
413 // Fetch is ready to drain at any time.
414 cpu->signalDrained();
419 template <class Impl>
421 DefaultFetch<Impl>::resume()
423 drainPending = false;
426 template <class Impl>
428 DefaultFetch<Impl>::switchOut()
431 // Branch predictor needs to have its state cleared.
432 branchPred.switchOut();
435 template <class Impl>
437 DefaultFetch<Impl>::takeOverFrom()
440 for (int i = 0; i < Impl::MaxThreads; ++i) {
441 stalls[i].decode = 0;
442 stalls[i].rename = 0;
444 stalls[i].commit = 0;
445 PC[i] = cpu->readPC(i);
446 nextPC[i] = cpu->readNextPC(i);
447 microPC[i] = cpu->readMicroPC(i);
448 fetchStatus[i] = Running;
451 wroteToTimeBuffer = false;
454 interruptPending = false;
455 branchPred.takeOverFrom();
458 template <class Impl>
460 DefaultFetch<Impl>::wakeFromQuiesce()
462 DPRINTF(Fetch, "Waking up from quiesce\n");
463 // Hopefully this is safe
464 // @todo: Allow other threads to wake from quiesce.
465 fetchStatus[0] = Running;
468 template <class Impl>
470 DefaultFetch<Impl>::switchToActive()
472 if (_status == Inactive) {
473 DPRINTF(Activity, "Activating stage.\n");
475 cpu->activateStage(O3CPU::FetchIdx);
481 template <class Impl>
483 DefaultFetch<Impl>::switchToInactive()
485 if (_status == Active) {
486 DPRINTF(Activity, "Deactivating stage.\n");
488 cpu->deactivateStage(O3CPU::FetchIdx);
494 template <class Impl>
496 DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
497 Addr &next_NPC, Addr &next_MicroPC)
499 // Do branch prediction check here.
500 // A bit of a misnomer...next_PC is actually the current PC until
501 // this function updates it.
504 if (!inst->isControl()) {
505 if (inst->isMicroop() && !inst->isLastMicroop()) {
509 next_NPC = next_NPC + instSize;
512 inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
513 inst->setPredTaken(false);
517 //Assume for now that all control flow is to a different macroop which
518 //would reset the micro pc to 0.
521 int tid = inst->threadNumber;
522 Addr pred_PC = next_PC;
523 predict_taken = branchPred.predict(inst, pred_PC, tid);
526 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %#x.\n",
527 tid, inst->seqNum, pred_PC);
529 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
533 #if ISA_HAS_DELAY_SLOT
538 next_NPC += instSize;
544 next_NPC = next_PC + instSize;
547 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %#x and then %#x.\n",
548 tid, inst->seqNum, next_PC, next_NPC);
549 inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
550 inst->setPredTaken(predict_taken);
558 return predict_taken;
561 template <class Impl>
563 DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
565 Fault fault = NoFault;
569 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
572 } else if (isSwitchedOut()) {
573 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
576 } else if (interruptPending && !(fetch_PC & 0x3)) {
577 // Hold off fetch from getting new instructions when:
578 // Cache is blocked, or
579 // while an interrupt is pending and we're not in PAL mode, or
580 // fetch is switched out.
581 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
586 // Align the fetch PC so it's at the start of a cache block.
587 Addr block_PC = icacheBlockAlignPC(fetch_PC);
589 // If we've already got the block, no need to try to fetch it again.
590 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
594 // Setup the memReq to do a read of the first instruction's address.
595 // Set the appropriate read size and flags as well.
596 // Build request here.
597 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
598 fetch_PC, cpu->thread[tid]->contextId(),
601 memReq[tid] = mem_req;
603 // Translate the instruction request.
604 fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC(),
607 // In the case of faults, the fetch stage may need to stall and wait
608 // for the ITB miss to be handled.
610 // If translation was successful, attempt to read the first
612 if (fault == NoFault) {
614 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
615 memReq[tid]->isUncacheable()) {
616 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
617 "misspeculating path)!",
619 ret_fault = TheISA::genMachineCheckFault();
624 // Build packet here.
625 PacketPtr data_pkt = new Packet(mem_req,
626 MemCmd::ReadReq, Packet::Broadcast);
627 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
629 cacheDataPC[tid] = block_PC;
630 cacheDataValid[tid] = false;
632 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
636 // Now do the timing access to see whether or not the instruction
637 // exists within the cache.
638 if (!icachePort->sendTiming(data_pkt)) {
639 assert(retryPkt == NULL);
640 assert(retryTid == -1);
641 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
642 fetchStatus[tid] = IcacheWaitRetry;
649 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
651 lastIcacheStall[tid] = curTick;
653 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
656 fetchStatus[tid] = IcacheWaitResponse;
666 template <class Impl>
668 DefaultFetch<Impl>::doSquash(const Addr &new_PC,
669 const Addr &new_NPC, const Addr &new_microPC, unsigned tid)
671 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n",
672 tid, new_PC, new_NPC);
675 nextPC[tid] = new_NPC;
676 microPC[tid] = new_microPC;
678 // Clear the icache miss if it's outstanding.
679 if (fetchStatus[tid] == IcacheWaitResponse) {
680 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
685 // Get rid of the retrying packet if it was from this thread.
686 if (retryTid == tid) {
687 assert(cacheBlocked);
689 delete retryPkt->req;
696 fetchStatus[tid] = Squashing;
703 DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
704 const Addr &new_MicroPC,
705 const InstSeqNum &seq_num, unsigned tid)
707 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
709 doSquash(new_PC, new_NPC, new_MicroPC, tid);
711 // Tell the CPU to remove any instructions that are in flight between
713 cpu->removeInstsUntil(seq_num, tid);
718 DefaultFetch<Impl>::checkStall(unsigned tid) const
720 bool ret_val = false;
722 if (cpu->contextSwitch) {
723 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
725 } else if (stalls[tid].decode) {
726 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
728 } else if (stalls[tid].rename) {
729 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
731 } else if (stalls[tid].iew) {
732 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
734 } else if (stalls[tid].commit) {
735 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
743 typename DefaultFetch<Impl>::FetchStatus
744 DefaultFetch<Impl>::updateFetchStatus()
747 std::list<unsigned>::iterator threads = activeThreads->begin();
748 std::list<unsigned>::iterator end = activeThreads->end();
750 while (threads != end) {
751 unsigned tid = *threads++;
753 if (fetchStatus[tid] == Running ||
754 fetchStatus[tid] == Squashing ||
755 fetchStatus[tid] == IcacheAccessComplete) {
757 if (_status == Inactive) {
758 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
760 if (fetchStatus[tid] == IcacheAccessComplete) {
761 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
765 cpu->activateStage(O3CPU::FetchIdx);
772 // Stage is switching from active to inactive, notify CPU of it.
773 if (_status == Active) {
774 DPRINTF(Activity, "Deactivating stage.\n");
776 cpu->deactivateStage(O3CPU::FetchIdx);
782 template <class Impl>
784 DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
785 const Addr &new_MicroPC,
786 const InstSeqNum &seq_num, unsigned tid)
788 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
790 doSquash(new_PC, new_NPC, new_MicroPC, tid);
792 // Tell the CPU to remove any instructions that are not in the ROB.
793 cpu->removeInstsNotInROB(tid);
796 template <class Impl>
798 DefaultFetch<Impl>::tick()
800 std::list<unsigned>::iterator threads = activeThreads->begin();
801 std::list<unsigned>::iterator end = activeThreads->end();
802 bool status_change = false;
804 wroteToTimeBuffer = false;
806 while (threads != end) {
807 unsigned tid = *threads++;
809 // Check the signals for each thread to determine the proper status
811 bool updated_status = checkSignalsAndUpdate(tid);
812 status_change = status_change || updated_status;
815 DPRINTF(Fetch, "Running stage.\n");
817 // Reset the number of the instruction we're fetching.
821 if (fromCommit->commitInfo[0].interruptPending) {
822 interruptPending = true;
825 if (fromCommit->commitInfo[0].clearInterrupt) {
826 interruptPending = false;
830 for (threadFetched = 0; threadFetched < numFetchingThreads;
832 // Fetch each of the actively fetching threads.
833 fetch(status_change);
836 // Record number of instructions fetched this cycle for distribution.
837 fetchNisnDist.sample(numInst);
840 // Change the fetch stage status if there was a status change.
841 _status = updateFetchStatus();
844 // If there was activity this cycle, inform the CPU of it.
845 if (wroteToTimeBuffer || cpu->contextSwitch) {
846 DPRINTF(Activity, "Activity this cycle.\n");
848 cpu->activityThisCycle();
852 template <class Impl>
854 DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
856 // Update the per thread stall statuses.
857 if (fromDecode->decodeBlock[tid]) {
858 stalls[tid].decode = true;
861 if (fromDecode->decodeUnblock[tid]) {
862 assert(stalls[tid].decode);
863 assert(!fromDecode->decodeBlock[tid]);
864 stalls[tid].decode = false;
867 if (fromRename->renameBlock[tid]) {
868 stalls[tid].rename = true;
871 if (fromRename->renameUnblock[tid]) {
872 assert(stalls[tid].rename);
873 assert(!fromRename->renameBlock[tid]);
874 stalls[tid].rename = false;
877 if (fromIEW->iewBlock[tid]) {
878 stalls[tid].iew = true;
881 if (fromIEW->iewUnblock[tid]) {
882 assert(stalls[tid].iew);
883 assert(!fromIEW->iewBlock[tid]);
884 stalls[tid].iew = false;
887 if (fromCommit->commitBlock[tid]) {
888 stalls[tid].commit = true;
891 if (fromCommit->commitUnblock[tid]) {
892 assert(stalls[tid].commit);
893 assert(!fromCommit->commitBlock[tid]);
894 stalls[tid].commit = false;
897 // Check squash signals from commit.
898 if (fromCommit->commitInfo[tid].squash) {
900 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
901 "from commit.\n",tid);
902 // In any case, squash.
903 squash(fromCommit->commitInfo[tid].nextPC,
904 fromCommit->commitInfo[tid].nextNPC,
905 fromCommit->commitInfo[tid].nextMicroPC,
906 fromCommit->commitInfo[tid].doneSeqNum,
909 // Also check if there's a mispredict that happened.
910 if (fromCommit->commitInfo[tid].branchMispredict) {
911 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
912 fromCommit->commitInfo[tid].nextPC,
913 fromCommit->commitInfo[tid].branchTaken,
916 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
921 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
922 // Update the branch predictor if it wasn't a squashed instruction
923 // that was broadcasted.
924 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
927 // Check ROB squash signals from commit.
928 if (fromCommit->commitInfo[tid].robSquashing) {
929 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
931 // Continue to squash.
932 fetchStatus[tid] = Squashing;
937 // Check squash signals from decode.
938 if (fromDecode->decodeInfo[tid].squash) {
939 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
940 "from decode.\n",tid);
942 // Update the branch predictor.
943 if (fromDecode->decodeInfo[tid].branchMispredict) {
944 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
945 fromDecode->decodeInfo[tid].nextPC,
946 fromDecode->decodeInfo[tid].branchTaken,
949 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
953 if (fetchStatus[tid] != Squashing) {
955 DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n",
956 fromDecode->decodeInfo[tid].nextPC,
957 fromDecode->decodeInfo[tid].nextNPC);
958 // Squash unless we're already squashing
959 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
960 fromDecode->decodeInfo[tid].nextNPC,
961 fromDecode->decodeInfo[tid].nextMicroPC,
962 fromDecode->decodeInfo[tid].doneSeqNum,
969 if (checkStall(tid) &&
970 fetchStatus[tid] != IcacheWaitResponse &&
971 fetchStatus[tid] != IcacheWaitRetry) {
972 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
974 fetchStatus[tid] = Blocked;
979 if (fetchStatus[tid] == Blocked ||
980 fetchStatus[tid] == Squashing) {
981 // Switch status to running if fetch isn't being told to block or
982 // squash this cycle.
983 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
986 fetchStatus[tid] = Running;
991 // If we've reached this point, we have not gotten any signals that
992 // cause fetch to change its status. Fetch remains the same as before.
998 DefaultFetch<Impl>::fetch(bool &status_change)
1000 //////////////////////////////////////////
1001 // Start actual fetch
1002 //////////////////////////////////////////
1003 int tid = getFetchingThread(fetchPolicy);
1005 if (tid == -1 || drainPending) {
1006 DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1008 // Breaks looping condition in tick()
1009 threadFetched = numFetchingThreads;
1013 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1016 Addr fetch_PC = PC[tid];
1017 Addr fetch_NPC = nextPC[tid];
1018 Addr fetch_MicroPC = microPC[tid];
1020 // Fault code for memory access.
1021 Fault fault = NoFault;
1023 // If returning from the delay of a cache miss, then update the status
1024 // to running, otherwise do the cache access. Possibly move this up
1025 // to tick() function.
1026 if (fetchStatus[tid] == IcacheAccessComplete) {
1027 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1030 fetchStatus[tid] = Running;
1031 status_change = true;
1032 } else if (fetchStatus[tid] == Running) {
1033 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1034 "instruction, starting at PC %08p.\n",
1037 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1038 if (!fetch_success) {
1040 ++icacheStallCycles;
1042 ++fetchMiscStallCycles;
1047 if (fetchStatus[tid] == Idle) {
1049 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1050 } else if (fetchStatus[tid] == Blocked) {
1051 ++fetchBlockedCycles;
1052 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1053 } else if (fetchStatus[tid] == Squashing) {
1054 ++fetchSquashCycles;
1055 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1056 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1057 ++icacheStallCycles;
1058 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid);
1061 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1062 // fetch should do nothing.
1068 // If we had a stall due to an icache miss, then return.
1069 if (fetchStatus[tid] == IcacheWaitResponse) {
1070 ++icacheStallCycles;
1071 status_change = true;
1075 Addr next_PC = fetch_PC;
1076 Addr next_NPC = fetch_NPC;
1077 Addr next_MicroPC = fetch_MicroPC;
1079 InstSeqNum inst_seq;
1081 ExtMachInst ext_inst;
1082 // @todo: Fix this hack.
1083 unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1085 StaticInstPtr staticInst = NULL;
1086 StaticInstPtr macroop = NULL;
1088 if (fault == NoFault) {
1089 // If the read of the first instruction was successful, then grab the
1090 // instructions from the rest of the cache line and put them into the
1091 // queue heading to decode.
1093 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1096 // Need to keep track of whether or not a predicted branch
1097 // ended this fetch block.
1098 bool predicted_branch = false;
1100 while (offset < cacheBlkSize &&
1101 numInst < fetchWidth &&
1102 !predicted_branch) {
1104 // If we're branching after this instruction, quite fetching
1105 // from the same block then.
1107 (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC);
1108 if (predicted_branch) {
1109 DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n",
1110 fetch_PC, fetch_NPC);
1113 // Make sure this is a valid index.
1114 assert(offset <= cacheBlkSize - instSize);
1117 // Get the instruction from the array of the cache line.
1118 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1119 (&cacheData[tid][offset]));
1121 predecoder.setTC(cpu->thread[tid]->getTC());
1122 predecoder.moreBytes(fetch_PC, fetch_PC, inst);
1124 ext_inst = predecoder.getExtMachInst();
1125 staticInst = StaticInstPtr(ext_inst, fetch_PC);
1126 if (staticInst->isMacroop())
1127 macroop = staticInst;
1131 staticInst = macroop->fetchMicroop(fetch_MicroPC);
1132 if (staticInst->isLastMicroop())
1136 // Get a sequence number.
1137 inst_seq = cpu->getAndIncrementInstSeq();
1139 // Create a new DynInst from the instruction fetched.
1140 DynInstPtr instruction = new DynInst(staticInst,
1141 fetch_PC, fetch_NPC, fetch_MicroPC,
1142 next_PC, next_NPC, next_MicroPC,
1144 instruction->setTid(tid);
1146 instruction->setASID(tid);
1148 instruction->setThreadState(cpu->thread[tid]);
1150 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1152 tid, instruction->readPC(), inst_seq);
1154 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
1156 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1157 tid, instruction->staticInst->disassemble(fetch_PC));
1160 instruction->traceData =
1161 cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid),
1162 instruction->staticInst, instruction->readPC());
1164 instruction->traceData = NULL;
1167 ///FIXME This needs to be more robust in dealing with delay slots
1169 lookupAndUpdateNextPC(instruction, next_PC, next_NPC, next_MicroPC);
1171 // Add instruction to the CPU's list of instructions.
1172 instruction->setInstListIt(cpu->addInst(instruction));
1174 // Write the instruction to the first slot in the queue
1175 // that heads to decode.
1176 toDecode->insts[numInst] = instruction;
1180 // Increment stat of fetched instructions.
1183 // Move to the next instruction, unless we have a branch.
1185 fetch_NPC = next_NPC;
1186 fetch_MicroPC = next_MicroPC;
1188 if (instruction->isQuiesce()) {
1189 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1191 fetchStatus[tid] = QuiescePending;
1193 status_change = true;
1198 } while (staticInst->isMicroop() &&
1199 !staticInst->isLastMicroop() &&
1200 numInst < fetchWidth);
1204 if (predicted_branch) {
1205 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1206 "instruction encountered.\n", tid);
1207 } else if (numInst >= fetchWidth) {
1208 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1209 "for this cycle.\n", tid);
1210 } else if (offset >= cacheBlkSize) {
1211 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1217 wroteToTimeBuffer = true;
1220 // Now that fetching is completed, update the PC to signify what the next
1222 if (fault == NoFault) {
1224 nextPC[tid] = next_NPC;
1225 microPC[tid] = next_MicroPC;
1226 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC);
1228 // We shouldn't be in an icache miss and also have a fault (an ITB
1230 if (fetchStatus[tid] == IcacheWaitResponse) {
1231 panic("Fetch should have exited prior to this!");
1234 // Send the fault to commit. This thread will not do anything
1235 // until commit handles the fault. The only other way it can
1236 // wake up is if a squash comes along and changes the PC.
1237 assert(numInst < fetchWidth);
1238 // Get a sequence number.
1239 inst_seq = cpu->getAndIncrementInstSeq();
1240 // We will use a nop in order to carry the fault.
1241 ext_inst = TheISA::NoopMachInst;
1243 // Create a new DynInst from the dummy nop.
1244 DynInstPtr instruction = new DynInst(ext_inst,
1245 fetch_PC, fetch_NPC, fetch_MicroPC,
1246 next_PC, next_NPC, next_MicroPC,
1248 instruction->setPredTarg(next_NPC, next_NPC + instSize, 0);
1249 instruction->setTid(tid);
1251 instruction->setASID(tid);
1253 instruction->setThreadState(cpu->thread[tid]);
1255 instruction->traceData = NULL;
1257 instruction->setInstListIt(cpu->addInst(instruction));
1259 instruction->fault = fault;
1261 toDecode->insts[numInst] = instruction;
1264 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1266 fetchStatus[tid] = TrapPending;
1267 status_change = true;
1269 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
1270 tid, fault->name(), PC[tid]);
1274 template<class Impl>
1276 DefaultFetch<Impl>::recvRetry()
1278 if (retryPkt != NULL) {
1279 assert(cacheBlocked);
1280 assert(retryTid != -1);
1281 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1283 if (icachePort->sendTiming(retryPkt)) {
1284 fetchStatus[retryTid] = IcacheWaitResponse;
1287 cacheBlocked = false;
1290 assert(retryTid == -1);
1291 // Access has been squashed since it was sent out. Just clear
1292 // the cache being blocked.
1293 cacheBlocked = false;
1297 ///////////////////////////////////////
1299 // SMT FETCH POLICY MAINTAINED HERE //
1301 ///////////////////////////////////////
1302 template<class Impl>
1304 DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1306 if (numThreads > 1) {
1307 switch (fetch_priority) {
1313 return roundRobin();
1322 return branchCount();
1328 std::list<unsigned>::iterator thread = activeThreads->begin();
1329 if (thread == activeThreads->end()) {
1335 if (fetchStatus[tid] == Running ||
1336 fetchStatus[tid] == IcacheAccessComplete ||
1337 fetchStatus[tid] == Idle) {
1347 template<class Impl>
1349 DefaultFetch<Impl>::roundRobin()
1351 std::list<unsigned>::iterator pri_iter = priorityList.begin();
1352 std::list<unsigned>::iterator end = priorityList.end();
1356 while (pri_iter != end) {
1357 high_pri = *pri_iter;
1359 assert(high_pri <= numThreads);
1361 if (fetchStatus[high_pri] == Running ||
1362 fetchStatus[high_pri] == IcacheAccessComplete ||
1363 fetchStatus[high_pri] == Idle) {
1365 priorityList.erase(pri_iter);
1366 priorityList.push_back(high_pri);
1377 template<class Impl>
1379 DefaultFetch<Impl>::iqCount()
1381 std::priority_queue<unsigned> PQ;
1383 std::list<unsigned>::iterator threads = activeThreads->begin();
1384 std::list<unsigned>::iterator end = activeThreads->end();
1386 while (threads != end) {
1387 unsigned tid = *threads++;
1389 PQ.push(fromIEW->iewInfo[tid].iqCount);
1392 while (!PQ.empty()) {
1394 unsigned high_pri = PQ.top();
1396 if (fetchStatus[high_pri] == Running ||
1397 fetchStatus[high_pri] == IcacheAccessComplete ||
1398 fetchStatus[high_pri] == Idle)
1408 template<class Impl>
1410 DefaultFetch<Impl>::lsqCount()
1412 std::priority_queue<unsigned> PQ;
1414 std::list<unsigned>::iterator threads = activeThreads->begin();
1415 std::list<unsigned>::iterator end = activeThreads->end();
1417 while (threads != end) {
1418 unsigned tid = *threads++;
1420 PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1423 while (!PQ.empty()) {
1425 unsigned high_pri = PQ.top();
1427 if (fetchStatus[high_pri] == Running ||
1428 fetchStatus[high_pri] == IcacheAccessComplete ||
1429 fetchStatus[high_pri] == Idle)
1439 template<class Impl>
1441 DefaultFetch<Impl>::branchCount()
1443 std::list<unsigned>::iterator thread = activeThreads->begin();
1444 assert(thread != activeThreads->end());
1445 unsigned tid = *thread;
1447 panic("Branch Count Fetch policy unimplemented\n");