src/cpu/o3/fetch_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Korey Sewell
  30  */
  31
  32 #include <algorithm>
  33 #include <cstring>
  34
  35 #include "config/use_checker.hh"
  36
  37 #include "arch/isa_traits.hh"
  38 #include "arch/utility.hh"
  39 #include "cpu/checker/cpu.hh"
  40 #include "cpu/exetrace.hh"
  41 #include "cpu/o3/fetch.hh"
  42 #include "mem/packet.hh"
  43 #include "mem/request.hh"
  44 #include "sim/byteswap.hh"
  45 #include "sim/host.hh"
  46 #include "sim/core.hh"
  47
  48 #if FULL_SYSTEM
  49 #include "arch/tlb.hh"
  50 #include "arch/vtophys.hh"
  51 #include "sim/system.hh"
  52 #endif // FULL_SYSTEM
  53
  54 template<class Impl>
  55 void
  56 DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
  57 {
  58     Port::setPeer(port);
  59
  60     fetch->setIcache();
  61 }
  62
  63 template<class Impl>
  64 Tick
  65 DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
  66 {
  67     panic("DefaultFetch doesn't expect recvAtomic callback!");
  68     return curTick;
  69 }
  70
  71 template<class Impl>
  72 void
  73 DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
  74 {
  75     DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
  76             "functional call.");
  77 }
  78
  79 template<class Impl>
  80 void
  81 DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
  82 {
  83     if (status == RangeChange) {
  84         if (!snoopRangeSent) {
  85             snoopRangeSent = true;
  86             sendStatusChange(Port::RangeChange);
  87         }
  88         return;
  89     }
  90
  91     panic("DefaultFetch doesn't expect recvStatusChange callback!");
  92 }
  93
  94 template<class Impl>
  95 bool
  96 DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
  97 {
  98     DPRINTF(Fetch, "Received timing\n");
  99     if (pkt->isResponse()) {
 100         fetch->processCacheCompletion(pkt);
 101     }
 102     //else Snooped a coherence request, just return
 103     return true;
 104 }
 105
 106 template<class Impl>
 107 void
 108 DefaultFetch<Impl>::IcachePort::recvRetry()
 109 {
 110     fetch->recvRetry();
 111 }
 112
 113 template<class Impl>
 114 DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, Params *params)
 115     : cpu(_cpu),
 116       branchPred(params),
 117       predecoder(NULL),
 118       decodeToFetchDelay(params->decodeToFetchDelay),
 119       renameToFetchDelay(params->renameToFetchDelay),
 120       iewToFetchDelay(params->iewToFetchDelay),
 121       commitToFetchDelay(params->commitToFetchDelay),
 122       fetchWidth(params->fetchWidth),
 123       cacheBlocked(false),
 124       retryPkt(NULL),
 125       retryTid(-1),
 126       numThreads(params->numberOfThreads),
 127       numFetchingThreads(params->smtNumFetchingThreads),
 128       interruptPending(false),
 129       drainPending(false),
 130       switchedOut(false)
 131 {
 132     if (numThreads > Impl::MaxThreads)
 133         fatal("numThreads is not a valid value\n");
 134
 135     // Set fetch stage's status to inactive.
 136     _status = Inactive;
 137
 138     std::string policy = params->smtFetchPolicy;
 139
 140     // Convert string to lowercase
 141     std::transform(policy.begin(), policy.end(), policy.begin(),
 142                    (int(*)(int)) tolower);
 143
 144     // Figure out fetch policy
 145     if (policy == "singlethread") {
 146         fetchPolicy = SingleThread;
 147         if (numThreads > 1)
 148             panic("Invalid Fetch Policy for a SMT workload.");
 149     } else if (policy == "roundrobin") {
 150         fetchPolicy = RoundRobin;
 151         DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
 152     } else if (policy == "branch") {
 153         fetchPolicy = Branch;
 154         DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
 155     } else if (policy == "iqcount") {
 156         fetchPolicy = IQ;
 157         DPRINTF(Fetch, "Fetch policy set to IQ count\n");
 158     } else if (policy == "lsqcount") {
 159         fetchPolicy = LSQ;
 160         DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
 161     } else {
 162         fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
 163               " RoundRobin,LSQcount,IQcount}\n");
 164     }
 165
 166     // Get the size of an instruction.
 167     instSize = sizeof(TheISA::MachInst);
 168
 169     // Name is finally available, so create the port.
 170     icachePort = new IcachePort(this);
 171
 172     icachePort->snoopRangeSent = false;
 173
 174 #if USE_CHECKER
 175     if (cpu->checker) {
 176         cpu->checker->setIcachePort(icachePort);
 177     }
 178 #endif
 179 }
 180
 181 template <class Impl>
 182 std::string
 183 DefaultFetch<Impl>::name() const
 184 {
 185     return cpu->name() + ".fetch";
 186 }
 187
 188 template <class Impl>
 189 void
 190 DefaultFetch<Impl>::regStats()
 191 {
 192     icacheStallCycles
 193         .name(name() + ".icacheStallCycles")
 194         .desc("Number of cycles fetch is stalled on an Icache miss")
 195         .prereq(icacheStallCycles);
 196
 197     fetchedInsts
 198         .name(name() + ".Insts")
 199         .desc("Number of instructions fetch has processed")
 200         .prereq(fetchedInsts);
 201
 202     fetchedBranches
 203         .name(name() + ".Branches")
 204         .desc("Number of branches that fetch encountered")
 205         .prereq(fetchedBranches);
 206
 207     predictedBranches
 208         .name(name() + ".predictedBranches")
 209         .desc("Number of branches that fetch has predicted taken")
 210         .prereq(predictedBranches);
 211
 212     fetchCycles
 213         .name(name() + ".Cycles")
 214         .desc("Number of cycles fetch has run and was not squashing or"
 215               " blocked")
 216         .prereq(fetchCycles);
 217
 218     fetchSquashCycles
 219         .name(name() + ".SquashCycles")
 220         .desc("Number of cycles fetch has spent squashing")
 221         .prereq(fetchSquashCycles);
 222
 223     fetchIdleCycles
 224         .name(name() + ".IdleCycles")
 225         .desc("Number of cycles fetch was idle")
 226         .prereq(fetchIdleCycles);
 227
 228     fetchBlockedCycles
 229         .name(name() + ".BlockedCycles")
 230         .desc("Number of cycles fetch has spent blocked")
 231         .prereq(fetchBlockedCycles);
 232
 233     fetchedCacheLines
 234         .name(name() + ".CacheLines")
 235         .desc("Number of cache lines fetched")
 236         .prereq(fetchedCacheLines);
 237
 238     fetchMiscStallCycles
 239         .name(name() + ".MiscStallCycles")
 240         .desc("Number of cycles fetch has spent waiting on interrupts, or "
 241               "bad addresses, or out of MSHRs")
 242         .prereq(fetchMiscStallCycles);
 243
 244     fetchIcacheSquashes
 245         .name(name() + ".IcacheSquashes")
 246         .desc("Number of outstanding Icache misses that were squashed")
 247         .prereq(fetchIcacheSquashes);
 248
 249     fetchNisnDist
 250         .init(/* base value */ 0,
 251               /* last value */ fetchWidth,
 252               /* bucket size */ 1)
 253         .name(name() + ".rateDist")
 254         .desc("Number of instructions fetched each cycle (Total)")
 255         .flags(Stats::pdf);
 256
 257     idleRate
 258         .name(name() + ".idleRate")
 259         .desc("Percent of cycles fetch was idle")
 260         .prereq(idleRate);
 261     idleRate = fetchIdleCycles * 100 / cpu->numCycles;
 262
 263     branchRate
 264         .name(name() + ".branchRate")
 265         .desc("Number of branch fetches per cycle")
 266         .flags(Stats::total);
 267     branchRate = fetchedBranches / cpu->numCycles;
 268
 269     fetchRate
 270         .name(name() + ".rate")
 271         .desc("Number of inst fetches per cycle")
 272         .flags(Stats::total);
 273     fetchRate = fetchedInsts / cpu->numCycles;
 274
 275     branchPred.regStats();
 276 }
 277
 278 template<class Impl>
 279 void
 280 DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
 281 {
 282     timeBuffer = time_buffer;
 283
 284     // Create wires to get information from proper places in time buffer.
 285     fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
 286     fromRename = timeBuffer->getWire(-renameToFetchDelay);
 287     fromIEW = timeBuffer->getWire(-iewToFetchDelay);
 288     fromCommit = timeBuffer->getWire(-commitToFetchDelay);
 289 }
 290
 291 template<class Impl>
 292 void
 293 DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
 294 {
 295     activeThreads = at_ptr;
 296 }
 297
 298 template<class Impl>
 299 void
 300 DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
 301 {
 302     fetchQueue = fq_ptr;
 303
 304     // Create wire to write information to proper place in fetch queue.
 305     toDecode = fetchQueue->getWire(0);
 306 }
 307
 308 template<class Impl>
 309 void
 310 DefaultFetch<Impl>::initStage()
 311 {
 312     // Setup PC and nextPC with initial state.
 313     for (int tid = 0; tid < numThreads; tid++) {
 314         PC[tid] = cpu->readPC(tid);
 315         nextPC[tid] = cpu->readNextPC(tid);
 316         microPC[tid] = cpu->readMicroPC(tid);
 317     }
 318
 319     for (int tid=0; tid < numThreads; tid++) {
 320
 321         fetchStatus[tid] = Running;
 322
 323         priorityList.push_back(tid);
 324
 325         memReq[tid] = NULL;
 326
 327         stalls[tid].decode = false;
 328         stalls[tid].rename = false;
 329         stalls[tid].iew = false;
 330         stalls[tid].commit = false;
 331     }
 332
 333     // Schedule fetch to get the correct PC from the CPU
 334     // scheduleFetchStartupEvent(1);
 335
 336     // Fetch needs to start fetching instructions at the very beginning,
 337     // so it must start up in active state.
 338     switchToActive();
 339 }
 340
 341 template<class Impl>
 342 void
 343 DefaultFetch<Impl>::setIcache()
 344 {
 345     // Size of cache block.
 346     cacheBlkSize = icachePort->peerBlockSize();
 347
 348     // Create mask to get rid of offset bits.
 349     cacheBlkMask = (cacheBlkSize - 1);
 350
 351     for (int tid=0; tid < numThreads; tid++) {
 352         // Create space to store a cache line.
 353         cacheData[tid] = new uint8_t[cacheBlkSize];
 354         cacheDataPC[tid] = 0;
 355         cacheDataValid[tid] = false;
 356     }
 357 }
 358
 359 template<class Impl>
 360 void
 361 DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
 362 {
 363     unsigned tid = pkt->req->getThreadNum();
 364
 365     DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
 366
 367     // Only change the status if it's still waiting on the icache access
 368     // to return.
 369     if (fetchStatus[tid] != IcacheWaitResponse ||
 370         pkt->req != memReq[tid] ||
 371         isSwitchedOut()) {
 372         ++fetchIcacheSquashes;
 373         delete pkt->req;
 374         delete pkt;
 375         return;
 376     }
 377
 378     memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
 379     cacheDataValid[tid] = true;
 380
 381     if (!drainPending) {
 382         // Wake up the CPU (if it went to sleep and was waiting on
 383         // this completion event).
 384         cpu->wakeCPU();
 385
 386         DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
 387                 tid);
 388
 389         switchToActive();
 390     }
 391
 392     // Only switch to IcacheAccessComplete if we're not stalled as well.
 393     if (checkStall(tid)) {
 394         fetchStatus[tid] = Blocked;
 395     } else {
 396         fetchStatus[tid] = IcacheAccessComplete;
 397     }
 398
 399     // Reset the mem req to NULL.
 400     delete pkt->req;
 401     delete pkt;
 402     memReq[tid] = NULL;
 403 }
 404
 405 template <class Impl>
 406 bool
 407 DefaultFetch<Impl>::drain()
 408 {
 409     // Fetch is ready to drain at any time.
 410     cpu->signalDrained();
 411     drainPending = true;
 412     return true;
 413 }
 414
 415 template <class Impl>
 416 void
 417 DefaultFetch<Impl>::resume()
 418 {
 419     drainPending = false;
 420 }
 421
 422 template <class Impl>
 423 void
 424 DefaultFetch<Impl>::switchOut()
 425 {
 426     switchedOut = true;
 427     // Branch predictor needs to have its state cleared.
 428     branchPred.switchOut();
 429 }
 430
 431 template <class Impl>
 432 void
 433 DefaultFetch<Impl>::takeOverFrom()
 434 {
 435     // Reset all state
 436     for (int i = 0; i < Impl::MaxThreads; ++i) {
 437         stalls[i].decode = 0;
 438         stalls[i].rename = 0;
 439         stalls[i].iew = 0;
 440         stalls[i].commit = 0;
 441         PC[i] = cpu->readPC(i);
 442         nextPC[i] = cpu->readNextPC(i);
 443         microPC[i] = cpu->readMicroPC(i);
 444         fetchStatus[i] = Running;
 445     }
 446     numInst = 0;
 447     wroteToTimeBuffer = false;
 448     _status = Inactive;
 449     switchedOut = false;
 450     interruptPending = false;
 451     branchPred.takeOverFrom();
 452 }
 453
 454 template <class Impl>
 455 void
 456 DefaultFetch<Impl>::wakeFromQuiesce()
 457 {
 458     DPRINTF(Fetch, "Waking up from quiesce\n");
 459     // Hopefully this is safe
 460     // @todo: Allow other threads to wake from quiesce.
 461     fetchStatus[0] = Running;
 462 }
 463
 464 template <class Impl>
 465 inline void
 466 DefaultFetch<Impl>::switchToActive()
 467 {
 468     if (_status == Inactive) {
 469         DPRINTF(Activity, "Activating stage.\n");
 470
 471         cpu->activateStage(O3CPU::FetchIdx);
 472
 473         _status = Active;
 474     }
 475 }
 476
 477 template <class Impl>
 478 inline void
 479 DefaultFetch<Impl>::switchToInactive()
 480 {
 481     if (_status == Active) {
 482         DPRINTF(Activity, "Deactivating stage.\n");
 483
 484         cpu->deactivateStage(O3CPU::FetchIdx);
 485
 486         _status = Inactive;
 487     }
 488 }
 489
 490 template <class Impl>
 491 bool
 492 DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
 493                                           Addr &next_NPC, Addr &next_MicroPC)
 494 {
 495     // Do branch prediction check here.
 496     // A bit of a misnomer...next_PC is actually the current PC until
 497     // this function updates it.
 498     bool predict_taken;
 499
 500     if (!inst->isControl()) {
 501         if (inst->isMicroop() && !inst->isLastMicroop()) {
 502             next_MicroPC++;
 503         } else {
 504             next_PC  = next_NPC;
 505             next_NPC = next_NPC + instSize;
 506             next_MicroPC = 0;
 507         }
 508         inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
 509         inst->setPredTaken(false);
 510         return false;
 511     }
 512
 513     //Assume for now that all control flow is to a different macroop which
 514     //would reset the micro pc to 0.
 515     next_MicroPC = 0;
 516
 517     int tid = inst->threadNumber;
 518     Addr pred_PC = next_PC;
 519     predict_taken = branchPred.predict(inst, pred_PC, tid);
 520
 521 /*    if (predict_taken) {
 522         DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken to %#x.\n",
 523                 tid, pred_PC);
 524     } else {
 525         DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid);
 526     }*/
 527
 528 #if ISA_HAS_DELAY_SLOT
 529     next_PC = next_NPC;
 530     if (predict_taken)
 531         next_NPC = pred_PC;
 532     else
 533         next_NPC += instSize;
 534 #else
 535     if (predict_taken)
 536         next_PC = pred_PC;
 537     else
 538         next_PC += instSize;
 539     next_NPC = next_PC + instSize;
 540 #endif
 541 /*    DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n",
 542             tid, next_PC, next_NPC);*/
 543     inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
 544     inst->setPredTaken(predict_taken);
 545
 546     ++fetchedBranches;
 547
 548     if (predict_taken) {
 549         ++predictedBranches;
 550     }
 551
 552     return predict_taken;
 553 }
 554
 555 template <class Impl>
 556 bool
 557 DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
 558 {
 559     Fault fault = NoFault;
 560
 561     //AlphaDep
 562     if (cacheBlocked) {
 563         DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
 564                 tid);
 565         return false;
 566     } else if (isSwitchedOut()) {
 567         DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
 568                 tid);
 569         return false;
 570     } else if (interruptPending && !(fetch_PC & 0x3)) {
 571         // Hold off fetch from getting new instructions when:
 572         // Cache is blocked, or
 573         // while an interrupt is pending and we're not in PAL mode, or
 574         // fetch is switched out.
 575         DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
 576                 tid);
 577         return false;
 578     }
 579
 580     // Align the fetch PC so it's at the start of a cache block.
 581     Addr block_PC = icacheBlockAlignPC(fetch_PC);
 582
 583     // If we've already got the block, no need to try to fetch it again.
 584     if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
 585         return true;
 586     }
 587
 588     // Setup the memReq to do a read of the first instruction's address.
 589     // Set the appropriate read size and flags as well.
 590     // Build request here.
 591     RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
 592                                      fetch_PC, cpu->readCpuId(), tid);
 593
 594     memReq[tid] = mem_req;
 595
 596     // Translate the instruction request.
 597     fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
 598
 599     // In the case of faults, the fetch stage may need to stall and wait
 600     // for the ITB miss to be handled.
 601
 602     // If translation was successful, attempt to read the first
 603     // instruction.
 604     if (fault == NoFault) {
 605 #if 0
 606         if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
 607             memReq[tid]->isUncacheable()) {
 608             DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
 609                     "misspeculating path)!",
 610                     memReq[tid]->paddr);
 611             ret_fault = TheISA::genMachineCheckFault();
 612             return false;
 613         }
 614 #endif
 615
 616         // Build packet here.
 617         PacketPtr data_pkt = new Packet(mem_req,
 618                                         MemCmd::ReadReq, Packet::Broadcast);
 619         data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
 620
 621         cacheDataPC[tid] = block_PC;
 622         cacheDataValid[tid] = false;
 623
 624         DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
 625
 626         fetchedCacheLines++;
 627
 628         // Now do the timing access to see whether or not the instruction
 629         // exists within the cache.
 630         if (!icachePort->sendTiming(data_pkt)) {
 631             if (data_pkt->result == Packet::BadAddress) {
 632                 fault = TheISA::genMachineCheckFault();
 633                 delete mem_req;
 634                 memReq[tid] = NULL;
 635                 warn("Bad address!\n");
 636             }
 637             assert(retryPkt == NULL);
 638             assert(retryTid == -1);
 639             DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
 640             fetchStatus[tid] = IcacheWaitRetry;
 641             retryPkt = data_pkt;
 642             retryTid = tid;
 643             cacheBlocked = true;
 644             return false;
 645         }
 646
 647         DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
 648
 649         lastIcacheStall[tid] = curTick;
 650
 651         DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
 652                 "response.\n", tid);
 653
 654         fetchStatus[tid] = IcacheWaitResponse;
 655     } else {
 656         delete mem_req;
 657         memReq[tid] = NULL;
 658     }
 659
 660     ret_fault = fault;
 661     return true;
 662 }
 663
 664 template <class Impl>
 665 inline void
 666 DefaultFetch<Impl>::doSquash(const Addr &new_PC,
 667         const Addr &new_NPC, const Addr &new_microPC, unsigned tid)
 668 {
 669     DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n",
 670             tid, new_PC, new_NPC);
 671
 672     PC[tid] = new_PC;
 673     nextPC[tid] = new_NPC;
 674     microPC[tid] = new_microPC;
 675
 676     // Clear the icache miss if it's outstanding.
 677     if (fetchStatus[tid] == IcacheWaitResponse) {
 678         DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
 679                 tid);
 680         memReq[tid] = NULL;
 681     }
 682
 683     // Get rid of the retrying packet if it was from this thread.
 684     if (retryTid == tid) {
 685         assert(cacheBlocked);
 686         if (retryPkt) {
 687             delete retryPkt->req;
 688             delete retryPkt;
 689         }
 690         retryPkt = NULL;
 691         retryTid = -1;
 692     }
 693
 694     fetchStatus[tid] = Squashing;
 695
 696     ++fetchSquashCycles;
 697 }
 698
 699 template<class Impl>
 700 void
 701 DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
 702                                      const Addr &new_MicroPC,
 703                                      const InstSeqNum &seq_num, unsigned tid)
 704 {
 705     DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
 706
 707     doSquash(new_PC, new_NPC, new_MicroPC, tid);
 708
 709     // Tell the CPU to remove any instructions that are in flight between
 710     // fetch and decode.
 711     cpu->removeInstsUntil(seq_num, tid);
 712 }
 713
 714 template<class Impl>
 715 bool
 716 DefaultFetch<Impl>::checkStall(unsigned tid) const
 717 {
 718     bool ret_val = false;
 719
 720     if (cpu->contextSwitch) {
 721         DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
 722         ret_val = true;
 723     } else if (stalls[tid].decode) {
 724         DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
 725         ret_val = true;
 726     } else if (stalls[tid].rename) {
 727         DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
 728         ret_val = true;
 729     } else if (stalls[tid].iew) {
 730         DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
 731         ret_val = true;
 732     } else if (stalls[tid].commit) {
 733         DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
 734         ret_val = true;
 735     }
 736
 737     return ret_val;
 738 }
 739
 740 template<class Impl>
 741 typename DefaultFetch<Impl>::FetchStatus
 742 DefaultFetch<Impl>::updateFetchStatus()
 743 {
 744     //Check Running
 745     std::list<unsigned>::iterator threads = activeThreads->begin();
 746     std::list<unsigned>::iterator end = activeThreads->end();
 747
 748     while (threads != end) {
 749         unsigned tid = *threads++;
 750
 751         if (fetchStatus[tid] == Running ||
 752             fetchStatus[tid] == Squashing ||
 753             fetchStatus[tid] == IcacheAccessComplete) {
 754
 755             if (_status == Inactive) {
 756                 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
 757
 758                 if (fetchStatus[tid] == IcacheAccessComplete) {
 759                     DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
 760                             "completion\n",tid);
 761                 }
 762
 763                 cpu->activateStage(O3CPU::FetchIdx);
 764             }
 765
 766             return Active;
 767         }
 768     }
 769
 770     // Stage is switching from active to inactive, notify CPU of it.
 771     if (_status == Active) {
 772         DPRINTF(Activity, "Deactivating stage.\n");
 773
 774         cpu->deactivateStage(O3CPU::FetchIdx);
 775     }
 776
 777     return Inactive;
 778 }
 779
 780 template <class Impl>
 781 void
 782 DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
 783                            const Addr &new_MicroPC,
 784                            const InstSeqNum &seq_num, unsigned tid)
 785 {
 786     DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
 787
 788     doSquash(new_PC, new_NPC, new_MicroPC, tid);
 789
 790     // Tell the CPU to remove any instructions that are not in the ROB.
 791     cpu->removeInstsNotInROB(tid);
 792 }
 793
 794 template <class Impl>
 795 void
 796 DefaultFetch<Impl>::tick()
 797 {
 798     std::list<unsigned>::iterator threads = activeThreads->begin();
 799     std::list<unsigned>::iterator end = activeThreads->end();
 800     bool status_change = false;
 801
 802     wroteToTimeBuffer = false;
 803
 804     while (threads != end) {
 805         unsigned tid = *threads++;
 806
 807         // Check the signals for each thread to determine the proper status
 808         // for each thread.
 809         bool updated_status = checkSignalsAndUpdate(tid);
 810         status_change =  status_change || updated_status;
 811     }
 812
 813     DPRINTF(Fetch, "Running stage.\n");
 814
 815     // Reset the number of the instruction we're fetching.
 816     numInst = 0;
 817
 818 #if FULL_SYSTEM
 819     if (fromCommit->commitInfo[0].interruptPending) {
 820         interruptPending = true;
 821     }
 822
 823     if (fromCommit->commitInfo[0].clearInterrupt) {
 824         interruptPending = false;
 825     }
 826 #endif
 827
 828     for (threadFetched = 0; threadFetched < numFetchingThreads;
 829          threadFetched++) {
 830         // Fetch each of the actively fetching threads.
 831         fetch(status_change);
 832     }
 833
 834     // Record number of instructions fetched this cycle for distribution.
 835     fetchNisnDist.sample(numInst);
 836
 837     if (status_change) {
 838         // Change the fetch stage status if there was a status change.
 839         _status = updateFetchStatus();
 840     }
 841
 842     // If there was activity this cycle, inform the CPU of it.
 843     if (wroteToTimeBuffer || cpu->contextSwitch) {
 844         DPRINTF(Activity, "Activity this cycle.\n");
 845
 846         cpu->activityThisCycle();
 847     }
 848 }
 849
 850 template <class Impl>
 851 bool
 852 DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
 853 {
 854     // Update the per thread stall statuses.
 855     if (fromDecode->decodeBlock[tid]) {
 856         stalls[tid].decode = true;
 857     }
 858
 859     if (fromDecode->decodeUnblock[tid]) {
 860         assert(stalls[tid].decode);
 861         assert(!fromDecode->decodeBlock[tid]);
 862         stalls[tid].decode = false;
 863     }
 864
 865     if (fromRename->renameBlock[tid]) {
 866         stalls[tid].rename = true;
 867     }
 868
 869     if (fromRename->renameUnblock[tid]) {
 870         assert(stalls[tid].rename);
 871         assert(!fromRename->renameBlock[tid]);
 872         stalls[tid].rename = false;
 873     }
 874
 875     if (fromIEW->iewBlock[tid]) {
 876         stalls[tid].iew = true;
 877     }
 878
 879     if (fromIEW->iewUnblock[tid]) {
 880         assert(stalls[tid].iew);
 881         assert(!fromIEW->iewBlock[tid]);
 882         stalls[tid].iew = false;
 883     }
 884
 885     if (fromCommit->commitBlock[tid]) {
 886         stalls[tid].commit = true;
 887     }
 888
 889     if (fromCommit->commitUnblock[tid]) {
 890         assert(stalls[tid].commit);
 891         assert(!fromCommit->commitBlock[tid]);
 892         stalls[tid].commit = false;
 893     }
 894
 895     // Check squash signals from commit.
 896     if (fromCommit->commitInfo[tid].squash) {
 897
 898         DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
 899                 "from commit.\n",tid);
 900         // In any case, squash.
 901         squash(fromCommit->commitInfo[tid].nextPC,
 902                fromCommit->commitInfo[tid].nextNPC,
 903                fromCommit->commitInfo[tid].nextMicroPC,
 904                fromCommit->commitInfo[tid].doneSeqNum,
 905                tid);
 906
 907         // Also check if there's a mispredict that happened.
 908         if (fromCommit->commitInfo[tid].branchMispredict) {
 909             branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
 910                               fromCommit->commitInfo[tid].nextPC,
 911                               fromCommit->commitInfo[tid].branchTaken,
 912                               tid);
 913         } else {
 914             branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
 915                               tid);
 916         }
 917
 918         return true;
 919     } else if (fromCommit->commitInfo[tid].doneSeqNum) {
 920         // Update the branch predictor if it wasn't a squashed instruction
 921         // that was broadcasted.
 922         branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
 923     }
 924
 925     // Check ROB squash signals from commit.
 926     if (fromCommit->commitInfo[tid].robSquashing) {
 927         DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
 928
 929         // Continue to squash.
 930         fetchStatus[tid] = Squashing;
 931
 932         return true;
 933     }
 934
 935     // Check squash signals from decode.
 936     if (fromDecode->decodeInfo[tid].squash) {
 937         DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
 938                 "from decode.\n",tid);
 939
 940         // Update the branch predictor.
 941         if (fromDecode->decodeInfo[tid].branchMispredict) {
 942             branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
 943                               fromDecode->decodeInfo[tid].nextPC,
 944                               fromDecode->decodeInfo[tid].branchTaken,
 945                               tid);
 946         } else {
 947             branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
 948                               tid);
 949         }
 950
 951         if (fetchStatus[tid] != Squashing) {
 952
 953             DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n",
 954                     fromDecode->decodeInfo[tid].nextPC,
 955                     fromDecode->decodeInfo[tid].nextNPC);
 956             // Squash unless we're already squashing
 957             squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
 958                              fromDecode->decodeInfo[tid].nextNPC,
 959                              fromDecode->decodeInfo[tid].nextMicroPC,
 960                              fromDecode->decodeInfo[tid].doneSeqNum,
 961                              tid);
 962
 963             return true;
 964         }
 965     }
 966
 967     if (checkStall(tid) &&
 968         fetchStatus[tid] != IcacheWaitResponse &&
 969         fetchStatus[tid] != IcacheWaitRetry) {
 970         DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
 971
 972         fetchStatus[tid] = Blocked;
 973
 974         return true;
 975     }
 976
 977     if (fetchStatus[tid] == Blocked ||
 978         fetchStatus[tid] == Squashing) {
 979         // Switch status to running if fetch isn't being told to block or
 980         // squash this cycle.
 981         DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
 982                 tid);
 983
 984         fetchStatus[tid] = Running;
 985
 986         return true;
 987     }
 988
 989     // If we've reached this point, we have not gotten any signals that
 990     // cause fetch to change its status.  Fetch remains the same as before.
 991     return false;
 992 }
 993
 994 template<class Impl>
 995 void
 996 DefaultFetch<Impl>::fetch(bool &status_change)
 997 {
 998     //////////////////////////////////////////
 999     // Start actual fetch
1000     //////////////////////////////////////////
1001     int tid = getFetchingThread(fetchPolicy);
1002
1003     if (tid == -1 || drainPending) {
1004         DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1005
1006         // Breaks looping condition in tick()
1007         threadFetched = numFetchingThreads;
1008         return;
1009     }
1010
1011     DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1012
1013     // The current PC.
1014     Addr fetch_PC = PC[tid];
1015     Addr fetch_NPC = nextPC[tid];
1016     Addr fetch_MicroPC = microPC[tid];
1017
1018     // Fault code for memory access.
1019     Fault fault = NoFault;
1020
1021     // If returning from the delay of a cache miss, then update the status
1022     // to running, otherwise do the cache access.  Possibly move this up
1023     // to tick() function.
1024     if (fetchStatus[tid] == IcacheAccessComplete) {
1025         DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1026                 tid);
1027
1028         fetchStatus[tid] = Running;
1029         status_change = true;
1030     } else if (fetchStatus[tid] == Running) {
1031         DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1032                 "instruction, starting at PC %08p.\n",
1033                 tid, fetch_PC);
1034
1035         bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1036         if (!fetch_success) {
1037             if (cacheBlocked) {
1038                 ++icacheStallCycles;
1039             } else {
1040                 ++fetchMiscStallCycles;
1041             }
1042             return;
1043         }
1044     } else {
1045         if (fetchStatus[tid] == Idle) {
1046             ++fetchIdleCycles;
1047             DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1048         } else if (fetchStatus[tid] == Blocked) {
1049             ++fetchBlockedCycles;
1050             DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1051         } else if (fetchStatus[tid] == Squashing) {
1052             ++fetchSquashCycles;
1053             DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1054         } else if (fetchStatus[tid] == IcacheWaitResponse) {
1055             ++icacheStallCycles;
1056             DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid);
1057         }
1058
1059         // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1060         // fetch should do nothing.
1061         return;
1062     }
1063
1064     ++fetchCycles;
1065
1066     // If we had a stall due to an icache miss, then return.
1067     if (fetchStatus[tid] == IcacheWaitResponse) {
1068         ++icacheStallCycles;
1069         status_change = true;
1070         return;
1071     }
1072
1073     Addr next_PC = fetch_PC;
1074     Addr next_NPC = fetch_NPC;
1075     Addr next_MicroPC = fetch_MicroPC;
1076
1077     InstSeqNum inst_seq;
1078     MachInst inst;
1079     ExtMachInst ext_inst;
1080     // @todo: Fix this hack.
1081     unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1082
1083     StaticInstPtr staticInst = NULL;
1084     StaticInstPtr macroop = NULL;
1085
1086     if (fault == NoFault) {
1087         // If the read of the first instruction was successful, then grab the
1088         // instructions from the rest of the cache line and put them into the
1089         // queue heading to decode.
1090
1091         DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1092                 "decode.\n",tid);
1093
1094         // Need to keep track of whether or not a predicted branch
1095         // ended this fetch block.
1096         bool predicted_branch = false;
1097
1098         while (offset < cacheBlkSize &&
1099                numInst < fetchWidth &&
1100                !predicted_branch) {
1101
1102             // If we're branching after this instruction, quite fetching
1103             // from the same block then.
1104             predicted_branch =
1105                 (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC);
1106             if (predicted_branch) {
1107                 DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n",
1108                         fetch_PC, fetch_NPC);
1109             }
1110
1111             // Make sure this is a valid index.
1112             assert(offset <= cacheBlkSize - instSize);
1113
1114             if (!macroop) {
1115                 // Get the instruction from the array of the cache line.
1116                 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1117                             (&cacheData[tid][offset]));
1118
1119                 predecoder.setTC(cpu->thread[tid]->getTC());
1120                 predecoder.moreBytes(fetch_PC, fetch_PC, inst);
1121
1122                 ext_inst = predecoder.getExtMachInst();
1123                 staticInst = StaticInstPtr(ext_inst, fetch_PC);
1124                 if (staticInst->isMacroop())
1125                     macroop = staticInst;
1126             }
1127             do {
1128                 if (macroop) {
1129                     staticInst = macroop->fetchMicroop(fetch_MicroPC);
1130                     if (staticInst->isLastMicroop())
1131                         macroop = NULL;
1132                 }
1133
1134                 // Get a sequence number.
1135                 inst_seq = cpu->getAndIncrementInstSeq();
1136
1137                 // Create a new DynInst from the instruction fetched.
1138                 DynInstPtr instruction = new DynInst(staticInst,
1139                                                      fetch_PC, fetch_NPC, fetch_MicroPC,
1140                                                      next_PC, next_NPC, next_MicroPC,
1141                                                      inst_seq, cpu);
1142                 instruction->setTid(tid);
1143
1144                 instruction->setASID(tid);
1145
1146                 instruction->setThreadState(cpu->thread[tid]);
1147
1148                 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1149                         "[sn:%lli]\n",
1150                         tid, instruction->readPC(), inst_seq);
1151
1152                 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
1153
1154                 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1155                         tid, instruction->staticInst->disassemble(fetch_PC));
1156
1157 #if TRACING_ON
1158                 instruction->traceData =
1159                     cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid),
1160                             instruction->staticInst, instruction->readPC());
1161 #else
1162                 instruction->traceData = NULL;
1163 #endif
1164
1165                 ///FIXME This needs to be more robust in dealing with delay slots
1166                 predicted_branch |=
1167                     lookupAndUpdateNextPC(instruction, next_PC, next_NPC, next_MicroPC);
1168
1169                 // Add instruction to the CPU's list of instructions.
1170                 instruction->setInstListIt(cpu->addInst(instruction));
1171
1172                 // Write the instruction to the first slot in the queue
1173                 // that heads to decode.
1174                 toDecode->insts[numInst] = instruction;
1175
1176                 toDecode->size++;
1177
1178                 // Increment stat of fetched instructions.
1179                 ++fetchedInsts;
1180
1181                 // Move to the next instruction, unless we have a branch.
1182                 fetch_PC = next_PC;
1183                 fetch_NPC = next_NPC;
1184                 fetch_MicroPC = next_MicroPC;
1185
1186                 if (instruction->isQuiesce()) {
1187                     DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1188                             curTick);
1189                     fetchStatus[tid] = QuiescePending;
1190                     ++numInst;
1191                     status_change = true;
1192                     break;
1193                 }
1194
1195                 ++numInst;
1196             } while (staticInst->isMicroop() &&
1197                      !staticInst->isLastMicroop() &&
1198                      numInst < fetchWidth);
1199             offset += instSize;
1200         }
1201
1202         if (predicted_branch) {
1203             DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1204                     "instruction encountered.\n", tid);
1205         } else if (numInst >= fetchWidth) {
1206             DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1207                     "for this cycle.\n", tid);
1208         } else if (offset >= cacheBlkSize) {
1209             DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1210                     "block.\n", tid);
1211         }
1212     }
1213
1214     if (numInst > 0) {
1215         wroteToTimeBuffer = true;
1216     }
1217
1218     // Now that fetching is completed, update the PC to signify what the next
1219     // cycle will be.
1220     if (fault == NoFault) {
1221         PC[tid] = next_PC;
1222         nextPC[tid] = next_NPC;
1223         microPC[tid] = next_MicroPC;
1224         DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC);
1225     } else {
1226         // We shouldn't be in an icache miss and also have a fault (an ITB
1227         // miss)
1228         if (fetchStatus[tid] == IcacheWaitResponse) {
1229             panic("Fetch should have exited prior to this!");
1230         }
1231
1232         // Send the fault to commit.  This thread will not do anything
1233         // until commit handles the fault.  The only other way it can
1234         // wake up is if a squash comes along and changes the PC.
1235 #if FULL_SYSTEM
1236         assert(numInst < fetchWidth);
1237         // Get a sequence number.
1238         inst_seq = cpu->getAndIncrementInstSeq();
1239         // We will use a nop in order to carry the fault.
1240         ext_inst = TheISA::NoopMachInst;
1241
1242         // Create a new DynInst from the dummy nop.
1243         DynInstPtr instruction = new DynInst(ext_inst,
1244                                              fetch_PC, fetch_NPC, fetch_MicroPC,
1245                                              next_PC, next_NPC, next_MicroPC,
1246                                              inst_seq, cpu);
1247         instruction->setPredTarg(next_PC, next_NPC, 1);
1248         instruction->setTid(tid);
1249
1250         instruction->setASID(tid);
1251
1252         instruction->setThreadState(cpu->thread[tid]);
1253
1254         instruction->traceData = NULL;
1255
1256         instruction->setInstListIt(cpu->addInst(instruction));
1257
1258         instruction->fault = fault;
1259
1260         toDecode->insts[numInst] = instruction;
1261         toDecode->size++;
1262
1263         DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1264
1265         fetchStatus[tid] = TrapPending;
1266         status_change = true;
1267 #else // !FULL_SYSTEM
1268         fetchStatus[tid] = TrapPending;
1269         status_change = true;
1270
1271 #endif // FULL_SYSTEM
1272         DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
1273                 tid, fault->name(), PC[tid]);
1274     }
1275 }
1276
1277 template<class Impl>
1278 void
1279 DefaultFetch<Impl>::recvRetry()
1280 {
1281     if (retryPkt != NULL) {
1282         assert(cacheBlocked);
1283         assert(retryTid != -1);
1284         assert(fetchStatus[retryTid] == IcacheWaitRetry);
1285
1286         if (icachePort->sendTiming(retryPkt)) {
1287             fetchStatus[retryTid] = IcacheWaitResponse;
1288             retryPkt = NULL;
1289             retryTid = -1;
1290             cacheBlocked = false;
1291         }
1292     } else {
1293         assert(retryTid == -1);
1294         // Access has been squashed since it was sent out.  Just clear
1295         // the cache being blocked.
1296         cacheBlocked = false;
1297     }
1298 }
1299
1300 ///////////////////////////////////////
1301 //                                   //
1302 //  SMT FETCH POLICY MAINTAINED HERE //
1303 //                                   //
1304 ///////////////////////////////////////
1305 template<class Impl>
1306 int
1307 DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1308 {
1309     if (numThreads > 1) {
1310         switch (fetch_priority) {
1311
1312           case SingleThread:
1313             return 0;
1314
1315           case RoundRobin:
1316             return roundRobin();
1317
1318           case IQ:
1319             return iqCount();
1320
1321           case LSQ:
1322             return lsqCount();
1323
1324           case Branch:
1325             return branchCount();
1326
1327           default:
1328             return -1;
1329         }
1330     } else {
1331         std::list<unsigned>::iterator thread = activeThreads->begin();
1332         assert(thread != activeThreads->end());
1333         int tid = *thread;
1334
1335         if (fetchStatus[tid] == Running ||
1336             fetchStatus[tid] == IcacheAccessComplete ||
1337             fetchStatus[tid] == Idle) {
1338             return tid;
1339         } else {
1340             return -1;
1341         }
1342     }
1343
1344 }
1345
1346
1347 template<class Impl>
1348 int
1349 DefaultFetch<Impl>::roundRobin()
1350 {
1351     std::list<unsigned>::iterator pri_iter = priorityList.begin();
1352     std::list<unsigned>::iterator end      = priorityList.end();
1353
1354     int high_pri;
1355
1356     while (pri_iter != end) {
1357         high_pri = *pri_iter;
1358
1359         assert(high_pri <= numThreads);
1360
1361         if (fetchStatus[high_pri] == Running ||
1362             fetchStatus[high_pri] == IcacheAccessComplete ||
1363             fetchStatus[high_pri] == Idle) {
1364
1365             priorityList.erase(pri_iter);
1366             priorityList.push_back(high_pri);
1367
1368             return high_pri;
1369         }
1370
1371         pri_iter++;
1372     }
1373
1374     return -1;
1375 }
1376
1377 template<class Impl>
1378 int
1379 DefaultFetch<Impl>::iqCount()
1380 {
1381     std::priority_queue<unsigned> PQ;
1382
1383     std::list<unsigned>::iterator threads = activeThreads->begin();
1384     std::list<unsigned>::iterator end = activeThreads->end();
1385
1386     while (threads != end) {
1387         unsigned tid = *threads++;
1388
1389         PQ.push(fromIEW->iewInfo[tid].iqCount);
1390     }
1391
1392     while (!PQ.empty()) {
1393
1394         unsigned high_pri = PQ.top();
1395
1396         if (fetchStatus[high_pri] == Running ||
1397             fetchStatus[high_pri] == IcacheAccessComplete ||
1398             fetchStatus[high_pri] == Idle)
1399             return high_pri;
1400         else
1401             PQ.pop();
1402
1403     }
1404
1405     return -1;
1406 }
1407
1408 template<class Impl>
1409 int
1410 DefaultFetch<Impl>::lsqCount()
1411 {
1412     std::priority_queue<unsigned> PQ;
1413
1414     std::list<unsigned>::iterator threads = activeThreads->begin();
1415     std::list<unsigned>::iterator end = activeThreads->end();
1416
1417     while (threads != end) {
1418         unsigned tid = *threads++;
1419
1420         PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1421     }
1422
1423     while (!PQ.empty()) {
1424
1425         unsigned high_pri = PQ.top();
1426
1427         if (fetchStatus[high_pri] == Running ||
1428             fetchStatus[high_pri] == IcacheAccessComplete ||
1429             fetchStatus[high_pri] == Idle)
1430             return high_pri;
1431         else
1432             PQ.pop();
1433
1434     }
1435
1436     return -1;
1437 }
1438
1439 template<class Impl>
1440 int
1441 DefaultFetch<Impl>::branchCount()
1442 {
1443     std::list<unsigned>::iterator thread = activeThreads->begin();
1444     assert(thread != activeThreads->end());
1445     unsigned tid = *thread;
1446
1447     panic("Branch Count Fetch policy unimplemented\n");
1448     return 0 * tid;
1449 }