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35 #include "config/use_checker.hh"
37 #include "arch/isa_traits.hh"
38 #include "arch/utility.hh"
39 #include "cpu/checker/cpu.hh"
40 #include "cpu/exetrace.hh"
41 #include "cpu/o3/fetch.hh"
42 #include "mem/packet.hh"
43 #include "mem/request.hh"
44 #include "sim/byteswap.hh"
45 #include "sim/host.hh"
46 #include "sim/core.hh"
49 #include "arch/tlb.hh"
50 #include "arch/vtophys.hh"
51 #include "sim/system.hh"
54 #include "params/DerivO3CPU.hh"
58 DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
67 DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
69 panic("DefaultFetch doesn't expect recvAtomic callback!");
75 DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
77 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
83 DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
85 if (status == RangeChange) {
86 if (!snoopRangeSent) {
87 snoopRangeSent = true;
88 sendStatusChange(Port::RangeChange);
93 panic("DefaultFetch doesn't expect recvStatusChange callback!");
98 DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
100 DPRINTF(Fetch, "Received timing\n");
101 if (pkt->isResponse()) {
102 fetch->processCacheCompletion(pkt);
104 //else Snooped a coherence request, just return
110 DefaultFetch<Impl>::IcachePort::recvRetry()
116 DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
120 decodeToFetchDelay(params->decodeToFetchDelay),
121 renameToFetchDelay(params->renameToFetchDelay),
122 iewToFetchDelay(params->iewToFetchDelay),
123 commitToFetchDelay(params->commitToFetchDelay),
124 fetchWidth(params->fetchWidth),
128 numThreads(params->numThreads),
129 numFetchingThreads(params->smtNumFetchingThreads),
130 interruptPending(false),
134 if (numThreads > Impl::MaxThreads)
135 fatal("numThreads (%d) is larger than compiled limit (%d),\n"
136 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n",
137 numThreads, static_cast<int>(Impl::MaxThreads));
139 // Set fetch stage's status to inactive.
142 std::string policy = params->smtFetchPolicy;
144 // Convert string to lowercase
145 std::transform(policy.begin(), policy.end(), policy.begin(),
146 (int(*)(int)) tolower);
148 // Figure out fetch policy
149 if (policy == "singlethread") {
150 fetchPolicy = SingleThread;
152 panic("Invalid Fetch Policy for a SMT workload.");
153 } else if (policy == "roundrobin") {
154 fetchPolicy = RoundRobin;
155 DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
156 } else if (policy == "branch") {
157 fetchPolicy = Branch;
158 DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
159 } else if (policy == "iqcount") {
161 DPRINTF(Fetch, "Fetch policy set to IQ count\n");
162 } else if (policy == "lsqcount") {
164 DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
166 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
167 " RoundRobin,LSQcount,IQcount}\n");
170 // Get the size of an instruction.
171 instSize = sizeof(TheISA::MachInst);
173 // Name is finally available, so create the port.
174 icachePort = new IcachePort(this);
176 icachePort->snoopRangeSent = false;
180 cpu->checker->setIcachePort(icachePort);
185 template <class Impl>
187 DefaultFetch<Impl>::name() const
189 return cpu->name() + ".fetch";
192 template <class Impl>
194 DefaultFetch<Impl>::regStats()
197 .name(name() + ".icacheStallCycles")
198 .desc("Number of cycles fetch is stalled on an Icache miss")
199 .prereq(icacheStallCycles);
202 .name(name() + ".Insts")
203 .desc("Number of instructions fetch has processed")
204 .prereq(fetchedInsts);
207 .name(name() + ".Branches")
208 .desc("Number of branches that fetch encountered")
209 .prereq(fetchedBranches);
212 .name(name() + ".predictedBranches")
213 .desc("Number of branches that fetch has predicted taken")
214 .prereq(predictedBranches);
217 .name(name() + ".Cycles")
218 .desc("Number of cycles fetch has run and was not squashing or"
220 .prereq(fetchCycles);
223 .name(name() + ".SquashCycles")
224 .desc("Number of cycles fetch has spent squashing")
225 .prereq(fetchSquashCycles);
228 .name(name() + ".IdleCycles")
229 .desc("Number of cycles fetch was idle")
230 .prereq(fetchIdleCycles);
233 .name(name() + ".BlockedCycles")
234 .desc("Number of cycles fetch has spent blocked")
235 .prereq(fetchBlockedCycles);
238 .name(name() + ".CacheLines")
239 .desc("Number of cache lines fetched")
240 .prereq(fetchedCacheLines);
243 .name(name() + ".MiscStallCycles")
244 .desc("Number of cycles fetch has spent waiting on interrupts, or "
245 "bad addresses, or out of MSHRs")
246 .prereq(fetchMiscStallCycles);
249 .name(name() + ".IcacheSquashes")
250 .desc("Number of outstanding Icache misses that were squashed")
251 .prereq(fetchIcacheSquashes);
254 .init(/* base value */ 0,
255 /* last value */ fetchWidth,
257 .name(name() + ".rateDist")
258 .desc("Number of instructions fetched each cycle (Total)")
262 .name(name() + ".idleRate")
263 .desc("Percent of cycles fetch was idle")
265 idleRate = fetchIdleCycles * 100 / cpu->numCycles;
268 .name(name() + ".branchRate")
269 .desc("Number of branch fetches per cycle")
270 .flags(Stats::total);
271 branchRate = fetchedBranches / cpu->numCycles;
274 .name(name() + ".rate")
275 .desc("Number of inst fetches per cycle")
276 .flags(Stats::total);
277 fetchRate = fetchedInsts / cpu->numCycles;
279 branchPred.regStats();
284 DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
286 timeBuffer = time_buffer;
288 // Create wires to get information from proper places in time buffer.
289 fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
290 fromRename = timeBuffer->getWire(-renameToFetchDelay);
291 fromIEW = timeBuffer->getWire(-iewToFetchDelay);
292 fromCommit = timeBuffer->getWire(-commitToFetchDelay);
297 DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
299 activeThreads = at_ptr;
304 DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
308 // Create wire to write information to proper place in fetch queue.
309 toDecode = fetchQueue->getWire(0);
314 DefaultFetch<Impl>::initStage()
316 // Setup PC and nextPC with initial state.
317 for (int tid = 0; tid < numThreads; tid++) {
318 PC[tid] = cpu->readPC(tid);
319 nextPC[tid] = cpu->readNextPC(tid);
320 microPC[tid] = cpu->readMicroPC(tid);
323 for (int tid=0; tid < numThreads; tid++) {
325 fetchStatus[tid] = Running;
327 priorityList.push_back(tid);
331 stalls[tid].decode = false;
332 stalls[tid].rename = false;
333 stalls[tid].iew = false;
334 stalls[tid].commit = false;
337 // Schedule fetch to get the correct PC from the CPU
338 // scheduleFetchStartupEvent(1);
340 // Fetch needs to start fetching instructions at the very beginning,
341 // so it must start up in active state.
347 DefaultFetch<Impl>::setIcache()
349 // Size of cache block.
350 cacheBlkSize = icachePort->peerBlockSize();
352 // Create mask to get rid of offset bits.
353 cacheBlkMask = (cacheBlkSize - 1);
355 for (int tid=0; tid < numThreads; tid++) {
356 // Create space to store a cache line.
357 cacheData[tid] = new uint8_t[cacheBlkSize];
358 cacheDataPC[tid] = 0;
359 cacheDataValid[tid] = false;
365 DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
367 unsigned tid = pkt->req->threadId();
369 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
371 assert(!pkt->wasNacked());
373 // Only change the status if it's still waiting on the icache access
375 if (fetchStatus[tid] != IcacheWaitResponse ||
376 pkt->req != memReq[tid] ||
378 ++fetchIcacheSquashes;
384 memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
385 cacheDataValid[tid] = true;
388 // Wake up the CPU (if it went to sleep and was waiting on
389 // this completion event).
392 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
398 // Only switch to IcacheAccessComplete if we're not stalled as well.
399 if (checkStall(tid)) {
400 fetchStatus[tid] = Blocked;
402 fetchStatus[tid] = IcacheAccessComplete;
405 // Reset the mem req to NULL.
411 template <class Impl>
413 DefaultFetch<Impl>::drain()
415 // Fetch is ready to drain at any time.
416 cpu->signalDrained();
421 template <class Impl>
423 DefaultFetch<Impl>::resume()
425 drainPending = false;
428 template <class Impl>
430 DefaultFetch<Impl>::switchOut()
433 // Branch predictor needs to have its state cleared.
434 branchPred.switchOut();
437 template <class Impl>
439 DefaultFetch<Impl>::takeOverFrom()
442 for (int i = 0; i < Impl::MaxThreads; ++i) {
443 stalls[i].decode = 0;
444 stalls[i].rename = 0;
446 stalls[i].commit = 0;
447 PC[i] = cpu->readPC(i);
448 nextPC[i] = cpu->readNextPC(i);
449 microPC[i] = cpu->readMicroPC(i);
450 fetchStatus[i] = Running;
453 wroteToTimeBuffer = false;
456 interruptPending = false;
457 branchPred.takeOverFrom();
460 template <class Impl>
462 DefaultFetch<Impl>::wakeFromQuiesce()
464 DPRINTF(Fetch, "Waking up from quiesce\n");
465 // Hopefully this is safe
466 // @todo: Allow other threads to wake from quiesce.
467 fetchStatus[0] = Running;
470 template <class Impl>
472 DefaultFetch<Impl>::switchToActive()
474 if (_status == Inactive) {
475 DPRINTF(Activity, "Activating stage.\n");
477 cpu->activateStage(O3CPU::FetchIdx);
483 template <class Impl>
485 DefaultFetch<Impl>::switchToInactive()
487 if (_status == Active) {
488 DPRINTF(Activity, "Deactivating stage.\n");
490 cpu->deactivateStage(O3CPU::FetchIdx);
496 template <class Impl>
498 DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
499 Addr &next_NPC, Addr &next_MicroPC)
501 // Do branch prediction check here.
502 // A bit of a misnomer...next_PC is actually the current PC until
503 // this function updates it.
506 if (!inst->isControl()) {
507 if (inst->isMicroop() && !inst->isLastMicroop()) {
511 next_NPC = next_NPC + instSize;
514 inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
515 inst->setPredTaken(false);
519 //Assume for now that all control flow is to a different macroop which
520 //would reset the micro pc to 0.
523 int tid = inst->threadNumber;
524 Addr pred_PC = next_PC;
525 predict_taken = branchPred.predict(inst, pred_PC, tid);
527 /* if (predict_taken) {
528 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken to %#x.\n",
531 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid);
534 #if ISA_HAS_DELAY_SLOT
539 next_NPC += instSize;
545 next_NPC = next_PC + instSize;
547 /* DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n",
548 tid, next_PC, next_NPC);*/
549 inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
550 inst->setPredTaken(predict_taken);
558 return predict_taken;
561 template <class Impl>
563 DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
565 Fault fault = NoFault;
569 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
572 } else if (isSwitchedOut()) {
573 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
576 } else if (interruptPending && !(fetch_PC & 0x3)) {
577 // Hold off fetch from getting new instructions when:
578 // Cache is blocked, or
579 // while an interrupt is pending and we're not in PAL mode, or
580 // fetch is switched out.
581 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
586 // Align the fetch PC so it's at the start of a cache block.
587 Addr block_PC = icacheBlockAlignPC(fetch_PC);
589 // If we've already got the block, no need to try to fetch it again.
590 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
594 // Setup the memReq to do a read of the first instruction's address.
595 // Set the appropriate read size and flags as well.
596 // Build request here.
597 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
598 fetch_PC, cpu->thread[tid]->contextId(),
601 memReq[tid] = mem_req;
603 // Translate the instruction request.
604 fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC());
606 // In the case of faults, the fetch stage may need to stall and wait
607 // for the ITB miss to be handled.
609 // If translation was successful, attempt to read the first
611 if (fault == NoFault) {
613 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
614 memReq[tid]->isUncacheable()) {
615 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
616 "misspeculating path)!",
618 ret_fault = TheISA::genMachineCheckFault();
623 // Build packet here.
624 PacketPtr data_pkt = new Packet(mem_req,
625 MemCmd::ReadReq, Packet::Broadcast);
626 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
628 cacheDataPC[tid] = block_PC;
629 cacheDataValid[tid] = false;
631 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
635 // Now do the timing access to see whether or not the instruction
636 // exists within the cache.
637 if (!icachePort->sendTiming(data_pkt)) {
638 assert(retryPkt == NULL);
639 assert(retryTid == -1);
640 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
641 fetchStatus[tid] = IcacheWaitRetry;
648 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
650 lastIcacheStall[tid] = curTick;
652 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
655 fetchStatus[tid] = IcacheWaitResponse;
665 template <class Impl>
667 DefaultFetch<Impl>::doSquash(const Addr &new_PC,
668 const Addr &new_NPC, const Addr &new_microPC, unsigned tid)
670 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n",
671 tid, new_PC, new_NPC);
674 nextPC[tid] = new_NPC;
675 microPC[tid] = new_microPC;
677 // Clear the icache miss if it's outstanding.
678 if (fetchStatus[tid] == IcacheWaitResponse) {
679 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
684 // Get rid of the retrying packet if it was from this thread.
685 if (retryTid == tid) {
686 assert(cacheBlocked);
688 delete retryPkt->req;
695 fetchStatus[tid] = Squashing;
702 DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
703 const Addr &new_MicroPC,
704 const InstSeqNum &seq_num, unsigned tid)
706 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
708 doSquash(new_PC, new_NPC, new_MicroPC, tid);
710 // Tell the CPU to remove any instructions that are in flight between
712 cpu->removeInstsUntil(seq_num, tid);
717 DefaultFetch<Impl>::checkStall(unsigned tid) const
719 bool ret_val = false;
721 if (cpu->contextSwitch) {
722 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
724 } else if (stalls[tid].decode) {
725 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
727 } else if (stalls[tid].rename) {
728 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
730 } else if (stalls[tid].iew) {
731 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
733 } else if (stalls[tid].commit) {
734 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
742 typename DefaultFetch<Impl>::FetchStatus
743 DefaultFetch<Impl>::updateFetchStatus()
746 std::list<unsigned>::iterator threads = activeThreads->begin();
747 std::list<unsigned>::iterator end = activeThreads->end();
749 while (threads != end) {
750 unsigned tid = *threads++;
752 if (fetchStatus[tid] == Running ||
753 fetchStatus[tid] == Squashing ||
754 fetchStatus[tid] == IcacheAccessComplete) {
756 if (_status == Inactive) {
757 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
759 if (fetchStatus[tid] == IcacheAccessComplete) {
760 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
764 cpu->activateStage(O3CPU::FetchIdx);
771 // Stage is switching from active to inactive, notify CPU of it.
772 if (_status == Active) {
773 DPRINTF(Activity, "Deactivating stage.\n");
775 cpu->deactivateStage(O3CPU::FetchIdx);
781 template <class Impl>
783 DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
784 const Addr &new_MicroPC,
785 const InstSeqNum &seq_num, unsigned tid)
787 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
789 doSquash(new_PC, new_NPC, new_MicroPC, tid);
791 // Tell the CPU to remove any instructions that are not in the ROB.
792 cpu->removeInstsNotInROB(tid);
795 template <class Impl>
797 DefaultFetch<Impl>::tick()
799 std::list<unsigned>::iterator threads = activeThreads->begin();
800 std::list<unsigned>::iterator end = activeThreads->end();
801 bool status_change = false;
803 wroteToTimeBuffer = false;
805 while (threads != end) {
806 unsigned tid = *threads++;
808 // Check the signals for each thread to determine the proper status
810 bool updated_status = checkSignalsAndUpdate(tid);
811 status_change = status_change || updated_status;
814 DPRINTF(Fetch, "Running stage.\n");
816 // Reset the number of the instruction we're fetching.
820 if (fromCommit->commitInfo[0].interruptPending) {
821 interruptPending = true;
824 if (fromCommit->commitInfo[0].clearInterrupt) {
825 interruptPending = false;
829 for (threadFetched = 0; threadFetched < numFetchingThreads;
831 // Fetch each of the actively fetching threads.
832 fetch(status_change);
835 // Record number of instructions fetched this cycle for distribution.
836 fetchNisnDist.sample(numInst);
839 // Change the fetch stage status if there was a status change.
840 _status = updateFetchStatus();
843 // If there was activity this cycle, inform the CPU of it.
844 if (wroteToTimeBuffer || cpu->contextSwitch) {
845 DPRINTF(Activity, "Activity this cycle.\n");
847 cpu->activityThisCycle();
851 template <class Impl>
853 DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
855 // Update the per thread stall statuses.
856 if (fromDecode->decodeBlock[tid]) {
857 stalls[tid].decode = true;
860 if (fromDecode->decodeUnblock[tid]) {
861 assert(stalls[tid].decode);
862 assert(!fromDecode->decodeBlock[tid]);
863 stalls[tid].decode = false;
866 if (fromRename->renameBlock[tid]) {
867 stalls[tid].rename = true;
870 if (fromRename->renameUnblock[tid]) {
871 assert(stalls[tid].rename);
872 assert(!fromRename->renameBlock[tid]);
873 stalls[tid].rename = false;
876 if (fromIEW->iewBlock[tid]) {
877 stalls[tid].iew = true;
880 if (fromIEW->iewUnblock[tid]) {
881 assert(stalls[tid].iew);
882 assert(!fromIEW->iewBlock[tid]);
883 stalls[tid].iew = false;
886 if (fromCommit->commitBlock[tid]) {
887 stalls[tid].commit = true;
890 if (fromCommit->commitUnblock[tid]) {
891 assert(stalls[tid].commit);
892 assert(!fromCommit->commitBlock[tid]);
893 stalls[tid].commit = false;
896 // Check squash signals from commit.
897 if (fromCommit->commitInfo[tid].squash) {
899 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
900 "from commit.\n",tid);
901 // In any case, squash.
902 squash(fromCommit->commitInfo[tid].nextPC,
903 fromCommit->commitInfo[tid].nextNPC,
904 fromCommit->commitInfo[tid].nextMicroPC,
905 fromCommit->commitInfo[tid].doneSeqNum,
908 // Also check if there's a mispredict that happened.
909 if (fromCommit->commitInfo[tid].branchMispredict) {
910 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
911 fromCommit->commitInfo[tid].nextPC,
912 fromCommit->commitInfo[tid].branchTaken,
915 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
920 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
921 // Update the branch predictor if it wasn't a squashed instruction
922 // that was broadcasted.
923 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
926 // Check ROB squash signals from commit.
927 if (fromCommit->commitInfo[tid].robSquashing) {
928 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
930 // Continue to squash.
931 fetchStatus[tid] = Squashing;
936 // Check squash signals from decode.
937 if (fromDecode->decodeInfo[tid].squash) {
938 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
939 "from decode.\n",tid);
941 // Update the branch predictor.
942 if (fromDecode->decodeInfo[tid].branchMispredict) {
943 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
944 fromDecode->decodeInfo[tid].nextPC,
945 fromDecode->decodeInfo[tid].branchTaken,
948 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
952 if (fetchStatus[tid] != Squashing) {
954 DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n",
955 fromDecode->decodeInfo[tid].nextPC,
956 fromDecode->decodeInfo[tid].nextNPC);
957 // Squash unless we're already squashing
958 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
959 fromDecode->decodeInfo[tid].nextNPC,
960 fromDecode->decodeInfo[tid].nextMicroPC,
961 fromDecode->decodeInfo[tid].doneSeqNum,
968 if (checkStall(tid) &&
969 fetchStatus[tid] != IcacheWaitResponse &&
970 fetchStatus[tid] != IcacheWaitRetry) {
971 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
973 fetchStatus[tid] = Blocked;
978 if (fetchStatus[tid] == Blocked ||
979 fetchStatus[tid] == Squashing) {
980 // Switch status to running if fetch isn't being told to block or
981 // squash this cycle.
982 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
985 fetchStatus[tid] = Running;
990 // If we've reached this point, we have not gotten any signals that
991 // cause fetch to change its status. Fetch remains the same as before.
997 DefaultFetch<Impl>::fetch(bool &status_change)
999 //////////////////////////////////////////
1000 // Start actual fetch
1001 //////////////////////////////////////////
1002 int tid = getFetchingThread(fetchPolicy);
1004 if (tid == -1 || drainPending) {
1005 DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1007 // Breaks looping condition in tick()
1008 threadFetched = numFetchingThreads;
1012 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1015 Addr fetch_PC = PC[tid];
1016 Addr fetch_NPC = nextPC[tid];
1017 Addr fetch_MicroPC = microPC[tid];
1019 // Fault code for memory access.
1020 Fault fault = NoFault;
1022 // If returning from the delay of a cache miss, then update the status
1023 // to running, otherwise do the cache access. Possibly move this up
1024 // to tick() function.
1025 if (fetchStatus[tid] == IcacheAccessComplete) {
1026 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1029 fetchStatus[tid] = Running;
1030 status_change = true;
1031 } else if (fetchStatus[tid] == Running) {
1032 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1033 "instruction, starting at PC %08p.\n",
1036 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1037 if (!fetch_success) {
1039 ++icacheStallCycles;
1041 ++fetchMiscStallCycles;
1046 if (fetchStatus[tid] == Idle) {
1048 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1049 } else if (fetchStatus[tid] == Blocked) {
1050 ++fetchBlockedCycles;
1051 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1052 } else if (fetchStatus[tid] == Squashing) {
1053 ++fetchSquashCycles;
1054 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1055 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1056 ++icacheStallCycles;
1057 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid);
1060 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1061 // fetch should do nothing.
1067 // If we had a stall due to an icache miss, then return.
1068 if (fetchStatus[tid] == IcacheWaitResponse) {
1069 ++icacheStallCycles;
1070 status_change = true;
1074 Addr next_PC = fetch_PC;
1075 Addr next_NPC = fetch_NPC;
1076 Addr next_MicroPC = fetch_MicroPC;
1078 InstSeqNum inst_seq;
1080 ExtMachInst ext_inst;
1081 // @todo: Fix this hack.
1082 unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1084 StaticInstPtr staticInst = NULL;
1085 StaticInstPtr macroop = NULL;
1087 if (fault == NoFault) {
1088 // If the read of the first instruction was successful, then grab the
1089 // instructions from the rest of the cache line and put them into the
1090 // queue heading to decode.
1092 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1095 // Need to keep track of whether or not a predicted branch
1096 // ended this fetch block.
1097 bool predicted_branch = false;
1099 while (offset < cacheBlkSize &&
1100 numInst < fetchWidth &&
1101 !predicted_branch) {
1103 // If we're branching after this instruction, quite fetching
1104 // from the same block then.
1106 (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC);
1107 if (predicted_branch) {
1108 DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n",
1109 fetch_PC, fetch_NPC);
1112 // Make sure this is a valid index.
1113 assert(offset <= cacheBlkSize - instSize);
1116 // Get the instruction from the array of the cache line.
1117 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1118 (&cacheData[tid][offset]));
1120 predecoder.setTC(cpu->thread[tid]->getTC());
1121 predecoder.moreBytes(fetch_PC, fetch_PC, inst);
1123 ext_inst = predecoder.getExtMachInst();
1124 staticInst = StaticInstPtr(ext_inst, fetch_PC);
1125 if (staticInst->isMacroop())
1126 macroop = staticInst;
1130 staticInst = macroop->fetchMicroop(fetch_MicroPC);
1131 if (staticInst->isLastMicroop())
1135 // Get a sequence number.
1136 inst_seq = cpu->getAndIncrementInstSeq();
1138 // Create a new DynInst from the instruction fetched.
1139 DynInstPtr instruction = new DynInst(staticInst,
1140 fetch_PC, fetch_NPC, fetch_MicroPC,
1141 next_PC, next_NPC, next_MicroPC,
1143 instruction->setTid(tid);
1145 instruction->setASID(tid);
1147 instruction->setThreadState(cpu->thread[tid]);
1149 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1151 tid, instruction->readPC(), inst_seq);
1153 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
1155 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1156 tid, instruction->staticInst->disassemble(fetch_PC));
1159 instruction->traceData =
1160 cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid),
1161 instruction->staticInst, instruction->readPC());
1163 instruction->traceData = NULL;
1166 ///FIXME This needs to be more robust in dealing with delay slots
1168 lookupAndUpdateNextPC(instruction, next_PC, next_NPC, next_MicroPC);
1170 // Add instruction to the CPU's list of instructions.
1171 instruction->setInstListIt(cpu->addInst(instruction));
1173 // Write the instruction to the first slot in the queue
1174 // that heads to decode.
1175 toDecode->insts[numInst] = instruction;
1179 // Increment stat of fetched instructions.
1182 // Move to the next instruction, unless we have a branch.
1184 fetch_NPC = next_NPC;
1185 fetch_MicroPC = next_MicroPC;
1187 if (instruction->isQuiesce()) {
1188 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1190 fetchStatus[tid] = QuiescePending;
1192 status_change = true;
1197 } while (staticInst->isMicroop() &&
1198 !staticInst->isLastMicroop() &&
1199 numInst < fetchWidth);
1203 if (predicted_branch) {
1204 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1205 "instruction encountered.\n", tid);
1206 } else if (numInst >= fetchWidth) {
1207 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1208 "for this cycle.\n", tid);
1209 } else if (offset >= cacheBlkSize) {
1210 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1216 wroteToTimeBuffer = true;
1219 // Now that fetching is completed, update the PC to signify what the next
1221 if (fault == NoFault) {
1223 nextPC[tid] = next_NPC;
1224 microPC[tid] = next_MicroPC;
1225 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC);
1227 // We shouldn't be in an icache miss and also have a fault (an ITB
1229 if (fetchStatus[tid] == IcacheWaitResponse) {
1230 panic("Fetch should have exited prior to this!");
1233 // Send the fault to commit. This thread will not do anything
1234 // until commit handles the fault. The only other way it can
1235 // wake up is if a squash comes along and changes the PC.
1236 assert(numInst < fetchWidth);
1237 // Get a sequence number.
1238 inst_seq = cpu->getAndIncrementInstSeq();
1239 // We will use a nop in order to carry the fault.
1240 ext_inst = TheISA::NoopMachInst;
1242 // Create a new DynInst from the dummy nop.
1243 DynInstPtr instruction = new DynInst(ext_inst,
1244 fetch_PC, fetch_NPC, fetch_MicroPC,
1245 next_PC, next_NPC, next_MicroPC,
1247 instruction->setPredTarg(next_NPC, next_NPC + instSize, 0);
1248 instruction->setTid(tid);
1250 instruction->setASID(tid);
1252 instruction->setThreadState(cpu->thread[tid]);
1254 instruction->traceData = NULL;
1256 instruction->setInstListIt(cpu->addInst(instruction));
1258 instruction->fault = fault;
1260 toDecode->insts[numInst] = instruction;
1263 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1265 fetchStatus[tid] = TrapPending;
1266 status_change = true;
1268 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
1269 tid, fault->name(), PC[tid]);
1273 template<class Impl>
1275 DefaultFetch<Impl>::recvRetry()
1277 if (retryPkt != NULL) {
1278 assert(cacheBlocked);
1279 assert(retryTid != -1);
1280 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1282 if (icachePort->sendTiming(retryPkt)) {
1283 fetchStatus[retryTid] = IcacheWaitResponse;
1286 cacheBlocked = false;
1289 assert(retryTid == -1);
1290 // Access has been squashed since it was sent out. Just clear
1291 // the cache being blocked.
1292 cacheBlocked = false;
1296 ///////////////////////////////////////
1298 // SMT FETCH POLICY MAINTAINED HERE //
1300 ///////////////////////////////////////
1301 template<class Impl>
1303 DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1305 if (numThreads > 1) {
1306 switch (fetch_priority) {
1312 return roundRobin();
1321 return branchCount();
1327 std::list<unsigned>::iterator thread = activeThreads->begin();
1328 assert(thread != activeThreads->end());
1331 if (fetchStatus[tid] == Running ||
1332 fetchStatus[tid] == IcacheAccessComplete ||
1333 fetchStatus[tid] == Idle) {
1343 template<class Impl>
1345 DefaultFetch<Impl>::roundRobin()
1347 std::list<unsigned>::iterator pri_iter = priorityList.begin();
1348 std::list<unsigned>::iterator end = priorityList.end();
1352 while (pri_iter != end) {
1353 high_pri = *pri_iter;
1355 assert(high_pri <= numThreads);
1357 if (fetchStatus[high_pri] == Running ||
1358 fetchStatus[high_pri] == IcacheAccessComplete ||
1359 fetchStatus[high_pri] == Idle) {
1361 priorityList.erase(pri_iter);
1362 priorityList.push_back(high_pri);
1373 template<class Impl>
1375 DefaultFetch<Impl>::iqCount()
1377 std::priority_queue<unsigned> PQ;
1379 std::list<unsigned>::iterator threads = activeThreads->begin();
1380 std::list<unsigned>::iterator end = activeThreads->end();
1382 while (threads != end) {
1383 unsigned tid = *threads++;
1385 PQ.push(fromIEW->iewInfo[tid].iqCount);
1388 while (!PQ.empty()) {
1390 unsigned high_pri = PQ.top();
1392 if (fetchStatus[high_pri] == Running ||
1393 fetchStatus[high_pri] == IcacheAccessComplete ||
1394 fetchStatus[high_pri] == Idle)
1404 template<class Impl>
1406 DefaultFetch<Impl>::lsqCount()
1408 std::priority_queue<unsigned> PQ;
1410 std::list<unsigned>::iterator threads = activeThreads->begin();
1411 std::list<unsigned>::iterator end = activeThreads->end();
1413 while (threads != end) {
1414 unsigned tid = *threads++;
1416 PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1419 while (!PQ.empty()) {
1421 unsigned high_pri = PQ.top();
1423 if (fetchStatus[high_pri] == Running ||
1424 fetchStatus[high_pri] == IcacheAccessComplete ||
1425 fetchStatus[high_pri] == Idle)
1435 template<class Impl>
1437 DefaultFetch<Impl>::branchCount()
1439 std::list<unsigned>::iterator thread = activeThreads->begin();
1440 assert(thread != activeThreads->end());
1441 unsigned tid = *thread;
1443 panic("Branch Count Fetch policy unimplemented\n");