src/cpu/o3/fetch_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Korey Sewell
  30  */
  31
  32 #include <algorithm>
  33 #include <cstring>
  34
  35 #include "config/use_checker.hh"
  36
  37 #include "arch/isa_traits.hh"
  38 #include "arch/utility.hh"
  39 #include "cpu/checker/cpu.hh"
  40 #include "cpu/exetrace.hh"
  41 #include "cpu/o3/fetch.hh"
  42 #include "mem/packet.hh"
  43 #include "mem/request.hh"
  44 #include "sim/byteswap.hh"
  45 #include "sim/host.hh"
  46 #include "sim/core.hh"
  47
  48 #if FULL_SYSTEM
  49 #include "arch/tlb.hh"
  50 #include "arch/vtophys.hh"
  51 #include "sim/system.hh"
  52 #endif // FULL_SYSTEM
  53
  54 template<class Impl>
  55 void
  56 DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
  57 {
  58     Port::setPeer(port);
  59
  60     fetch->setIcache();
  61 }
  62
  63 template<class Impl>
  64 Tick
  65 DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
  66 {
  67     panic("DefaultFetch doesn't expect recvAtomic callback!");
  68     return curTick;
  69 }
  70
  71 template<class Impl>
  72 void
  73 DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
  74 {
  75     DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
  76             "functional call.");
  77 }
  78
  79 template<class Impl>
  80 void
  81 DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
  82 {
  83     if (status == RangeChange) {
  84         if (!snoopRangeSent) {
  85             snoopRangeSent = true;
  86             sendStatusChange(Port::RangeChange);
  87         }
  88         return;
  89     }
  90
  91     panic("DefaultFetch doesn't expect recvStatusChange callback!");
  92 }
  93
  94 template<class Impl>
  95 bool
  96 DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
  97 {
  98     DPRINTF(Fetch, "Received timing\n");
  99     if (pkt->isResponse()) {
 100         fetch->processCacheCompletion(pkt);
 101     }
 102     //else Snooped a coherence request, just return
 103     return true;
 104 }
 105
 106 template<class Impl>
 107 void
 108 DefaultFetch<Impl>::IcachePort::recvRetry()
 109 {
 110     fetch->recvRetry();
 111 }
 112
 113 template<class Impl>
 114 DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, Params *params)
 115     : cpu(_cpu),
 116       branchPred(params),
 117       predecoder(NULL),
 118       decodeToFetchDelay(params->decodeToFetchDelay),
 119       renameToFetchDelay(params->renameToFetchDelay),
 120       iewToFetchDelay(params->iewToFetchDelay),
 121       commitToFetchDelay(params->commitToFetchDelay),
 122       fetchWidth(params->fetchWidth),
 123       cacheBlocked(false),
 124       retryPkt(NULL),
 125       retryTid(-1),
 126       numThreads(params->numberOfThreads),
 127       numFetchingThreads(params->smtNumFetchingThreads),
 128       interruptPending(false),
 129       drainPending(false),
 130       switchedOut(false)
 131 {
 132     if (numThreads > Impl::MaxThreads)
 133         fatal("numThreads is not a valid value\n");
 134
 135     // Set fetch stage's status to inactive.
 136     _status = Inactive;
 137
 138     std::string policy = params->smtFetchPolicy;
 139
 140     // Convert string to lowercase
 141     std::transform(policy.begin(), policy.end(), policy.begin(),
 142                    (int(*)(int)) tolower);
 143
 144     // Figure out fetch policy
 145     if (policy == "singlethread") {
 146         fetchPolicy = SingleThread;
 147         if (numThreads > 1)
 148             panic("Invalid Fetch Policy for a SMT workload.");
 149     } else if (policy == "roundrobin") {
 150         fetchPolicy = RoundRobin;
 151         DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
 152     } else if (policy == "branch") {
 153         fetchPolicy = Branch;
 154         DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
 155     } else if (policy == "iqcount") {
 156         fetchPolicy = IQ;
 157         DPRINTF(Fetch, "Fetch policy set to IQ count\n");
 158     } else if (policy == "lsqcount") {
 159         fetchPolicy = LSQ;
 160         DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
 161     } else {
 162         fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
 163               " RoundRobin,LSQcount,IQcount}\n");
 164     }
 165
 166     // Get the size of an instruction.
 167     instSize = sizeof(TheISA::MachInst);
 168
 169     // Name is finally available, so create the port.
 170     icachePort = new IcachePort(this);
 171
 172     icachePort->snoopRangeSent = false;
 173
 174 #if USE_CHECKER
 175     if (cpu->checker) {
 176         cpu->checker->setIcachePort(icachePort);
 177     }
 178 #endif
 179 }
 180
 181 template <class Impl>
 182 std::string
 183 DefaultFetch<Impl>::name() const
 184 {
 185     return cpu->name() + ".fetch";
 186 }
 187
 188 template <class Impl>
 189 void
 190 DefaultFetch<Impl>::regStats()
 191 {
 192     icacheStallCycles
 193         .name(name() + ".icacheStallCycles")
 194         .desc("Number of cycles fetch is stalled on an Icache miss")
 195         .prereq(icacheStallCycles);
 196
 197     fetchedInsts
 198         .name(name() + ".Insts")
 199         .desc("Number of instructions fetch has processed")
 200         .prereq(fetchedInsts);
 201
 202     fetchedBranches
 203         .name(name() + ".Branches")
 204         .desc("Number of branches that fetch encountered")
 205         .prereq(fetchedBranches);
 206
 207     predictedBranches
 208         .name(name() + ".predictedBranches")
 209         .desc("Number of branches that fetch has predicted taken")
 210         .prereq(predictedBranches);
 211
 212     fetchCycles
 213         .name(name() + ".Cycles")
 214         .desc("Number of cycles fetch has run and was not squashing or"
 215               " blocked")
 216         .prereq(fetchCycles);
 217
 218     fetchSquashCycles
 219         .name(name() + ".SquashCycles")
 220         .desc("Number of cycles fetch has spent squashing")
 221         .prereq(fetchSquashCycles);
 222
 223     fetchIdleCycles
 224         .name(name() + ".IdleCycles")
 225         .desc("Number of cycles fetch was idle")
 226         .prereq(fetchIdleCycles);
 227
 228     fetchBlockedCycles
 229         .name(name() + ".BlockedCycles")
 230         .desc("Number of cycles fetch has spent blocked")
 231         .prereq(fetchBlockedCycles);
 232
 233     fetchedCacheLines
 234         .name(name() + ".CacheLines")
 235         .desc("Number of cache lines fetched")
 236         .prereq(fetchedCacheLines);
 237
 238     fetchMiscStallCycles
 239         .name(name() + ".MiscStallCycles")
 240         .desc("Number of cycles fetch has spent waiting on interrupts, or "
 241               "bad addresses, or out of MSHRs")
 242         .prereq(fetchMiscStallCycles);
 243
 244     fetchIcacheSquashes
 245         .name(name() + ".IcacheSquashes")
 246         .desc("Number of outstanding Icache misses that were squashed")
 247         .prereq(fetchIcacheSquashes);
 248
 249     fetchNisnDist
 250         .init(/* base value */ 0,
 251               /* last value */ fetchWidth,
 252               /* bucket size */ 1)
 253         .name(name() + ".rateDist")
 254         .desc("Number of instructions fetched each cycle (Total)")
 255         .flags(Stats::pdf);
 256
 257     idleRate
 258         .name(name() + ".idleRate")
 259         .desc("Percent of cycles fetch was idle")
 260         .prereq(idleRate);
 261     idleRate = fetchIdleCycles * 100 / cpu->numCycles;
 262
 263     branchRate
 264         .name(name() + ".branchRate")
 265         .desc("Number of branch fetches per cycle")
 266         .flags(Stats::total);
 267     branchRate = fetchedBranches / cpu->numCycles;
 268
 269     fetchRate
 270         .name(name() + ".rate")
 271         .desc("Number of inst fetches per cycle")
 272         .flags(Stats::total);
 273     fetchRate = fetchedInsts / cpu->numCycles;
 274
 275     branchPred.regStats();
 276 }
 277
 278 template<class Impl>
 279 void
 280 DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
 281 {
 282     timeBuffer = time_buffer;
 283
 284     // Create wires to get information from proper places in time buffer.
 285     fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
 286     fromRename = timeBuffer->getWire(-renameToFetchDelay);
 287     fromIEW = timeBuffer->getWire(-iewToFetchDelay);
 288     fromCommit = timeBuffer->getWire(-commitToFetchDelay);
 289 }
 290
 291 template<class Impl>
 292 void
 293 DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
 294 {
 295     activeThreads = at_ptr;
 296 }
 297
 298 template<class Impl>
 299 void
 300 DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
 301 {
 302     fetchQueue = fq_ptr;
 303
 304     // Create wire to write information to proper place in fetch queue.
 305     toDecode = fetchQueue->getWire(0);
 306 }
 307
 308 template<class Impl>
 309 void
 310 DefaultFetch<Impl>::initStage()
 311 {
 312     // Setup PC and nextPC with initial state.
 313     for (int tid = 0; tid < numThreads; tid++) {
 314         PC[tid] = cpu->readPC(tid);
 315         nextPC[tid] = cpu->readNextPC(tid);
 316         nextNPC[tid] = cpu->readNextNPC(tid);
 317     }
 318
 319     for (int tid=0; tid < numThreads; tid++) {
 320
 321         fetchStatus[tid] = Running;
 322
 323         priorityList.push_back(tid);
 324
 325         memReq[tid] = NULL;
 326
 327         stalls[tid].decode = false;
 328         stalls[tid].rename = false;
 329         stalls[tid].iew = false;
 330         stalls[tid].commit = false;
 331     }
 332
 333     // Schedule fetch to get the correct PC from the CPU
 334     // scheduleFetchStartupEvent(1);
 335
 336     // Fetch needs to start fetching instructions at the very beginning,
 337     // so it must start up in active state.
 338     switchToActive();
 339 }
 340
 341 template<class Impl>
 342 void
 343 DefaultFetch<Impl>::setIcache()
 344 {
 345     // Size of cache block.
 346     cacheBlkSize = icachePort->peerBlockSize();
 347
 348     // Create mask to get rid of offset bits.
 349     cacheBlkMask = (cacheBlkSize - 1);
 350
 351     for (int tid=0; tid < numThreads; tid++) {
 352         // Create space to store a cache line.
 353         cacheData[tid] = new uint8_t[cacheBlkSize];
 354         cacheDataPC[tid] = 0;
 355         cacheDataValid[tid] = false;
 356     }
 357 }
 358
 359 template<class Impl>
 360 void
 361 DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
 362 {
 363     unsigned tid = pkt->req->getThreadNum();
 364
 365     DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
 366
 367     // Only change the status if it's still waiting on the icache access
 368     // to return.
 369     if (fetchStatus[tid] != IcacheWaitResponse ||
 370         pkt->req != memReq[tid] ||
 371         isSwitchedOut()) {
 372         ++fetchIcacheSquashes;
 373         delete pkt->req;
 374         delete pkt;
 375         return;
 376     }
 377
 378     memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
 379     cacheDataValid[tid] = true;
 380
 381     if (!drainPending) {
 382         // Wake up the CPU (if it went to sleep and was waiting on
 383         // this completion event).
 384         cpu->wakeCPU();
 385
 386         DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
 387                 tid);
 388
 389         switchToActive();
 390     }
 391
 392     // Only switch to IcacheAccessComplete if we're not stalled as well.
 393     if (checkStall(tid)) {
 394         fetchStatus[tid] = Blocked;
 395     } else {
 396         fetchStatus[tid] = IcacheAccessComplete;
 397     }
 398
 399     // Reset the mem req to NULL.
 400     delete pkt->req;
 401     delete pkt;
 402     memReq[tid] = NULL;
 403 }
 404
 405 template <class Impl>
 406 bool
 407 DefaultFetch<Impl>::drain()
 408 {
 409     // Fetch is ready to drain at any time.
 410     cpu->signalDrained();
 411     drainPending = true;
 412     return true;
 413 }
 414
 415 template <class Impl>
 416 void
 417 DefaultFetch<Impl>::resume()
 418 {
 419     drainPending = false;
 420 }
 421
 422 template <class Impl>
 423 void
 424 DefaultFetch<Impl>::switchOut()
 425 {
 426     switchedOut = true;
 427     // Branch predictor needs to have its state cleared.
 428     branchPred.switchOut();
 429 }
 430
 431 template <class Impl>
 432 void
 433 DefaultFetch<Impl>::takeOverFrom()
 434 {
 435     // Reset all state
 436     for (int i = 0; i < Impl::MaxThreads; ++i) {
 437         stalls[i].decode = 0;
 438         stalls[i].rename = 0;
 439         stalls[i].iew = 0;
 440         stalls[i].commit = 0;
 441         PC[i] = cpu->readPC(i);
 442         nextPC[i] = cpu->readNextPC(i);
 443 #if ISA_HAS_DELAY_SLOT
 444         nextNPC[i] = cpu->readNextNPC(i);
 445 #else
 446         nextNPC[i] = nextPC[i] + sizeof(TheISA::MachInst);
 447 #endif
 448         fetchStatus[i] = Running;
 449     }
 450     numInst = 0;
 451     wroteToTimeBuffer = false;
 452     _status = Inactive;
 453     switchedOut = false;
 454     interruptPending = false;
 455     branchPred.takeOverFrom();
 456 }
 457
 458 template <class Impl>
 459 void
 460 DefaultFetch<Impl>::wakeFromQuiesce()
 461 {
 462     DPRINTF(Fetch, "Waking up from quiesce\n");
 463     // Hopefully this is safe
 464     // @todo: Allow other threads to wake from quiesce.
 465     fetchStatus[0] = Running;
 466 }
 467
 468 template <class Impl>
 469 inline void
 470 DefaultFetch<Impl>::switchToActive()
 471 {
 472     if (_status == Inactive) {
 473         DPRINTF(Activity, "Activating stage.\n");
 474
 475         cpu->activateStage(O3CPU::FetchIdx);
 476
 477         _status = Active;
 478     }
 479 }
 480
 481 template <class Impl>
 482 inline void
 483 DefaultFetch<Impl>::switchToInactive()
 484 {
 485     if (_status == Active) {
 486         DPRINTF(Activity, "Deactivating stage.\n");
 487
 488         cpu->deactivateStage(O3CPU::FetchIdx);
 489
 490         _status = Inactive;
 491     }
 492 }
 493
 494 template <class Impl>
 495 bool
 496 DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
 497                                           Addr &next_NPC)
 498 {
 499     // Do branch prediction check here.
 500     // A bit of a misnomer...next_PC is actually the current PC until
 501     // this function updates it.
 502     bool predict_taken;
 503
 504     if (!inst->isControl()) {
 505         next_PC  = next_NPC;
 506         next_NPC = next_NPC + instSize;
 507         inst->setPredTarg(next_PC, next_NPC);
 508         inst->setPredTaken(false);
 509         return false;
 510     }
 511
 512     int tid = inst->threadNumber;
 513     Addr pred_PC = next_PC;
 514     predict_taken = branchPred.predict(inst, pred_PC, tid);
 515
 516 /*    if (predict_taken) {
 517         DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken to %#x.\n",
 518                 tid, pred_PC);
 519     } else {
 520         DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid);
 521     }*/
 522
 523 #if ISA_HAS_DELAY_SLOT
 524     next_PC = next_NPC;
 525     if (predict_taken)
 526         next_NPC = pred_PC;
 527     else
 528         next_NPC += instSize;
 529 #else
 530     if (predict_taken)
 531         next_PC = pred_PC;
 532     else
 533         next_PC += instSize;
 534     next_NPC = next_PC + instSize;
 535 #endif
 536 /*    DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n",
 537             tid, next_PC, next_NPC);*/
 538     inst->setPredTarg(next_PC, next_NPC);
 539     inst->setPredTaken(predict_taken);
 540
 541     ++fetchedBranches;
 542
 543     if (predict_taken) {
 544         ++predictedBranches;
 545     }
 546
 547     return predict_taken;
 548 }
 549
 550 template <class Impl>
 551 bool
 552 DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
 553 {
 554     Fault fault = NoFault;
 555
 556     //AlphaDep
 557     if (cacheBlocked) {
 558         DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
 559                 tid);
 560         return false;
 561     } else if (isSwitchedOut()) {
 562         DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
 563                 tid);
 564         return false;
 565     } else if (interruptPending && !(fetch_PC & 0x3)) {
 566         // Hold off fetch from getting new instructions when:
 567         // Cache is blocked, or
 568         // while an interrupt is pending and we're not in PAL mode, or
 569         // fetch is switched out.
 570         DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
 571                 tid);
 572         return false;
 573     }
 574
 575     // Align the fetch PC so it's at the start of a cache block.
 576     Addr block_PC = icacheBlockAlignPC(fetch_PC);
 577
 578     // If we've already got the block, no need to try to fetch it again.
 579     if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
 580         return true;
 581     }
 582
 583     // Setup the memReq to do a read of the first instruction's address.
 584     // Set the appropriate read size and flags as well.
 585     // Build request here.
 586     RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
 587                                      fetch_PC, cpu->readCpuId(), tid);
 588
 589     memReq[tid] = mem_req;
 590
 591     // Translate the instruction request.
 592     fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
 593
 594     // In the case of faults, the fetch stage may need to stall and wait
 595     // for the ITB miss to be handled.
 596
 597     // If translation was successful, attempt to read the first
 598     // instruction.
 599     if (fault == NoFault) {
 600 #if 0
 601         if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
 602             memReq[tid]->isUncacheable()) {
 603             DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
 604                     "misspeculating path)!",
 605                     memReq[tid]->paddr);
 606             ret_fault = TheISA::genMachineCheckFault();
 607             return false;
 608         }
 609 #endif
 610
 611         // Build packet here.
 612         PacketPtr data_pkt = new Packet(mem_req,
 613                                         MemCmd::ReadReq, Packet::Broadcast);
 614         data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
 615
 616         cacheDataPC[tid] = block_PC;
 617         cacheDataValid[tid] = false;
 618
 619         DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
 620
 621         fetchedCacheLines++;
 622
 623         // Now do the timing access to see whether or not the instruction
 624         // exists within the cache.
 625         if (!icachePort->sendTiming(data_pkt)) {
 626             if (data_pkt->result == Packet::BadAddress) {
 627                 fault = TheISA::genMachineCheckFault();
 628                 delete mem_req;
 629                 memReq[tid] = NULL;
 630                 warn("Bad address!\n");
 631             }
 632             assert(retryPkt == NULL);
 633             assert(retryTid == -1);
 634             DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
 635             fetchStatus[tid] = IcacheWaitRetry;
 636             retryPkt = data_pkt;
 637             retryTid = tid;
 638             cacheBlocked = true;
 639             return false;
 640         }
 641
 642         DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
 643
 644         lastIcacheStall[tid] = curTick;
 645
 646         DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
 647                 "response.\n", tid);
 648
 649         fetchStatus[tid] = IcacheWaitResponse;
 650     } else {
 651         delete mem_req;
 652         memReq[tid] = NULL;
 653     }
 654
 655     ret_fault = fault;
 656     return true;
 657 }
 658
 659 template <class Impl>
 660 inline void
 661 DefaultFetch<Impl>::doSquash(const Addr &new_PC,
 662         const Addr &new_NPC, unsigned tid)
 663 {
 664     DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n",
 665             tid, new_PC, new_NPC);
 666
 667     PC[tid] = new_PC;
 668     nextPC[tid] = new_NPC;
 669     nextNPC[tid] = new_NPC + instSize;
 670
 671     // Clear the icache miss if it's outstanding.
 672     if (fetchStatus[tid] == IcacheWaitResponse) {
 673         DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
 674                 tid);
 675         memReq[tid] = NULL;
 676     }
 677
 678     // Get rid of the retrying packet if it was from this thread.
 679     if (retryTid == tid) {
 680         assert(cacheBlocked);
 681         if (retryPkt) {
 682             delete retryPkt->req;
 683             delete retryPkt;
 684         }
 685         retryPkt = NULL;
 686         retryTid = -1;
 687     }
 688
 689     fetchStatus[tid] = Squashing;
 690
 691     ++fetchSquashCycles;
 692 }
 693
 694 template<class Impl>
 695 void
 696 DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
 697                                      const InstSeqNum &seq_num,
 698                                      unsigned tid)
 699 {
 700     DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
 701
 702     doSquash(new_PC, new_NPC, tid);
 703
 704     // Tell the CPU to remove any instructions that are in flight between
 705     // fetch and decode.
 706     cpu->removeInstsUntil(seq_num, tid);
 707 }
 708
 709 template<class Impl>
 710 bool
 711 DefaultFetch<Impl>::checkStall(unsigned tid) const
 712 {
 713     bool ret_val = false;
 714
 715     if (cpu->contextSwitch) {
 716         DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
 717         ret_val = true;
 718     } else if (stalls[tid].decode) {
 719         DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
 720         ret_val = true;
 721     } else if (stalls[tid].rename) {
 722         DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
 723         ret_val = true;
 724     } else if (stalls[tid].iew) {
 725         DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
 726         ret_val = true;
 727     } else if (stalls[tid].commit) {
 728         DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
 729         ret_val = true;
 730     }
 731
 732     return ret_val;
 733 }
 734
 735 template<class Impl>
 736 typename DefaultFetch<Impl>::FetchStatus
 737 DefaultFetch<Impl>::updateFetchStatus()
 738 {
 739     //Check Running
 740     std::list<unsigned>::iterator threads = activeThreads->begin();
 741     std::list<unsigned>::iterator end = activeThreads->end();
 742
 743     while (threads != end) {
 744         unsigned tid = *threads++;
 745
 746         if (fetchStatus[tid] == Running ||
 747             fetchStatus[tid] == Squashing ||
 748             fetchStatus[tid] == IcacheAccessComplete) {
 749
 750             if (_status == Inactive) {
 751                 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
 752
 753                 if (fetchStatus[tid] == IcacheAccessComplete) {
 754                     DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
 755                             "completion\n",tid);
 756                 }
 757
 758                 cpu->activateStage(O3CPU::FetchIdx);
 759             }
 760
 761             return Active;
 762         }
 763     }
 764
 765     // Stage is switching from active to inactive, notify CPU of it.
 766     if (_status == Active) {
 767         DPRINTF(Activity, "Deactivating stage.\n");
 768
 769         cpu->deactivateStage(O3CPU::FetchIdx);
 770     }
 771
 772     return Inactive;
 773 }
 774
 775 template <class Impl>
 776 void
 777 DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
 778                            const InstSeqNum &seq_num,
 779                            bool squash_delay_slot, unsigned tid)
 780 {
 781     DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
 782
 783     doSquash(new_PC, new_NPC, tid);
 784
 785 #if ISA_HAS_DELAY_SLOT
 786     // Tell the CPU to remove any instructions that are not in the ROB.
 787     cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
 788 #else
 789     // Tell the CPU to remove any instructions that are not in the ROB.
 790     cpu->removeInstsNotInROB(tid, true, 0);
 791 #endif
 792 }
 793
 794 template <class Impl>
 795 void
 796 DefaultFetch<Impl>::tick()
 797 {
 798     std::list<unsigned>::iterator threads = activeThreads->begin();
 799     std::list<unsigned>::iterator end = activeThreads->end();
 800     bool status_change = false;
 801
 802     wroteToTimeBuffer = false;
 803
 804     while (threads != end) {
 805         unsigned tid = *threads++;
 806
 807         // Check the signals for each thread to determine the proper status
 808         // for each thread.
 809         bool updated_status = checkSignalsAndUpdate(tid);
 810         status_change =  status_change || updated_status;
 811     }
 812
 813     DPRINTF(Fetch, "Running stage.\n");
 814
 815     // Reset the number of the instruction we're fetching.
 816     numInst = 0;
 817
 818 #if FULL_SYSTEM
 819     if (fromCommit->commitInfo[0].interruptPending) {
 820         interruptPending = true;
 821     }
 822
 823     if (fromCommit->commitInfo[0].clearInterrupt) {
 824         interruptPending = false;
 825     }
 826 #endif
 827
 828     for (threadFetched = 0; threadFetched < numFetchingThreads;
 829          threadFetched++) {
 830         // Fetch each of the actively fetching threads.
 831         fetch(status_change);
 832     }
 833
 834     // Record number of instructions fetched this cycle for distribution.
 835     fetchNisnDist.sample(numInst);
 836
 837     if (status_change) {
 838         // Change the fetch stage status if there was a status change.
 839         _status = updateFetchStatus();
 840     }
 841
 842     // If there was activity this cycle, inform the CPU of it.
 843     if (wroteToTimeBuffer || cpu->contextSwitch) {
 844         DPRINTF(Activity, "Activity this cycle.\n");
 845
 846         cpu->activityThisCycle();
 847     }
 848 }
 849
 850 template <class Impl>
 851 bool
 852 DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
 853 {
 854     // Update the per thread stall statuses.
 855     if (fromDecode->decodeBlock[tid]) {
 856         stalls[tid].decode = true;
 857     }
 858
 859     if (fromDecode->decodeUnblock[tid]) {
 860         assert(stalls[tid].decode);
 861         assert(!fromDecode->decodeBlock[tid]);
 862         stalls[tid].decode = false;
 863     }
 864
 865     if (fromRename->renameBlock[tid]) {
 866         stalls[tid].rename = true;
 867     }
 868
 869     if (fromRename->renameUnblock[tid]) {
 870         assert(stalls[tid].rename);
 871         assert(!fromRename->renameBlock[tid]);
 872         stalls[tid].rename = false;
 873     }
 874
 875     if (fromIEW->iewBlock[tid]) {
 876         stalls[tid].iew = true;
 877     }
 878
 879     if (fromIEW->iewUnblock[tid]) {
 880         assert(stalls[tid].iew);
 881         assert(!fromIEW->iewBlock[tid]);
 882         stalls[tid].iew = false;
 883     }
 884
 885     if (fromCommit->commitBlock[tid]) {
 886         stalls[tid].commit = true;
 887     }
 888
 889     if (fromCommit->commitUnblock[tid]) {
 890         assert(stalls[tid].commit);
 891         assert(!fromCommit->commitBlock[tid]);
 892         stalls[tid].commit = false;
 893     }
 894
 895     // Check squash signals from commit.
 896     if (fromCommit->commitInfo[tid].squash) {
 897
 898         DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
 899                 "from commit.\n",tid);
 900
 901 #if ISA_HAS_DELAY_SLOT
 902     InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
 903 #else
 904     InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
 905 #endif
 906         // In any case, squash.
 907         squash(fromCommit->commitInfo[tid].nextPC,
 908                fromCommit->commitInfo[tid].nextNPC,
 909                doneSeqNum,
 910                fromCommit->commitInfo[tid].squashDelaySlot,
 911                tid);
 912
 913         // Also check if there's a mispredict that happened.
 914         if (fromCommit->commitInfo[tid].branchMispredict) {
 915             branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
 916                               fromCommit->commitInfo[tid].nextPC,
 917                               fromCommit->commitInfo[tid].branchTaken,
 918                               tid);
 919         } else {
 920             branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
 921                               tid);
 922         }
 923
 924         return true;
 925     } else if (fromCommit->commitInfo[tid].doneSeqNum) {
 926         // Update the branch predictor if it wasn't a squashed instruction
 927         // that was broadcasted.
 928         branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
 929     }
 930
 931     // Check ROB squash signals from commit.
 932     if (fromCommit->commitInfo[tid].robSquashing) {
 933         DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
 934
 935         // Continue to squash.
 936         fetchStatus[tid] = Squashing;
 937
 938         return true;
 939     }
 940
 941     // Check squash signals from decode.
 942     if (fromDecode->decodeInfo[tid].squash) {
 943         DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
 944                 "from decode.\n",tid);
 945
 946         // Update the branch predictor.
 947         if (fromDecode->decodeInfo[tid].branchMispredict) {
 948             branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
 949                               fromDecode->decodeInfo[tid].nextPC,
 950                               fromDecode->decodeInfo[tid].branchTaken,
 951                               tid);
 952         } else {
 953             branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
 954                               tid);
 955         }
 956
 957         if (fetchStatus[tid] != Squashing) {
 958
 959 #if ISA_HAS_DELAY_SLOT
 960             InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
 961 #else
 962             InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
 963 #endif
 964             DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n",
 965                     fromDecode->decodeInfo[tid].nextPC,
 966                     fromDecode->decodeInfo[tid].nextNPC);
 967             // Squash unless we're already squashing
 968             squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
 969                              fromDecode->decodeInfo[tid].nextNPC,
 970                              doneSeqNum,
 971                              tid);
 972
 973             return true;
 974         }
 975     }
 976
 977     if (checkStall(tid) &&
 978         fetchStatus[tid] != IcacheWaitResponse &&
 979         fetchStatus[tid] != IcacheWaitRetry) {
 980         DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
 981
 982         fetchStatus[tid] = Blocked;
 983
 984         return true;
 985     }
 986
 987     if (fetchStatus[tid] == Blocked ||
 988         fetchStatus[tid] == Squashing) {
 989         // Switch status to running if fetch isn't being told to block or
 990         // squash this cycle.
 991         DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
 992                 tid);
 993
 994         fetchStatus[tid] = Running;
 995
 996         return true;
 997     }
 998
 999     // If we've reached this point, we have not gotten any signals that
1000     // cause fetch to change its status.  Fetch remains the same as before.
1001     return false;
1002 }
1003
1004 template<class Impl>
1005 void
1006 DefaultFetch<Impl>::fetch(bool &status_change)
1007 {
1008     //////////////////////////////////////////
1009     // Start actual fetch
1010     //////////////////////////////////////////
1011     int tid = getFetchingThread(fetchPolicy);
1012
1013     if (tid == -1 || drainPending) {
1014         DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1015
1016         // Breaks looping condition in tick()
1017         threadFetched = numFetchingThreads;
1018         return;
1019     }
1020
1021     DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1022
1023     // The current PC.
1024     Addr &fetch_PC = PC[tid];
1025
1026     Addr &fetch_NPC = nextPC[tid];
1027
1028     // Fault code for memory access.
1029     Fault fault = NoFault;
1030
1031     // If returning from the delay of a cache miss, then update the status
1032     // to running, otherwise do the cache access.  Possibly move this up
1033     // to tick() function.
1034     if (fetchStatus[tid] == IcacheAccessComplete) {
1035         DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1036                 tid);
1037
1038         fetchStatus[tid] = Running;
1039         status_change = true;
1040     } else if (fetchStatus[tid] == Running) {
1041         DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1042                 "instruction, starting at PC %08p.\n",
1043                 tid, fetch_PC);
1044
1045         bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1046         if (!fetch_success) {
1047             if (cacheBlocked) {
1048                 ++icacheStallCycles;
1049             } else {
1050                 ++fetchMiscStallCycles;
1051             }
1052             return;
1053         }
1054     } else {
1055         if (fetchStatus[tid] == Idle) {
1056             ++fetchIdleCycles;
1057             DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1058         } else if (fetchStatus[tid] == Blocked) {
1059             ++fetchBlockedCycles;
1060             DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1061         } else if (fetchStatus[tid] == Squashing) {
1062             ++fetchSquashCycles;
1063             DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1064         } else if (fetchStatus[tid] == IcacheWaitResponse) {
1065             ++icacheStallCycles;
1066             DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid);
1067         }
1068
1069         // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1070         // fetch should do nothing.
1071         return;
1072     }
1073
1074     ++fetchCycles;
1075
1076     // If we had a stall due to an icache miss, then return.
1077     if (fetchStatus[tid] == IcacheWaitResponse) {
1078         ++icacheStallCycles;
1079         status_change = true;
1080         return;
1081     }
1082
1083     Addr next_PC = fetch_PC;
1084     Addr next_NPC = fetch_NPC;
1085
1086     InstSeqNum inst_seq;
1087     MachInst inst;
1088     ExtMachInst ext_inst;
1089     // @todo: Fix this hack.
1090     unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1091
1092     if (fault == NoFault) {
1093         // If the read of the first instruction was successful, then grab the
1094         // instructions from the rest of the cache line and put them into the
1095         // queue heading to decode.
1096
1097         DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1098                 "decode.\n",tid);
1099
1100         // Need to keep track of whether or not a predicted branch
1101         // ended this fetch block.
1102         bool predicted_branch = false;
1103
1104         for (;
1105              offset < cacheBlkSize &&
1106                  numInst < fetchWidth &&
1107                  !predicted_branch;
1108              ++numInst) {
1109
1110             // If we're branching after this instruction, quite fetching
1111             // from the same block then.
1112             predicted_branch =
1113                 (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC);
1114             if (predicted_branch) {
1115                 DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n",
1116                         fetch_PC, fetch_NPC);
1117             }
1118
1119
1120             // Get a sequence number.
1121             inst_seq = cpu->getAndIncrementInstSeq();
1122
1123             // Make sure this is a valid index.
1124             assert(offset <= cacheBlkSize - instSize);
1125
1126             // Get the instruction from the array of the cache line.
1127             inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1128                         (&cacheData[tid][offset]));
1129
1130             predecoder.setTC(cpu->thread[tid]->getTC());
1131             predecoder.moreBytes(fetch_PC, fetch_PC, inst);
1132
1133             ext_inst = predecoder.getExtMachInst();
1134
1135             // Create a new DynInst from the instruction fetched.
1136             DynInstPtr instruction = new DynInst(ext_inst,
1137                                                  fetch_PC, fetch_NPC,
1138                                                  next_PC, next_NPC,
1139                                                  inst_seq, cpu);
1140             instruction->setTid(tid);
1141
1142             instruction->setASID(tid);
1143
1144             instruction->setThreadState(cpu->thread[tid]);
1145
1146             DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1147                     "[sn:%lli]\n",
1148                     tid, instruction->readPC(), inst_seq);
1149
1150             //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
1151
1152             DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1153                     tid, instruction->staticInst->disassemble(fetch_PC));
1154
1155 #if TRACING_ON
1156             instruction->traceData =
1157                 Trace::getInstRecord(curTick, cpu->tcBase(tid),
1158                                      instruction->staticInst,
1159                                      instruction->readPC());
1160 #else
1161             instruction->traceData = NULL;
1162 #endif
1163
1164             ///FIXME This needs to be more robust in dealing with delay slots
1165 #if !ISA_HAS_DELAY_SLOT
1166 //          predicted_branch |=
1167 #endif
1168             lookupAndUpdateNextPC(instruction, next_PC, next_NPC);
1169             predicted_branch |= (next_PC != fetch_NPC);
1170
1171             // Add instruction to the CPU's list of instructions.
1172             instruction->setInstListIt(cpu->addInst(instruction));
1173
1174             // Write the instruction to the first slot in the queue
1175             // that heads to decode.
1176             toDecode->insts[numInst] = instruction;
1177
1178             toDecode->size++;
1179
1180             // Increment stat of fetched instructions.
1181             ++fetchedInsts;
1182
1183             // Move to the next instruction, unless we have a branch.
1184             fetch_PC = next_PC;
1185             fetch_NPC = next_NPC;
1186
1187             if (instruction->isQuiesce()) {
1188                 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1189                         curTick);
1190                 fetchStatus[tid] = QuiescePending;
1191                 ++numInst;
1192                 status_change = true;
1193                 break;
1194             }
1195
1196             offset += instSize;
1197         }
1198
1199         if (offset >= cacheBlkSize) {
1200             DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1201                     "block.\n", tid);
1202         } else if (numInst >= fetchWidth) {
1203             DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1204                     "for this cycle.\n", tid);
1205         } else if (predicted_branch) {
1206             DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1207                     "instruction encountered.\n", tid);
1208         }
1209     }
1210
1211     if (numInst > 0) {
1212         wroteToTimeBuffer = true;
1213     }
1214
1215     // Now that fetching is completed, update the PC to signify what the next
1216     // cycle will be.
1217     if (fault == NoFault) {
1218         PC[tid] = next_PC;
1219         nextPC[tid] = next_NPC;
1220         nextNPC[tid] = next_NPC + instSize;
1221 #if ISA_HAS_DELAY_SLOT
1222         DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
1223 #else
1224         DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC);
1225 #endif
1226     } else {
1227         // We shouldn't be in an icache miss and also have a fault (an ITB
1228         // miss)
1229         if (fetchStatus[tid] == IcacheWaitResponse) {
1230             panic("Fetch should have exited prior to this!");
1231         }
1232
1233         // Send the fault to commit.  This thread will not do anything
1234         // until commit handles the fault.  The only other way it can
1235         // wake up is if a squash comes along and changes the PC.
1236 #if FULL_SYSTEM
1237         assert(numInst < fetchWidth);
1238         // Get a sequence number.
1239         inst_seq = cpu->getAndIncrementInstSeq();
1240         // We will use a nop in order to carry the fault.
1241         ext_inst = TheISA::NoopMachInst;
1242
1243         // Create a new DynInst from the dummy nop.
1244         DynInstPtr instruction = new DynInst(ext_inst,
1245                                              fetch_PC, fetch_NPC,
1246                                              next_PC, next_NPC,
1247                                              inst_seq, cpu);
1248         instruction->setPredTarg(next_PC, next_NPC);
1249         instruction->setTid(tid);
1250
1251         instruction->setASID(tid);
1252
1253         instruction->setThreadState(cpu->thread[tid]);
1254
1255         instruction->traceData = NULL;
1256
1257         instruction->setInstListIt(cpu->addInst(instruction));
1258
1259         instruction->fault = fault;
1260
1261         toDecode->insts[numInst] = instruction;
1262         toDecode->size++;
1263
1264         DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1265
1266         fetchStatus[tid] = TrapPending;
1267         status_change = true;
1268 #else // !FULL_SYSTEM
1269         fetchStatus[tid] = TrapPending;
1270         status_change = true;
1271
1272 #endif // FULL_SYSTEM
1273         DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
1274                 tid, fault->name(), PC[tid]);
1275     }
1276 }
1277
1278 template<class Impl>
1279 void
1280 DefaultFetch<Impl>::recvRetry()
1281 {
1282     if (retryPkt != NULL) {
1283         assert(cacheBlocked);
1284         assert(retryTid != -1);
1285         assert(fetchStatus[retryTid] == IcacheWaitRetry);
1286
1287         if (icachePort->sendTiming(retryPkt)) {
1288             fetchStatus[retryTid] = IcacheWaitResponse;
1289             retryPkt = NULL;
1290             retryTid = -1;
1291             cacheBlocked = false;
1292         }
1293     } else {
1294         assert(retryTid == -1);
1295         // Access has been squashed since it was sent out.  Just clear
1296         // the cache being blocked.
1297         cacheBlocked = false;
1298     }
1299 }
1300
1301 ///////////////////////////////////////
1302 //                                   //
1303 //  SMT FETCH POLICY MAINTAINED HERE //
1304 //                                   //
1305 ///////////////////////////////////////
1306 template<class Impl>
1307 int
1308 DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1309 {
1310     if (numThreads > 1) {
1311         switch (fetch_priority) {
1312
1313           case SingleThread:
1314             return 0;
1315
1316           case RoundRobin:
1317             return roundRobin();
1318
1319           case IQ:
1320             return iqCount();
1321
1322           case LSQ:
1323             return lsqCount();
1324
1325           case Branch:
1326             return branchCount();
1327
1328           default:
1329             return -1;
1330         }
1331     } else {
1332         std::list<unsigned>::iterator thread = activeThreads->begin();
1333         assert(thread != activeThreads->end());
1334         int tid = *thread;
1335
1336         if (fetchStatus[tid] == Running ||
1337             fetchStatus[tid] == IcacheAccessComplete ||
1338             fetchStatus[tid] == Idle) {
1339             return tid;
1340         } else {
1341             return -1;
1342         }
1343     }
1344
1345 }
1346
1347
1348 template<class Impl>
1349 int
1350 DefaultFetch<Impl>::roundRobin()
1351 {
1352     std::list<unsigned>::iterator pri_iter = priorityList.begin();
1353     std::list<unsigned>::iterator end      = priorityList.end();
1354
1355     int high_pri;
1356
1357     while (pri_iter != end) {
1358         high_pri = *pri_iter;
1359
1360         assert(high_pri <= numThreads);
1361
1362         if (fetchStatus[high_pri] == Running ||
1363             fetchStatus[high_pri] == IcacheAccessComplete ||
1364             fetchStatus[high_pri] == Idle) {
1365
1366             priorityList.erase(pri_iter);
1367             priorityList.push_back(high_pri);
1368
1369             return high_pri;
1370         }
1371
1372         pri_iter++;
1373     }
1374
1375     return -1;
1376 }
1377
1378 template<class Impl>
1379 int
1380 DefaultFetch<Impl>::iqCount()
1381 {
1382     std::priority_queue<unsigned> PQ;
1383
1384     std::list<unsigned>::iterator threads = activeThreads->begin();
1385     std::list<unsigned>::iterator end = activeThreads->end();
1386
1387     while (threads != end) {
1388         unsigned tid = *threads++;
1389
1390         PQ.push(fromIEW->iewInfo[tid].iqCount);
1391     }
1392
1393     while (!PQ.empty()) {
1394
1395         unsigned high_pri = PQ.top();
1396
1397         if (fetchStatus[high_pri] == Running ||
1398             fetchStatus[high_pri] == IcacheAccessComplete ||
1399             fetchStatus[high_pri] == Idle)
1400             return high_pri;
1401         else
1402             PQ.pop();
1403
1404     }
1405
1406     return -1;
1407 }
1408
1409 template<class Impl>
1410 int
1411 DefaultFetch<Impl>::lsqCount()
1412 {
1413     std::priority_queue<unsigned> PQ;
1414
1415     std::list<unsigned>::iterator threads = activeThreads->begin();
1416     std::list<unsigned>::iterator end = activeThreads->end();
1417
1418     while (threads != end) {
1419         unsigned tid = *threads++;
1420
1421         PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1422     }
1423
1424     while (!PQ.empty()) {
1425
1426         unsigned high_pri = PQ.top();
1427
1428         if (fetchStatus[high_pri] == Running ||
1429             fetchStatus[high_pri] == IcacheAccessComplete ||
1430             fetchStatus[high_pri] == Idle)
1431             return high_pri;
1432         else
1433             PQ.pop();
1434
1435     }
1436
1437     return -1;
1438 }
1439
1440 template<class Impl>
1441 int
1442 DefaultFetch<Impl>::branchCount()
1443 {
1444     std::list<unsigned>::iterator thread = activeThreads->begin();
1445     assert(thread != activeThreads->end());
1446     unsigned tid = *thread;
1447
1448     panic("Branch Count Fetch policy unimplemented\n");
1449     return 0 * tid;
1450 }