src/cpu/o3/free_list.hh

   1 /*
   2  * Copyright (c) 2016-2018 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder. You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
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  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #ifndef __CPU_O3_FREE_LIST_HH__
  43 #define __CPU_O3_FREE_LIST_HH__
  44
  45 #include <iostream>
  46 #include <queue>
  47 #include <vector>
  48
  49 #include "base/logging.hh"
  50 #include "base/trace.hh"
  51 #include "cpu/o3/comm.hh"
  52 #include "cpu/o3/regfile.hh"
  53 #include "debug/FreeList.hh"
  54
  55 /**
  56  * Free list for a single class of registers (e.g., integer
  57  * or floating point).  Because the register class is implicitly
  58  * determined by the rename map instance being accessed, all
  59  * architectural register index parameters and values in this class
  60  * are relative (e.g., %fp2 is just index 2).
  61  */
  62 class SimpleFreeList
  63 {
  64   private:
  65
  66     /** The actual free list */
  67     std::queue<PhysRegIdPtr> freeRegs;
  68
  69   public:
  70
  71     SimpleFreeList() {};
  72
  73     /** Add a physical register to the free list */
  74     void addReg(PhysRegIdPtr reg) { freeRegs.push(reg); }
  75
  76     /** Add physical registers to the free list */
  77     template<class InputIt>
  78     void
  79     addRegs(InputIt first, InputIt last) {
  80         std::for_each(first, last, [this](typename InputIt::value_type& reg) {
  81             this->freeRegs.push(&reg);
  82         });
  83     }
  84
  85     /** Get the next available register from the free list */
  86     PhysRegIdPtr getReg()
  87     {
  88         assert(!freeRegs.empty());
  89         PhysRegIdPtr free_reg = freeRegs.front();
  90         freeRegs.pop();
  91         return free_reg;
  92     }
  93
  94     /** Return the number of free registers on the list. */
  95     unsigned numFreeRegs() const { return freeRegs.size(); }
  96
  97     /** True iff there are free registers on the list. */
  98     bool hasFreeRegs() const { return !freeRegs.empty(); }
  99 };
 100
 101
 102 /**
 103  * FreeList class that simply holds the list of free integer and floating
 104  * point registers.  Can request for a free register of either type, and
 105  * also send back free registers of either type.  This is a very simple
 106  * class, but it should be sufficient for most implementations.  Like all
 107  * other classes, it assumes that the indices for the floating point
 108  * registers starts after the integer registers end.  Hence the variable
 109  * numPhysicalIntRegs is logically equivalent to the baseFP dependency.
 110  * Note that while this most likely should be called FreeList, the name
 111  * "FreeList" is used in a typedef within the CPU Policy, and therefore no
 112  * class can be named simply "FreeList".
 113  * @todo: Give a better name to the base FP dependency.
 114  */
 115 class UnifiedFreeList
 116 {
 117   private:
 118
 119     /** The object name, for DPRINTF.  We have to declare this
 120      *  explicitly because Scoreboard is not a SimObject. */
 121     const std::string _name;
 122
 123     /** The list of free integer registers. */
 124     SimpleFreeList intList;
 125
 126     /** The list of free floating point registers. */
 127     SimpleFreeList floatList;
 128
 129     /** The following two are exclusive interfaces. */
 130     /** @{ */
 131     /** The list of free vector registers. */
 132     SimpleFreeList vecList;
 133
 134     /** The list of free vector element registers. */
 135     SimpleFreeList vecElemList;
 136     /** @} */
 137
 138     /** The list of free predicate registers. */
 139     SimpleFreeList predList;
 140
 141     /** The list of free condition-code registers. */
 142     SimpleFreeList ccList;
 143
 144     /**
 145      * The register file object is used only to distinguish integer
 146      * from floating-point physical register indices.
 147      */
 148     PhysRegFile *regFile;
 149
 150     /*
 151      * We give UnifiedRenameMap internal access so it can get at the
 152      * internal per-class free lists and associate those with its
 153      * per-class rename maps. See UnifiedRenameMap::init().
 154      */
 155     friend class UnifiedRenameMap;
 156
 157   public:
 158     /** Constructs a free list.
 159      *  @param _numPhysicalIntRegs Number of physical integer registers.
 160      *  @param reservedIntRegs Number of integer registers already
 161      *                         used by initial mappings.
 162      *  @param _numPhysicalFloatRegs Number of physical fp registers.
 163      *  @param reservedFloatRegs Number of fp registers already
 164      *                           used by initial mappings.
 165      */
 166     UnifiedFreeList(const std::string &_my_name, PhysRegFile *_regFile);
 167
 168     /** Gives the name of the freelist. */
 169     std::string name() const { return _name; };
 170
 171     /** Returns a pointer to the condition-code free list */
 172     SimpleFreeList *getCCList() { return &ccList; }
 173
 174     /** Gets a free integer register. */
 175     PhysRegIdPtr getIntReg() { return intList.getReg(); }
 176
 177     /** Gets a free fp register. */
 178     PhysRegIdPtr getFloatReg() { return floatList.getReg(); }
 179
 180     /** Gets a free vector register. */
 181     PhysRegIdPtr getVecReg() { return vecList.getReg(); }
 182
 183     /** Gets a free vector elemenet register. */
 184     PhysRegIdPtr getVecElem() { return vecElemList.getReg(); }
 185
 186     /** Gets a free predicate register. */
 187     PhysRegIdPtr getVecPredReg() { return predList.getReg(); }
 188
 189     /** Gets a free cc register. */
 190     PhysRegIdPtr getCCReg() { return ccList.getReg(); }
 191
 192     /** Adds a register back to the free list. */
 193     void addReg(PhysRegIdPtr freed_reg);
 194
 195     /** Adds a register back to the free list. */
 196     template<class InputIt>
 197     void addRegs(InputIt first, InputIt last);
 198
 199     /** Adds an integer register back to the free list. */
 200     void addIntReg(PhysRegIdPtr freed_reg) { intList.addReg(freed_reg); }
 201
 202     /** Adds a fp register back to the free list. */
 203     void addFloatReg(PhysRegIdPtr freed_reg) { floatList.addReg(freed_reg); }
 204
 205     /** Adds a vector register back to the free list. */
 206     void addVecReg(PhysRegIdPtr freed_reg) { vecList.addReg(freed_reg); }
 207
 208     /** Adds a vector element register back to the free list. */
 209     void addVecElem(PhysRegIdPtr freed_reg) {
 210         vecElemList.addReg(freed_reg);
 211     }
 212
 213     /** Adds a predicate register back to the free list. */
 214     void addVecPredReg(PhysRegIdPtr freed_reg) { predList.addReg(freed_reg); }
 215
 216     /** Adds a cc register back to the free list. */
 217     void addCCReg(PhysRegIdPtr freed_reg) { ccList.addReg(freed_reg); }
 218
 219     /** Checks if there are any free integer registers. */
 220     bool hasFreeIntRegs() const { return intList.hasFreeRegs(); }
 221
 222     /** Checks if there are any free fp registers. */
 223     bool hasFreeFloatRegs() const { return floatList.hasFreeRegs(); }
 224
 225     /** Checks if there are any free vector registers. */
 226     bool hasFreeVecRegs() const { return vecList.hasFreeRegs(); }
 227
 228     /** Checks if there are any free vector registers. */
 229     bool hasFreeVecElems() const { return vecElemList.hasFreeRegs(); }
 230
 231     /** Checks if there are any free predicate registers. */
 232     bool hasFreeVecPredRegs() const { return predList.hasFreeRegs(); }
 233
 234     /** Checks if there are any free cc registers. */
 235     bool hasFreeCCRegs() const { return ccList.hasFreeRegs(); }
 236
 237     /** Returns the number of free integer registers. */
 238     unsigned numFreeIntRegs() const { return intList.numFreeRegs(); }
 239
 240     /** Returns the number of free fp registers. */
 241     unsigned numFreeFloatRegs() const { return floatList.numFreeRegs(); }
 242
 243     /** Returns the number of free vector registers. */
 244     unsigned numFreeVecRegs() const { return vecList.numFreeRegs(); }
 245
 246     /** Returns the number of free vector registers. */
 247     unsigned numFreeVecElems() const { return vecElemList.numFreeRegs(); }
 248
 249     /** Returns the number of free predicate registers. */
 250     unsigned numFreeVecPredRegs() const { return predList.numFreeRegs(); }
 251
 252     /** Returns the number of free cc registers. */
 253     unsigned numFreeCCRegs() const { return ccList.numFreeRegs(); }
 254 };
 255
 256 template<class InputIt>
 257 inline void
 258 UnifiedFreeList::addRegs(InputIt first, InputIt last)
 259 {
 260     // Are there any registers to add?
 261     if (first == last)
 262         return;
 263
 264     panic_if((first != last) &&
 265             first->classValue() != (last-1)->classValue(),
 266             "Attempt to add mixed type regs: %s and %s",
 267             first->className(),
 268             (last-1)->className());
 269     switch (first->classValue()) {
 270         case IntRegClass:
 271             intList.addRegs(first, last);
 272             break;
 273         case FloatRegClass:
 274             floatList.addRegs(first, last);
 275             break;
 276         case VecRegClass:
 277             vecList.addRegs(first, last);
 278             break;
 279         case VecElemClass:
 280             vecElemList.addRegs(first, last);
 281             break;
 282         case VecPredRegClass:
 283             predList.addRegs(first, last);
 284             break;
 285         case CCRegClass:
 286             ccList.addRegs(first, last);
 287             break;
 288         default:
 289             panic("Unexpected RegClass (%s)",
 290                                    first->className());
 291     }
 292
 293 }
 294
 295 inline void
 296 UnifiedFreeList::addReg(PhysRegIdPtr freed_reg)
 297 {
 298     DPRINTF(FreeList,"Freeing register %i (%s).\n", freed_reg->index(),
 299             freed_reg->className());
 300     //Might want to add in a check for whether or not this register is
 301     //already in there.  A bit vector or something similar would be useful.
 302     switch (freed_reg->classValue()) {
 303         case IntRegClass:
 304             intList.addReg(freed_reg);
 305             break;
 306         case FloatRegClass:
 307             floatList.addReg(freed_reg);
 308             break;
 309         case VecRegClass:
 310             vecList.addReg(freed_reg);
 311             break;
 312         case VecElemClass:
 313             vecElemList.addReg(freed_reg);
 314             break;
 315         case VecPredRegClass:
 316             predList.addReg(freed_reg);
 317             break;
 318         case CCRegClass:
 319             ccList.addReg(freed_reg);
 320             break;
 321         default:
 322             panic("Unexpected RegClass (%s)",
 323                                    freed_reg->className());
 324     }
 325
 326     // These assert conditions ensure that the number of free
 327     // registers are not more than the # of total Physical  Registers.
 328     // If this were false, it would mean that registers
 329     // have been freed twice, overflowing the free register
 330     // pool and potentially crashing SMT workloads.
 331     // ----
 332     // Comment out for now so as to not potentially break
 333     // CMP and single-threaded workloads
 334     // ----
 335     // assert(freeIntRegs.size() <= numPhysicalIntRegs);
 336     // assert(freeFloatRegs.size() <= numPhysicalFloatRegs);
 337 }
 338
 339
 340 #endif // __CPU_O3_FREE_LIST_HH__