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43 #ifndef __CPU_O3_IEW_HH__
44 #define __CPU_O3_IEW_HH__
49 #include "base/statistics.hh"
50 #include "cpu/o3/comm.hh"
51 #include "cpu/o3/lsq.hh"
52 #include "cpu/o3/scoreboard.hh"
53 #include "cpu/timebuf.hh"
54 #include "debug/IEW.hh"
56 struct DerivO3CPUParams;
60 * DefaultIEW handles both single threaded and SMT IEW
61 * (issue/execute/writeback). It handles the dispatching of
62 * instructions to the LSQ/IQ as part of the issue stage, and has the
63 * IQ try to issue instructions each cycle. The execute latency is
64 * actually tied into the issue latency to allow the IQ to be able to
65 * do back-to-back scheduling without having to speculatively schedule
66 * instructions. This happens by having the IQ have access to the
67 * functional units, and the IQ gets the execution latencies from the
68 * FUs when it issues instructions. Instructions reach the execute
69 * stage on the last cycle of their execution, which is when the IQ
70 * knows to wake up any dependent instructions, allowing back to back
71 * scheduling. The execute portion of IEW separates memory
72 * instructions from non-memory instructions, either telling the LSQ
73 * to execute the instruction, or executing the instruction directly.
74 * The writeback portion of IEW completes the instructions by waking
75 * up any dependents, and marking the register ready on the
83 typedef typename Impl::CPUPol CPUPol;
84 typedef typename Impl::DynInstPtr DynInstPtr;
85 typedef typename Impl::O3CPU O3CPU;
87 typedef typename CPUPol::IQ IQ;
88 typedef typename CPUPol::RenameMap RenameMap;
89 typedef typename CPUPol::LSQ LSQ;
91 typedef typename CPUPol::TimeStruct TimeStruct;
92 typedef typename CPUPol::IEWStruct IEWStruct;
93 typedef typename CPUPol::RenameStruct RenameStruct;
94 typedef typename CPUPol::IssueStruct IssueStruct;
97 /** Overall IEW stage status. Used to determine if the CPU can
98 * deschedule itself due to a lack of activity.
105 /** Status for Issue, Execute, and Writeback stages. */
116 /** Overall stage status. */
118 /** Dispatch status. */
119 StageStatus dispatchStatus[Impl::MaxThreads];
120 /** Execute status. */
121 StageStatus exeStatus;
122 /** Writeback status. */
123 StageStatus wbStatus;
126 /** Constructs a DefaultIEW with the given parameters. */
127 DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
129 /** Returns the name of the DefaultIEW stage. */
130 std::string name() const;
132 /** Registers statistics. */
135 /** Initializes stage; sends back the number of free IQ and LSQ entries. */
138 /** Sets main time buffer used for backwards communication. */
139 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
141 /** Sets time buffer for getting instructions coming from rename. */
142 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
144 /** Sets time buffer to pass on instructions to commit. */
145 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
147 /** Sets pointer to list of active threads. */
148 void setActiveThreads(std::list<ThreadID> *at_ptr);
150 /** Sets pointer to the scoreboard. */
151 void setScoreboard(Scoreboard *sb_ptr);
153 /** Drains IEW stage. */
156 /** Resumes execution after a drain. */
159 /** Completes switch out of IEW stage. */
162 /** Takes over from another CPU's thread. */
165 /** Returns if IEW is switched out. */
166 bool isSwitchedOut() { return switchedOut; }
168 /** Squashes instructions in IEW for a specific thread. */
169 void squash(ThreadID tid);
171 /** Wakes all dependents of a completed instruction. */
172 void wakeDependents(DynInstPtr &inst);
174 /** Tells memory dependence unit that a memory instruction needs to be
175 * rescheduled. It will re-execute once replayMemInst() is called.
177 void rescheduleMemInst(DynInstPtr &inst);
179 /** Re-executes all rescheduled memory instructions. */
180 void replayMemInst(DynInstPtr &inst);
182 /** Sends an instruction to commit through the time buffer. */
183 void instToCommit(DynInstPtr &inst);
185 /** Inserts unused instructions of a thread into the skid buffer. */
186 void skidInsert(ThreadID tid);
188 /** Returns the max of the number of entries in all of the skid buffers. */
191 /** Returns if all of the skid buffers are empty. */
194 /** Updates overall IEW status based on all of the stages' statuses. */
197 /** Resets entries of the IQ and the LSQ. */
200 /** Tells the CPU to wakeup if it has descheduled itself due to no
201 * activity. Used mainly by the LdWritebackEvent.
205 /** Reports to the CPU that there is activity this cycle. */
206 void activityThisCycle();
208 /** Tells CPU that the IEW stage is active and running. */
209 inline void activateStage();
211 /** Tells CPU that the IEW stage is inactive and idle. */
212 inline void deactivateStage();
214 /** Returns if the LSQ has any stores to writeback. */
215 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
217 /** Returns if the LSQ has any stores to writeback. */
218 bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
220 void incrWb(InstSeqNum &sn)
222 if (++wbOutstanding == wbMax)
224 DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn);
225 assert(wbOutstanding <= wbMax);
231 void decrWb(InstSeqNum &sn)
233 if (wbOutstanding-- == wbMax)
235 DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn);
236 assert(wbOutstanding >= 0);
238 assert(wbList.find(sn) != wbList.end());
244 std::set<InstSeqNum> wbList;
248 std::set<InstSeqNum>::iterator wb_it = wbList.begin();
249 while (wb_it != wbList.end()) {
250 cprintf("[sn:%lli]\n",
257 bool canIssue() { return ableToIssue; }
261 /** Check misprediction */
262 void checkMisprediction(DynInstPtr &inst);
265 /** Sends commit proper information for a squash due to a branch
268 void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
270 /** Sends commit proper information for a squash due to a memory order
273 void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid);
275 /** Sends commit proper information for a squash due to memory becoming
276 * blocked (younger issued instructions must be retried).
278 void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid);
280 /** Sets Dispatch to blocked, and signals back to other stages to block. */
281 void block(ThreadID tid);
283 /** Unblocks Dispatch if the skid buffer is empty, and signals back to
284 * other stages to unblock.
286 void unblock(ThreadID tid);
288 /** Determines proper actions to take given Dispatch's status. */
289 void dispatch(ThreadID tid);
291 /** Dispatches instructions to IQ and LSQ. */
292 void dispatchInsts(ThreadID tid);
294 /** Executes instructions. In the case of memory operations, it informs the
295 * LSQ to execute the instructions. Also handles any redirects that occur
296 * due to the executed instructions.
300 /** Writebacks instructions. In our model, the instruction's execute()
301 * function atomically reads registers, executes, and writes registers.
302 * Thus this writeback only wakes up dependent instructions, and informs
303 * the scoreboard of registers becoming ready.
305 void writebackInsts();
307 /** Returns the number of valid, non-squashed instructions coming from
308 * rename to dispatch.
310 unsigned validInstsFromRename();
312 /** Reads the stall signals. */
313 void readStallSignals(ThreadID tid);
315 /** Checks if any of the stall conditions are currently true. */
316 bool checkStall(ThreadID tid);
318 /** Processes inputs and changes state accordingly. */
319 void checkSignalsAndUpdate(ThreadID tid);
321 /** Removes instructions from rename from a thread's instruction list. */
322 void emptyRenameInsts(ThreadID tid);
324 /** Sorts instructions coming from rename into lists separated by thread. */
328 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
329 * Writeback to run for one cycle.
334 /** Updates execution stats based on the instruction. */
335 void updateExeInstStats(DynInstPtr &inst);
337 /** Pointer to main time buffer used for backwards communication. */
338 TimeBuffer<TimeStruct> *timeBuffer;
340 /** Wire to write information heading to previous stages. */
341 typename TimeBuffer<TimeStruct>::wire toFetch;
343 /** Wire to get commit's output from backwards time buffer. */
344 typename TimeBuffer<TimeStruct>::wire fromCommit;
346 /** Wire to write information heading to previous stages. */
347 typename TimeBuffer<TimeStruct>::wire toRename;
349 /** Rename instruction queue interface. */
350 TimeBuffer<RenameStruct> *renameQueue;
352 /** Wire to get rename's output from rename queue. */
353 typename TimeBuffer<RenameStruct>::wire fromRename;
355 /** Issue stage queue. */
356 TimeBuffer<IssueStruct> issueToExecQueue;
358 /** Wire to read information from the issue stage time queue. */
359 typename TimeBuffer<IssueStruct>::wire fromIssue;
362 * IEW stage time buffer. Holds ROB indices of instructions that
363 * can be marked as completed.
365 TimeBuffer<IEWStruct> *iewQueue;
367 /** Wire to write infromation heading to commit. */
368 typename TimeBuffer<IEWStruct>::wire toCommit;
370 /** Queue of all instructions coming from rename this cycle. */
371 std::queue<DynInstPtr> insts[Impl::MaxThreads];
373 /** Skid buffer between rename and IEW. */
374 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
376 /** Scoreboard pointer. */
377 Scoreboard* scoreboard;
383 /** Records if IEW has written to the time buffer this cycle, so that the
384 * CPU can deschedule itself if there is no activity.
386 bool wroteToTimeBuffer;
388 /** Source of possible stalls. */
393 /** Stages that are telling IEW to stall. */
394 Stalls stalls[Impl::MaxThreads];
396 /** Debug function to print instructions that are issued this cycle. */
397 void printAvailableInsts();
400 /** Instruction queue. */
403 /** Load / store queue. */
406 /** Pointer to the functional unit pool. */
408 /** Records if the LSQ needs to be updated on the next cycle, so that
409 * IEW knows if there will be activity on the next cycle.
411 bool updateLSQNextCycle;
414 /** Records if there is a fetch redirect on this cycle for each thread. */
415 bool fetchRedirect[Impl::MaxThreads];
417 /** Records if the queues have been changed (inserted or issued insts),
418 * so that IEW knows to broadcast the updated amount of free entries.
422 /** Commit to IEW delay. */
423 Cycles commitToIEWDelay;
425 /** Rename to IEW delay. */
426 Cycles renameToIEWDelay;
429 * Issue to execute delay. What this actually represents is
430 * the amount of time it takes for an instruction to wake up, be
431 * scheduled, and sent to a FU for execution.
433 Cycles issueToExecuteDelay;
435 /** Width of dispatch, in instructions. */
436 unsigned dispatchWidth;
438 /** Width of issue, in instructions. */
441 /** Index into queue of instructions being written back. */
444 /** Cycle number within the queue of instructions being written back.
445 * Used in case there are too many instructions writing back at the current
446 * cycle and writesbacks need to be scheduled for the future. See comments
451 /** Number of instructions in flight that will writeback. */
453 /** Number of instructions in flight that will writeback. */
456 /** Writeback width. */
459 /** Writeback width * writeback depth, where writeback depth is
460 * the number of cycles of writing back instructions that can be
464 /** Number of active threads. */
467 /** Pointer to list of active threads. */
468 std::list<ThreadID> *activeThreads;
470 /** Maximum size of the skid buffer. */
471 unsigned skidBufferMax;
473 /** Is this stage switched out. */
476 /** Stat for total number of idle cycles. */
477 Stats::Scalar iewIdleCycles;
478 /** Stat for total number of squashing cycles. */
479 Stats::Scalar iewSquashCycles;
480 /** Stat for total number of blocking cycles. */
481 Stats::Scalar iewBlockCycles;
482 /** Stat for total number of unblocking cycles. */
483 Stats::Scalar iewUnblockCycles;
484 /** Stat for total number of instructions dispatched. */
485 Stats::Scalar iewDispatchedInsts;
486 /** Stat for total number of squashed instructions dispatch skips. */
487 Stats::Scalar iewDispSquashedInsts;
488 /** Stat for total number of dispatched load instructions. */
489 Stats::Scalar iewDispLoadInsts;
490 /** Stat for total number of dispatched store instructions. */
491 Stats::Scalar iewDispStoreInsts;
492 /** Stat for total number of dispatched non speculative instructions. */
493 Stats::Scalar iewDispNonSpecInsts;
494 /** Stat for number of times the IQ becomes full. */
495 Stats::Scalar iewIQFullEvents;
496 /** Stat for number of times the LSQ becomes full. */
497 Stats::Scalar iewLSQFullEvents;
498 /** Stat for total number of memory ordering violation events. */
499 Stats::Scalar memOrderViolationEvents;
500 /** Stat for total number of incorrect predicted taken branches. */
501 Stats::Scalar predictedTakenIncorrect;
502 /** Stat for total number of incorrect predicted not taken branches. */
503 Stats::Scalar predictedNotTakenIncorrect;
504 /** Stat for total number of mispredicted branches detected at execute. */
505 Stats::Formula branchMispredicts;
507 /** Stat for total number of executed instructions. */
508 Stats::Scalar iewExecutedInsts;
509 /** Stat for total number of executed load instructions. */
510 Stats::Vector iewExecLoadInsts;
511 /** Stat for total number of executed store instructions. */
512 // Stats::Scalar iewExecStoreInsts;
513 /** Stat for total number of squashed instructions skipped at execute. */
514 Stats::Scalar iewExecSquashedInsts;
515 /** Number of executed software prefetches. */
516 Stats::Vector iewExecutedSwp;
517 /** Number of executed nops. */
518 Stats::Vector iewExecutedNop;
519 /** Number of executed meomory references. */
520 Stats::Vector iewExecutedRefs;
521 /** Number of executed branches. */
522 Stats::Vector iewExecutedBranches;
523 /** Number of executed store instructions. */
524 Stats::Formula iewExecStoreInsts;
525 /** Number of instructions executed per cycle. */
526 Stats::Formula iewExecRate;
528 /** Number of instructions sent to commit. */
529 Stats::Vector iewInstsToCommit;
530 /** Number of instructions that writeback. */
531 Stats::Vector writebackCount;
532 /** Number of instructions that wake consumers. */
533 Stats::Vector producerInst;
534 /** Number of instructions that wake up from producers. */
535 Stats::Vector consumerInst;
536 /** Number of instructions that were delayed in writing back due
537 * to resource contention.
539 Stats::Vector wbPenalized;
540 /** Number of instructions per cycle written back. */
541 Stats::Formula wbRate;
542 /** Average number of woken instructions per writeback. */
543 Stats::Formula wbFanout;
544 /** Number of instructions per cycle delayed in writing back . */
545 Stats::Formula wbPenalizedRate;
548 #endif // __CPU_O3_IEW_HH__